DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 9,026,962 to Kruberg et al. (“Kruberg”).
As to independent claim 1 and similarly recited independent claims 9 and 17, an apparatus/method/system (2:29-44) comprising: a processor a non-transitory, machine-readable medium including instructions wherein the instructions, when loaded and executed by the processor, cause the processor to build system-level designs made up of electrical components that have cross-block or cross-function dependencies (3:1-6, 5:3-15. “modules” correspond to “electrical components”. Their EIS defines dependencies (e.g., power, bus signals).) by: presenting a system diagram of an electronic system having component blocks representing electrical components (6:41-47. The displayed board with drag-and-drop module icons is a “system diagram” with blocks for electrical components.); receiving constraints or parameters for each electrical component represented by the component blocks (6:54-58, 8:2-21. “EIS requirements and providers” correspond to “constraints or parameters”. When a module is added, its EIS constraints (voltage, signals, capacity, etc.) are received and recorded by the system.); presenting a list of candidate components corresponding to the constraints or parameters for each electrical component represented by the component blocks (6:54-64, 29:63-67. System shows a list of modules that satisfy constraints when requirements are unmet. This corresponds to presenting candidate components corresponding to parameters.); receiving an instruction to select a component from the list candidate components for each electrical component represented by the component blocks (29:63-67. Clicking and adding a selected module from the list corresponds to “receiving an instruction to select a component”.); and checking system cross-block or cross-function dependencies for all electrical components selected for inclusion in the system diagram (6:56-64, 8:17-21. EIS validity check ensures all dependencies between blocks are satisfied (“checking cross-block or cross-function dependencies”).).
As to claim 2 and similarly recited claim 10, the apparatus of claim 1, wherein the presenting of a system diagram of an electronic system comprises presenting a template diagram (6:50-57, 29:55-60, 30:1-3. Design area/board image serves as a template diagram onto which components are placed. System also provides pre-structured modules (functional templates) from the library.).
As to claim 3 and similarly recited clams 11 and 18, the apparatus of claim 1, wherein the receiving constraints or parameters comprises receiving constraints or parameters selected from power, bandwidth, and noise (8:1-8, 27-67. EIS encodes power requirements (e.g., voltage level, capacity). Furthermore, EIS conceptually allows specifying other constraints (e.g., bandwidth would be part of the bus properties, noise would be tied to signal integrity or LVS properties.).).
As to claim 4 and similarly recited claim 12, the apparatus of claim 1, wherein the instructions, when loaded and executed by the processor, cause the processor to build the system-level designs by receiving an instruction to modify a component block by selecting a new electrical component (5:1-12, 29:64-67. When a module’s requirements are unsatisfied, system allows user to pick a different module to resolve the issue. This corresponds to “modify a component block by selecting a new electrical component”.).
As to claim 5 and similarly recited claim 13, the apparatus of claim 1, further comprising instructions, when loaded and executed by a processor, cause the processor to build system-level designs by adding a component block to the system diagram (6:54-57).
As to claim 6 and similarly recited claim 14, the apparatus of claim 1, further comprising instructions, when loaded and executed by a processor, configure the processor to build system-level designs by removing a component block from the system diagram (4:63-67, 6:50-54. Adding and removing modules is explicitly disclosed.).
As to claim 7 and similarly recited claim 15, the apparatus of claim 1, further comprising instructions, when loaded and executed by a processor, configure the processor to build system-level designs by outputting a description of the electrical components of the system diagram (5-15-20, 44-52.).
As to claim 8 and similarly recited claims 16 and 19, the apparatus of claim 7, wherein the description of the electrical components of the system diagram is selected from a diagram, a schematic, a bill of materials, a printed circuit board layout, and software (5-15-20, 44-52.).
As to claim 20, the system of claim 17, wherein the dependencies checked by the system dependency circuit are selected from power, communication, digital control, security, clock, and memory (8:14-67. Explicitly checks power and communication dependencies. Inherently checks clock (via I2C/UART), digital control (via GPIO), and memory because memory modules are selectable and must meet bus/power dependencies.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SURESH MEMULA/Primary Examiner, Art Unit 2851