DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 10, 19, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. No. US Pub. No. 2022/0367439 to Kang (“Kang”).
As to independent claim 1, a transistor cell (¶ 0003, 0029. Kang discloses ICs comprising standard cells, the standard cells form transistors.) comprising: a first transistor comprising a portion of a first diffusion region of a first type, the first diffusion region extending in a first direction (¶ 0041. Kang teaches a first active region RX1 extending in the X-axis direction. The first active region RX1 is formed in an N-well to for a P-type transistor.); a second transistor comprising a portion of a second diffusion region of a second type, the second diffusion region extending in the first direction (¶ 0041. Kang teaches a second active region RX2 extending in the X-axis direction. The second active region RX2 is formed in P-SUB to form an N-type transistor.); and a metal layer over the first transistor and the second transistor, the metal layer comprising a plurality of routing tracks arranged at a first pitch, each routing track extending in the first direction (¶ 0041, Fig. 4-6. Kang teaches a first metal layer M1 having patterns that extend in the X-axis direction, which is the same direction as the active regions. Fig. 4-6 show M1 comprises a plurality of routing tracks (TR1-TR5) arranged at a pitch.); wherein: a first routing track is over the first diffusion region (Fig. 4-6. TR2 is physically located over the first active region RX1.); a second routing track is over the second diffusion region (Fig. 4-6. TR4 is physically located over the second active region RX2.); and a third routing track is between the first diffusion region and the second diffusion region, and the third routing track is adjacent to the first routing track and the second routing track (Fig. 4-6. TR3 is physically located directly between RX1 and RX2. Furthermore, TR3 is strictly adjacent to TR2 and TR4 without any intervening tracks.).
As to claim 5, the transistor cell of claim 1, further comprising a third transistor (¶ 0090, 0091. Kang teaches standard cells implementing NAND circuits, including NAND4, and states the NAND4 circuit includes four N-type transistors and four P-type transistors.) comprising a second portion of the first diffusion region (¶ 0029, 0041. Adjacent transistors of the same type share a continuous active region.), the first transistor having a first gate (Fig. 13: CN21), and the third transistor having a second gate (Fig. 13: CN22), the first gate and the second gate arranged at a second pitch (Fig. 13, 14B, 15B, 15C disclose multiple parallel gate lines arranged at a consistent, regular pitch from one another.).
As to claim 10, the transistor cell of claim 1, wherein a metal region in the first routing track over the first diffusion region is coupled to a source or drain in the second diffusion region (¶ 0064-0066. Kang teaches a routing line connected to the active contact CA may be formed in at least one of the first to fifth tracks TR1 to TR5, the active contact CA may be formed to contact source/drain regions SD2 of the second active region RX2, and Kang further shows a first metal layer M1 routing line can be connected to the active contact CA.).
As to claim 19, a method for forming a device (¶ 0002), the method comprising: forming a first transistor comprising a portion of a first diffusion region of a first type, the first diffusion region extending in a first direction (¶ 0041. Kang teaches a first active region RX1 extending in the X-axis direction. The first active region RX1 is formed in an N-well to for a P-type transistor.); forming a second transistor comprising a portion of a second diffusion region of a second type, the second diffusion region extending in the first direction (¶ 0041. Kang teaches a second active region RX2 extending in the X-axis direction. The second active region RX2 is formed in P-SUB to form an N-type transistor.); forming a first metal line over the first transistor (¶ 0030, 0041, 0055. Kang teaches forming routing lines on specific tracks, such as TR2, which is located over the RX1.); forming a second metal line over the second transistor (¶ 0030, 0041, 0055. Kang teaches forming a routing line on TR4, which is located over RX2.); and forming a third metal line in a same layer as the first metal line and the second metal line, the third metal line adjacent to the first metal line and the second metal line, the third metal line not over the first transistor or the second transistor (Fig. 4-6. TR3 is physically located directly between RX1 and RX2. Furthermore, TR3 is strictly adjacent to TR2 and TR4 without any intervening tracks. Because TR3 is situated in the space between RX1 and RX2 the metal line formed on TR3 is not over the first transistor or the second transistor.).
As to claim 20, the method of claim 19, further comprising forming a plurality of metal lines over the first metal line, second metal line, and third metal line, the plurality of metal lines extending perpendicular to the first metal line, second metal line, and third metal line (Fig. 16: S55, ¶ 0030. M2 patterns are perpendicular to M1 patterns.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of US Pub. No. 2020/0373242 to Hiblot et al. (“Hiblot”).
Kang teaches the transistor cell of claim 1. Kang, however, does not explicitly teach the source is coupled to a back side metal layer under the transistor.
Hiblot teaches an IC chip having at least part of power delivery network on a back side of a substrate, including a power supply terminal and a reference terminal located at the back side, and TSV connections through the substrate configured to supply power from the backside terminals to active devices at the front side (Abstract.). Thus, Hiblot teaches coupling device regions (including transistor terminals) to a backside interconnect/metal level (i.e., a back side metal layer) beneath the front side active devices via TSV based connections (¶ 0008-0015).
It would have been obvious to a POSITA to modify Kang’s standard cell implementation to utilize Hiblot’s backside PDN/backside metal arrangement to couple the cell’s source to a back side metal layer under the transistor. The combination would have predictably reduced front side metal routing congestion and improved power delivery efficiency.
As to claim 4, the transistor cell of claim 2, further comprising a backside contact coupling the source to the back side metal layer (¶ 0016-0018, 0028, 0029, 0035-0037. Active region of the footer/header transistor that receives power from the PDC is the source terminal and Hiblot bridges the front side active regions to the backside PDN using TSV and buried vertical contacts.).
Claims 13- 15, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view US Pub. No. 2017/0358565 to Hensel et al. (“Hensel”).
As to claim 13, Kang teaches: A device (¶ 0033. IC 10 includes plurality of standard cells, e.g., C1 and C2.) comprising: a first cell (e.g., C1) comprising a first transistor having a first gate and a second transistor having a second gate, the first gate and the second gate arranged along a gate line extending in a first direction (¶ 0041, 0053. Kang teaches standard cells (e.g., STC1, STC2) include a first active region RX1 (forming a P-type transistor) and a second active region RX2 (forming an N-type transistor). These transistors share a continuous gate line that extends in the Y-axis direction.); a second cell (e.g., C2) comprising a third transistor having a third gate and a fourth transistor having a fourth gate, (¶ 0033, 0041, 0053. Kang’s IC includes multiple standard cells, and the same transistor forming structure applies to each standard cell: active region and gate line form a transistor. Thus, the second cell likewise includes transistor having gates on its gate line.); and a metal layer over the first cell and the second cell, the metal layer comprising a plurality of routing tracks arranged at a first pitch, each routing track extending in a second direction perpendicular to the first direction (¶ 0030, 0041, 0055. Kang teaches a first metal layer M1 with patterns extending in the X-axis direction and a gate line extending in the Y-axis direction, and a plurality of tracks TR1-TR5 in which patterns of M1 are arranged, with conductive patterns extending in the X-axis direction formed in the tracks. See track grid structure in Fig. 4-6 for “pitch”. ), and the plurality of routing tracks comprising: a first routing track over the first gate (Fig. 4-6. Because Kang’s track extends perpendicularly across the gate line, the track TR2 crosses directly over the gate line at the location of the first active region RX1 (the first gate).); a second routing track over the second gate (Fig. 4-6. Similarly, Kang’s track TR4 extends in the X-axis and crosses directly over the gate line at the location of the second active region RX2 (the second gate).); and a third routing track between and adjacent to the first routing track and the second routing track (Fig. 4-6. Kang’s TR3 crosses the gate line between the two active regions, RX1 and RX2, and adjacent to both TR2 and TR4.).
Kang’s figures illustrate single rows of standard cells bounded by power line PL1 and PL2, where the gate lines terminate at or within the cell boundaries. Kang, however, does not expressly depict a gate line continuing across the boundary into another cell.
Hensel is directed to a standard cell layout (¶ 0001). Hensel teaches gate lines that disposed over boundaries of standard cells (¶ 0040).
It would have been obvious to a POSITA to implement Kang’s plurality of standard cells such that a gate line extends across the boundary between adjacent cells, as taught by Hensel, in order to provide a second cell whose transistor gates are also arranged along that same gate line. The implementation is a known and predictable layout choice in standard cell design consistent with Kang’s goal of easing routing/congestion.
As to claim 14, the device of claim 13, the plurality of routing tracks further comprising a fourth routing track over the third gate (Kang: ¶ 0055, Hensel: ¶ 0040. Kang provides multiple tracks (TR1-TR5) for routing lines and those tracks run perpendicular to the gate line that extends across the standard cell boundaries in view of Hensel.).
As to claim 15, the device of claim 14, wherein the fourth routing track is adjacent to the first routing track (Kang: Fig. 4: TR1 (fourth track) is adjacent TR2).
As to claim 17, the device of claim 13, the first transistor further comprising a source or drain region, the first cell further comprising a fifth transistor comprising: the source or drain region of the first transistor; and a fifth gate (Kang: Fig. 13, 14. Kang’s specification details multi-input standard cells that contain more than two transistors. Fig. 13 shows NAND2 standard cell includes two P-type transistors and two N-type transistors, and Fig. 14 shows NAND4 standard cell includes four P-type transistors and four N-type transistors. Looking at CN41 in Fig. 14B, there are four distinct, parallel gate lines (IPA, IPB, IPC, and IPD) crossing the first active region RX1. If the transistor formed by gate IPA is the “first transistor” then the adjacent transistor formed by gate IPB serves as the “fifth transistor” having a “fifth gate”. Furthermore, RX1 is continuous structure extending in the X-axis direction. The segment of the active region situated between gate line IPA and gate line IPB acts as the shared source or drain region for both transistors.).
As to claim 18, the device of claim 17, the second transistor further comprising a second source or drain region, the first cell further comprising a sixth transistor comprising: the second source or drain region of the second transistor; and a sixth gate (Kang: Fig. 13 and 14. Similar analysis to claim 17 above. ¶ 0048, 0065. Kang teaches RX2 includes source/drain regions (e.g., SD2) formed over the fins or nanosheets. Kang’s multi-input standard cells, such as NAND2 and NAND4, feature continuous gate lines that cross both active regions. In standard cell CN41, parallel gates lines IPA and IPB both cross the second active region RX2. If the “second transistor” is formed by gate IPA over RX2, then the adjacent transistor formed by gate IPB (“sixth gate”) over that same active region RX2 serves as the “sixth transistor”. Furthermore, RX2 is a continuous structure extending in the X-axis direction. The segment of the active region RX2 physical located between gate line IPA and gate line IPB acts as the shared source or drain region for both of these adjacent N-type transistors.).
Allowable Subject Matter
Claims 3, 6-9, 11, 12, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3, 6-9, 11, 12, and 16 would be allowable if rewritten in the manner above because the prior art of record does not teach or suggest a transistor cell, device, or method having all the combinations of elements or steps as required by and recited in claims 3, 6, 7, 8, 9, 11, or 16. Claims 12 depends from claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851