DETAILED ACTION This is the initial Office action b ased on the application filed December 20, 2022 . Claims 2 1- 40 are pending and have been examined. Claims 1-20 have been canceled by preliminary amendment. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The Information Disclosure Statement filed 12/20/2022 has been considered. An initialed copy of Form 1449 is enclosed herewith. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 7-10, and 14-16 of U.S. Patent No. 11 , 544 , 121 (hereinafter the reference patent ). Although the claims at issue are not identical, they are not patentably distinct from each other because the examined application claim is anticipated by the reference claims. The examined application claim s are anticipated by the claims in the reference patent, because all the features recited in claims 21-40 of this application can also be found in the claims of the reference patent as per the following mappings. Claim s 1, 2, 2, 3, 7, 1, 3, 3, 8, 9, 9, 10, 14, 8, 10, 10, 15, 16, 16, and 15 of the reference patent anticipate the examined application’s claims 21-40 , respectively. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 21-40 are rejected under 35 U.S.C. 103 as being unpatentable over MacNamara (US 2018/0004693 ) in view of Black ( US 6,742,017 ). Regarding claim 2 1, MacNamara discloses: detect an indication of a network task (see at least figure 4A and paragraph 28, RX and TX packet indication) […] ; and process the network task, without involving an external processor, to generate a network message […] that is compatible with a network communication protocol of a network interface unit (see at least paragraph 17 , accelerator 110 is a GPU ; paragraph 2 1 , The accelerator 110 can include processing circuitry 206 that generates processed data packets by implementing packet processing functions on the data packets received from the NIC 108. ; paragraph 2 6 , GPU includes transport agent to transport packets to and from the NIC ; paragraph 39 , the GPU receives data packets, processes the data packets, and transmits the processed data packets to the NIC for transmission to the network ; paragraph 19, data packets can be transferred from the NIC to the GPU and back to the NIC without entering the cores 106 [of a CPU] ) However MacNamara does not explicitly disclose, but Black discloses: detect an indication […] in a cache (see at least col 3: 1-25, polling the cache memory ) network message comprising a payload and a first command (see at least col 17: 50-65, message with a payload and command ) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify MacNamara by adapting the teachings of Black to include polling cache memory and data packet contents . MacNamara discloses receiving packet indications via polling (¶28) and Black discloses the polling of cache memory. The combination allows for detecting important information in various storage locations including a cache . Regarding claim 2 2 , the rejection of claim 2 1 is incorporated . However MacNamara does not explicitly disclose, but Black discloses : wherein the network message comprises identifying information that causes the network message to be routed to a specific network interface on a network interface card (see at least col 10: 25-35, MAC packet with a destination address ) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify MacNamara by adapting the teachings of Black to include MAC packets . The combination allows for increased bandwidth of the system interface (Black col 3: 42-48) . Regarding claim 2 3 , the rejection of claim 22 is incorporated . However MacNamara does not explicitly disclose, but Black discloses : wherein the identifying information comprises source and destination media access control addresses (see at least col 10: 25-35, MAC packet with a source and destination address ) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify MacNamara by adapting the teachings of Black to include MAC packets. The combination allows for increased bandwidth of the system interface (Black col 3: 42-48). Regarding claim 2 4 , the rejection of claim 23 is incorporated . However MacNamara does not explicitly disclose, but Black discloses : wherein the circuitry is configured to translate a command in the network message to a different command using a network stack that supports the network communication protocol (see at least col 11: 64- col 12: 27, protocol translator ) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MacNamara and Black for the reasons listed above . Regarding claim 2 5 , the rejection of claim 21 is incorporated, and MacNamara further discloses: wherein the circuitry is included in a graphics processing unit (see at least paragraph 17, accelerator 110 is a GPU ) Regarding claim 2 6 , the rejection of claim 25 is incorporated, and MacNamara further discloses: wherein the processor is a graphics processing unit and the circuitry is included in a command processor of the graphics processing unit (see at least paragraph 17, accelerator 110 is a GPU ; figure 2 ; paragraph 21, processing circuitry 206 ) Regarding claim 2 7 , the rejection of claim 26 is incorporated, and MacNamara further discloses: wherein the command processor is configured to execute code of a network stack (see at least figure 3; paragraphs 23-26, functionality of the GPU including packet scheduling, packet traffic management, packet encryption and decryption, and other packet processing ) Regarding claim 2 8 , the rejection of claim 27 is incorporated, and MacNamara further discloses: wherein the network stack is executable to process network operations generated by threads executing on compute units of the graphics processing unit (see at least figure 3; paragraphs 23-26, functionality of the GPU including packet scheduling, packet traffic management, packet encryption and decryption, and other packet processing ) Regarding claims 7 and 8, the scope of the instant claims does not differ substantially from that of claims 3 and 4. Accordingly, claims 29-36 are rejected for the same reasons as claims 21-28 , respectively , claim 37 is rejected for the same reasons as claims 21 and 25, and claims 38-40 are rejected for the same reasons as claims 22, 23, and 26 , respectively . Examiner’s Note Claims 21 and 29 do not require a graphics processor and can be interpreted more broadly than the art citations provided above. For example, as noted in the background of the examined application CPUs can traditionally generate network messages and interact with the network interface. Potential art to read on these claims could include a CPU, without involving a separate CPU, detecting a network task and processing the task to generate a network message to send to the network interface. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Agostini discloses GPUDirect Async which removes dependency on the CPU by enabling the GPU to trigger communication on the HCA. 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