DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9-10, 14-16, 24, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ballani et al. (US Pub. No. 2022/0141558), hereinafter referred to as Ballani.
Referring to claim 1, Ballani discloses a mirrored switch configuration (fig. 1-5), the switch configuration comprising: at least two switches (fig. 1A-B, 102(1-n)), each having corresponding baseline bandwidths and corresponding radix and port configurations (radix of…network switch…bandwidth that can be supported; [0043-0045]); a plurality of links, and a host fabric interface adapter ('HFA') (fig. 1A-B, interfaces 104) including an interconnect adapted to receive, from corresponding ports of the at least two switches, one link from one port of one of the at least two switches and one link from a corresponding port of another of the at least two switches (Each computing node includes a plurality of node interfaces 104. In the depicted network 100, each computing node includes a distinct node interface 104 for each network switch 102, [0052]).
As to claim 9, Ballani discloses the at least two switches comprise three or more switches (fig. 4-5, [0125-0127]).
Referring to claim 10, Ballani discloses a host fabric adapter (fig. 1A-B, interfaces 104) comprising: a high-speed serial computer expansion bus (serial data stream that is transmitted over a high-speed connection to a receiver, [0002]; [0068-0069]); at least two dedicated ports configured to receive links from corresponding ports of at least two switches (Each computing node includes a plurality of node interfaces 104. In the depicted network 100, each computing node includes a distinct node interface 104 for each network switch 102, [0052]); each of the at least two switches comprising corresponding switches in parallel and independent topologies (fig. 1-5).
As to claim 14, Ballani discloses the host fabric adapter, the compute node, the switches, and the links are components of a fabric of a high-performance computing environment ([0002], [0068-0069]).
Referring to claim 15, Ballani discloses a high-performance computing environment (fig. 1-5) comprising: a fabric comprising a plurality of switches (fig. 1A-B, 102(1-n)) and links configured into at least two parallel and independent topologies (fig. 1-5, [0050], [0078-0079]), the switches each having corresponding baseline bandwidths and corresponding radix and port configurations (radix of…network switch…number of input ports and output ports…bandwidth that can be supported; [0043-0045]); a plurality of compute nodes each including a host fabric adapter adapted (fig. 1A-B, interfaces 104) for data transfer through ports dedicated to each of the topologies (Each computing node includes a plurality of node interfaces 104. In the depicted network 100, each computing node includes a distinct node interface 104 for each network switch 102, [0052]).
As to claim 16, Ballani discloses the host fabric adapter includes a high-speed serial computer expansion bus and at least two ports configured to receive links from corresponding ports of at least two switches ([0002], [0068-0069]).
Referring to claim 24, Ballani discloses a method of configuring a fabric for a high-performance computing environment, the method comprising: selecting a plurality of switches (fig. 1A-B, 102(1-n)) and links (fig. 1-5, [0050], [0078-0079]), each switch having corresponding baseline bandwidths and corresponding radix, and port configurations (radix of…network switch…number of input ports and output ports…bandwidth that can be supported; [0043-0045]); arranging the plurality of switches and links into at least two corresponding parallel and independent topologies (fig. 1-5, [0050], [0078-0079]); connecting corresponding ports of corresponding switches of each independent topology with a plurality of compute nodes, wherein each compute node has a host fabric adapter with a dedicated port adapted to independently transmit and receive data to a particular topology (Each computing node includes a plurality of node interfaces 104. In the depicted network 100, each computing node includes a distinct node interface 104 for each network switch 102, [0052]).
As to claim 26, Ballani discloses the host fabric adapter comprises a dedicated port adapted to independently transmit and receive data to each parallel and independent topology (Each computing node includes a plurality of node interfaces 104. In the depicted network 100, each computing node includes a distinct node interface 104 for each network switch 102, [0052]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Ballani in view of Rivaud et al. (US Pub. No. 2023/0010285), hereinafter referred to as Rivaud.
As to claims 2 and 25, Ballani discloses the one link from one port of one of the at least two switches and the one link from a corresponding port of another of the at least two switches is implemented through a cable adapted for the HFA and the at least two switches ([0061]).
Ballani does not appear to explicitly disclose the cable is a double density cable.
However, Rivaud discloses a double density cable ([0034]).
Ballani and Rivaud are analogous art because they are from the same field of endeavor, network interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ballani and Rivaud before him or her, to substitute the cabling of Ballani with the double density cabling taught by Rivaud because Ballani contained a device (method, product, etc.) which differed from the claimed device by the substitution of one network cabling with another (i.e. double density cabling), Rivaud demonstrates that that substituted double density cabling and its functions were known in the art, one of ordinary skill in the art could have substituted one known network cabling for another, and the results of the substitution would have been a predictable network interconnect.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art. If any of these findings cannot be made, then this rationale cannot be used to support a conclusion that the claim would have been obvious to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Ballani and Rivaud to obtain the invention as specified in the instant claim.
Claims 3-7, 11, 17-18, 21-23, and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Ballani in view of Singh et al. (US Pub. No. 2022/0353197), hereinafter referred to as Singh.
As to claims 3, Ballani discloses the HFA is coupled with a compute node and configured to administer traffic through the HFA to the at least two switches (Each computing node includes a plurality of node interfaces 104. In the depicted network 100, each computing node includes a distinct node interface 104 for each network switch 102, [0052]).
Ballani does not appear to explicitly disclose the compute node comprises a processor and memory and a pipeline administration module stored in memory configured to administer packet traffic.
However, Singh discloses compute node comprises a processor and memory and a pipeline administration module stored in memory configured to administer packet traffic ([0051], [0181]).
Ballani and Singh are analogous art because they are from the same field of endeavor, network interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ballani and Singh before him or her, to modify the network interconnect of Ballani to include the network traffic management of Singh in order to manage the network performance.
The suggestion/motivation for doing so would have been optimize network packet processing (Singh: [0040]).
Therefore, it would have been obvious to combine Ballani and Singh to obtain the invention as specified in the instant claim.
As to claim 4, while Ballani teaches selectively administer traffic among the at least two switches, Ballani does not appear to explicitly disclose the pipeline administration module is further configured to selectively administer packet traffic among the at least two switches.
However, Singh discloses the pipeline administration module is further configured to selectively administer packet traffic among the at least two switches (load-balancing, [0051]).
The suggestion/motivation to combine remains as indicated above.
As to claim 5, the combination of Ballani in view of Sing discloses the pipeline administration module is further configured to load balance packet traffic among the at least two switches (Singh: load-balancing, [0051]). The suggestion/motivation to combine remains as indicated above.
As to claims 6, 11, 17, and 27, the combination of Ballani in view of Sing discloses the HFA includes steering logic configured to selectively route packets among the ports to the switches (Singh: a particular processor of the programming data plane 102 may determine (e.g., based on executing a load-balancing algorithm) which data path to route a particular packet., [0051]). The suggestion/motivation to combine remains as indicated above.
As to claims 7, 18, and 28, the combination of Ballani in view of Sing discloses the HFA includes steering logic configured to load balance packet traffic among the ports to the switches (Singh: a particular processor of the programming data plane 102 may determine (e.g., based on executing a load-balancing algorithm) which data path to route a particular packet., [0051]). The suggestion/motivation to combine remains as indicated above.
As to claim 21, Ballani discloses the compute node configured to administer traffic through the host fabric adapter to the at least two parallel and independent topologies (Each computing node includes a plurality of node interfaces 104. In the depicted network 100, each computing node includes a distinct node interface 104 for each network switch 102, [0052]).
Ballani does not appear to explicitly disclose the compute node comprises a processor and memory and a pipeline administration module stored in memory configured to administer packet traffic.
However, Singh discloses the compute node comprises a processor and memory and a pipeline administration module stored in memory configured to administer packet traffic ([0051], [0181]).
Ballani and Singh are analogous art because they are from the same field of endeavor, network interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ballani and Singh before him or her, to modify the network interconnect of Ballani to include the network traffic management of Singh in order to manage the network performance.
The suggestion/motivation for doing so would have been optimize network packet processing (Singh: [0040]).
Therefore, it would have been obvious to combine Ballani and Singh to obtain the invention as specified in the instant claim.
As to claim 22, Ballani discloses module is further configured to administer traffic among the at least two parallel and independent topologies (Each computing node includes a plurality of node interfaces 104. In the depicted network 100, each computing node includes a distinct node interface 104 for each network switch 102, [0052]).
Ballani does not appear to explicitly disclose the pipeline administration module is further configured to administer packet traffic.
However, Singh discloses the pipeline administration module is further configured to administer packet traffic ([0051], [0181]).
The suggestion/motivation to combine remains as indicated above.
As to claim 23, the combination of Ballani in view of Sing discloses the pipeline administration module is further configured to load balance packet traffic among the at least two parallel and independent topologies (Singh: load-balancing, [0051]). The suggestion/motivation to combine remains as indicated above.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ballani in view of Vieregge et al. (US Pub. No. 2003/0120983), hereinafter referred to as Vieregge.
As to claim 8, while Ballani teaches the mirrored switch configuration retains the reach of the baseline links (fig. 2, destination computing node, [0052]), Ballani does not appear to disclose retaining a raw bit error rate.
However, Vieregge discloses retaining a raw bit error rate ([0017]).
Ballani and Vieregge are analogous art because they are from the same field of endeavor, network interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ballani and Vieregge before him or her, to modify the network of Ballani to include the path quality monitoring of Vieregge to assist in connection routing decisions.
The suggestion/motivation for doing so would have been to encourage the use of favorable links (Vieregge: [0017]).
Therefore, it would have been obvious to combine Ballani and Vieregge to obtain the invention as specified in the instant claim.
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ballani in view of Goel et al. (US Pub. No. 2019/0104206), hereinafter referred to as Goel.
As to claims 12 and 19, while Ballani discloses the high-speed serial computer expansion bus is bus coupled for data communications with a compute node, Ballani does not appear to explicitly disclose a Peripheral Component Interconnect Express bus.
However, Goel discloses a Peripheral Component Interconnect Express bus ([0091]).
Ballani and Goel are analogous art because they are from the same field of endeavor, network interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ballani and Goel before him or her, to substitute bus interconnect of Ballani with the PCIe interconnect of Goel because Ballani contained a device (method, product, etc.) which differed from the claimed device by the substitution of one bus with another (i.e. PCIe), Goel demonstrates that that substituted PCIe and its functions were known in the art, one of ordinary skill in the art could have substituted one known bus for another, and the results of the substitution would have been a predictable bus interconnect.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art. If any of these findings cannot be made, then this rationale cannot be used to support a conclusion that the claim would have been obvious to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Ballani and Goel to obtain the invention as specified in the instant claim.
Claims 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ballani in view of Banerjee et al. (US Pub. No. 2023/0116820), hereinafter referred to as Banerjee.
As to claims 13 and 20, while Ballani discloses the high-speed serial computer expansion bus is coupled for data communications with a compute node, Ballani does not appear to explicitly disclose a Compute Express Link bus.
However, Banerjee discloses a Compute Express Link bus ([0015], [0018]).
Ballani and Banerjee are analogous art because they are from the same field of endeavor, network interconnects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ballani and Banerjee before him or her, to substitute bus interconnect of Ballani with the CXL interconnect of Banerjee because Ballani contained a device (method, product, etc.) which differed from the claimed device by the substitution of one bus with another (i.e. CXL), Banerjee demonstrates that that substituted CXL and its functions were known in the art, one of ordinary skill in the art could have substituted one known bus for another, and the results of the substitution would have been a predictable bus interconnect.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art. If any of these findings cannot be made, then this rationale cannot be used to support a conclusion that the claim would have been obvious to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Ballani and Banerjee to obtain the invention as specified in the instant claim.
Response to Arguments
Applicant's arguments filed 1/26/2026 have been fully considered but they are not persuasive.
With respect to independent claim 1, rejected under 35 U.S.C. 102 as being anticipated by Ballani, the applicant asserts:
“The Office Action's interpretation that the "combination of node interfaces" constitutes the claimed HFA is incorrect under the broadest reasonable interpretation...the claimed HFA is a single integrated device…components are integrated within one physical adapter device that connects to the compute node via a single PCle interconnect.
…Examiner's prior assertion that "the combination of node interfaces" constitutes the claimed HFA is incorrect. Instead, Ballani discloses a conventional configuration where each compute node interface has a direct connection to a single switch interface. Ballani's "plurality of node interfaces 104" are separate, distinct interface devices as stated in Paragraph [0052] As recognized in the Office Action, Ballani fails to anticipate claim 1 stating at page 3, "each computing node [of Ballani] includes a distinct node interface 104 for each network switch 102." The Office Action's recognition of the one-to-one relationship between node interfaces and network switches in Ballani, is supported by the cited paragraph.
… Ballani does not disclose or suggest integrating multiple ports within a single adapter device. The Office Action's reading conflates "functional result (connecting a node to multiple switches) with "structural implementation" (a single integrated adapter with multiple ports).
Under BRI, a "host fabric adapter" means a single device, not an ad hoc collection of separate interface cards.”
The Examiner respectfully disagrees. First, it is noted that the configuration upon which applicant relies (i.e., “the claimed HFA is a single integrated device” and “a "host fabric adapter" means a single device”) is not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). What is claimed of the HFA is that it includes “an interconnect adapted to receive, from corresponding ports of the at least two switches, one link from one port of one of the at least two switches and one link from a corresponding port of another of the at least two switches”, and Ballani discloses a parallel computing node (see C1/C2/Ck of fig. 1A) is connected to a plurality of network switches (see 1021-n of fig. 1A-B) by a plurality of node interfaces (see 10411-1041n of fig. 1A-B) which teaches “an interconnect adapted to receive”, each network switch 1021-n includes a respective switch interface 10611-1061n which teaches “corresponding ports of the at least two switches”, and each node interface 10411-1041n connects in a “one-to-one relationship” to a respective switch interface 10611-1061n of the network switches 1021-n which teaches “adapted to receive…one link from one port of one of the at least two switches and one link from a corresponding port of another of the at least two switches.”
With respect to independent claim 15, rejected under 35 U.S.C. 102 as being anticipated by Ballani, the applicant asserts:
“…the figures and supporting disclosure of Ballani describe a set of switches that are a single topology-not a plurality of topologies. Furthermore, the single topology of Ballani is parallel with compute nodes- not another topology of switches. That is, Ballani describes one topology of switches that is parallel with a set of compute nodes. Ballani does not describe two topologies of switches that are parallel with and independent of one another.
The word "topology" is mentioned in Ballani ten times, always in the singular, to discuss the topology of the network. Nowhere does Ballani disclose duplicating a switching fabric into multiple independent topologies that coexist concurrently and are simultaneously available for data transmission. Instead, Ballani discusses a flattened topology that is itself parallel with compute nodes…
Ballani does not disclose more than one topology. Ballani does not disclose topologies parallel and independent of one another.
Ballani also does not disclose a host fabric adapter adapted for data transfer through ports dedicated to each of the topologies. As discussed above, Ballani discloses a conventional switch configuration that includes a one-to-one relationship between compute node interfaces and switch interfaces.”
The Examiner respectfully disagrees. Fig. 1A depicts the fabric of switches 102 and links in parallel, the switches are separate and therefore independent, which teaches “at least two parallel and independent topologies.”
With respect to dependent claims, the Applicant asserts:
“The Office Action does not articulate a rationale explaining why a person having ordinary skill in the art would have been motivated to combine traffic engineering techniques, protection switching mechanisms, modular cable arrangements, and interface protocols to arrive at an architecture that physically duplicates switching fabrics into parallel, independent topologies exposed through corresponding ports of a host fabric adapter. The proposed combination requires impermissible hindsight reconstruction and would fundamentally alter the operating principles of the cited references. Furthermore, because Ballani does not disclose the claimed architecture of parallel independent topologies with a single integrated HFA, no combination of references teaching cable types, packet processing, error monitoring, or bus protocols can cure this fundamental deficiency.
…While Rivaud teaches double-density cables, Examiner's proposed substitution ignores that the claimed "double density cable" is specifically "adapted for the HFA and at least two switches," meaning it must accommodate the unique architecture of a single HFA with dedicated ports to parallel independent topologies. Rivaud's cables are conventional cables for conventional point-to-point links, not cables designed for the claimed mirrored topology architecture. Furthermore, since Ballani doesn't disclose the underlying mirrored switch configuration with parallel independent topologies, adding Rivaud's cables to Ballani's conventional architecture does not yield the current invention. As such, Rivaud does not cure the deficiencies of Ballani.
… Singh does not disclose mirrored switch configurations, parallel and independent topologies, or HFAs according to the present invention. The examiner's motivation, optimizing packet processing, relates to software-level traffic management, not the physical duplication of switch fabrics into parallel topologies. Singh does not teach or suggest the claimed architectural approach, and does not cure the deficiencies of Ballani.
…Vieregge does not disclose mirrored switch configurations, parallel and independent topologies, or HFAs according to the present invention. Vieregge does not cure the deficiencies of Ballani.
…Goel does not disclose mirrored switch configurations, parallel and independent topologies, or HFAs according to the present invention. Goel does not cure the deficiencies of Ballani.
…Banerjee does not disclose mirrored switch configurations, parallel and independent topologies, or HFAs according to the present invention. Banerjee does not cure the deficiencies of Ballani.”
The Examiner respectfully disagrees. The rejections of each respective claim rejected under 35 U.S.C. 103 explicitly “articulate a rationale explaining why a person having ordinary skill in the art would have been motivated to combine traffic engineering techniques, protection switching mechanisms, modular cable arrangements, and interface protocols to arrive at an architecture that physically duplicates switching fabrics into parallel, independent topologies exposed through corresponding ports of a host fabric adapter.” Regarding the arguments address to Rivaud, other than stating “adapted” the claim does not provide distinguishing cable design limitations, just that the cable is “double density’; accordingly, the combination of the prior art components and their respective functionality is the “adapted” configuration. Regarding the remarks addressed to Singh, Vieregge, Goel, and Banerjee, the arguments rely on the persuasiveness of the arguments against Ballani, which are not considered persuasive and have been addressed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 20100312913 of Wittenschlaeger et al. is pertinent to network fabric configurations and discusses implementing a mirrored topology. The US Patent No. 5761433 of Billings et al. is pertinent to networked switches and discusses applying the advantages of “Mirrored-Server Topology”.
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Center. For more information about the Patent Center, see https://patentcenter.uspto.gov/. Should you have questions on access to the Patent Center system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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