DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
2. Claims 1 – 7 are objected to because of the following informalities: the claims recite in line 1 respectively “machine readable medium” which should be corrected to “non-transitory machine readable medium”.
Claims 1, 8, and 14 are objected to because of the following informalities: claim 1 – line 3, claim 8 – line 2, and claim 14 – line 6, recite “ASIC” which should be corrected to “application-specific integrated circuit (ASIC)”.
Claim 12 is objected to because of the following informalities: line 1 recites “The machine readable medium of claim 8” which should be corrected to “The apparatus of claim 8”.
Claim 14 is objected to because of the following informalities: line 5 recites “IPU” which should be corrected to “infrastructure processing unit (IPU)”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the first layer" and “the second layer” in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Doshi et al. (US Publication Number 2021/0117249, hereinafter “Doshi”).
7. As per claims 1, 8, and 14, Doshi teaches a medium, apparatus, system, comprising: a plurality of host processing cores (3810, figure 38 processing cores in light of figure 6 accelerator node having a plurality of cores); a network (figure 24, networked nodes); an infrastructure processing unit (IPU0…3 interfaced to the associated accelerator, figure 24) coupled in between the plurality of host processing cores and the network (IPU interfaced to the network via the network interface, figure 24), the infrastructure processing unit comprising one or more IPU processing cores (plurality of IPU cores in each node, figure 6), a first ASIC block (620, figure 6 ASIC block, paragraph 81) and a second ASIC block (620, figure 6, second ASIC block in light of paragraph 81 where plurality of 620 cores seen); first device driver (OS controlled device driver, paragraph 408 for each ASIC block) program code for the first ASIC block to execute on at least one of the one or more IPU processing cores (capability of IPU handled upon code execution, paragraph 408); second device driver program for the second ASIC block to execute on at least one of the one or more IPU processing cores (plurality of cores with respective device driver handling, figure 38, paragraph 408); framework program code (IPU has associated framework code functionality, paragraph 170) to execute on at least one of the one or more IPU processing core, the framework program code to: receive a first invocation (invocation A, paragraph 209, for first driver handling) for the first device driver from a first layer of software, the first invocation including a value (layer handling seen in figure 13 for particular device configuration); receive a second invocation (invocation B, paragraph 209, for second driver handling) for the second device driver from a second layer of software, the second invocation including the value (layer handling seen in figure 13, for second device, paragraphs 118 and 119); infer from the first and second invocations having included the value that the second ASIC block is to operate on output from the first ASIC block; invoke the first and second device drivers to cause the second ASIC block to operate on the output from the first ASIC block (paragraphs 118 – 121, where ASIC block operation allows for function to operate on output of first ASIC block for the nodes).
8. As per claim 2, Doshi teaches a medium, wherein the semiconductor chip comprises an infrastructure processing unit (IPU) (IPUs , paragraph 56).
9. As per claims 3, 9, and 15, Doshi teaches a medium, apparatus, system, wherein the output of the first ASIC block is direct memory access (DMA) data and the second ASIC block is to encrypt the DMA data (DMA access for the layer handling, paragraph 340).
10. As per claims 4, 10, and 16, Doshi teaches a medium, apparatus, system, wherein the first invocation is made by a first layer of a software stack and the second invocation is made by a second layer of the software stack (layers handled according to protocol stack, paragraphs 340 and 342).
11. As per claims 5, 11, and 17, Doshi teaches a medium, apparatus, system, wherein the first layer is higher than the second layer and the first invocation is made before the second invocation (paragraph 138, first layer invoked prior to second).
12. As per claims 6, 13, and 19, Doshi teaches a medium, apparatus, system, wherein the method further comprises waiting in between the first and second invocations (synchronous invocations, paragraph 201).
13. As per claims 7, 12, and 18, Doshi teaches a medium, apparatus, system, wherein the value is a Storage Platform Development Kit (SPDK) memory domain value (SPDK, paragraph 404).
14. As per claim 20, Doshi teaches a system, wherein the output is part of an IPSec egress packet to be sent on the network (paragraph 307, IPsec).
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bahirat/Glimcher/Pattan/Musleh have teachings of ASIC/IPU processing and handling.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184