Prosecution Insights
Last updated: April 19, 2026
Application No. 18/069,133

PACKAGES WITH MULTI-LAYER PIEZOELECTRIC SUBSTRATE

Non-Final OA §DP
Filed
Dec 20, 2022
Examiner
GLENN, KIMBERLY E
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Skyworks Solutions Inc.
OA Round
2 (Non-Final)
90%
Grant Probability
Favorable
2-3
OA Rounds
2y 6m
To Grant
96%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
949 granted / 1057 resolved
+21.8% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
38 currently pending
Career history
1095
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
24.6%
-15.4% vs TC avg
§102
38.0%
-2.0% vs TC avg
§112
30.9%
-9.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1057 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1,2 and 4-22 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5 , 6, 9-14, 16,17, and 20-22 of copending Application No. 18/069, 141(reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because : 18/069,133 18/069,141 1. A packaged acoustic wave component comprising: an acoustic wave device including a substrate, a piezoelectric layer disposed over at least a portion of the substrate and one or more signal lines; a thermally conductive structure attached to one or both of the substrate and the one or more signal lines, the one or more signal lines interconnecting the piezoelectric layer and the thermally conductive structure; and a dielectric layer disposed over an outer edge portion of the piezoelectric layer and interposed between the piezoelectric layer and the thermally conductive structure and between the one or more signal lines and the piezoelectric layer to thereby reduce a stress on the piezoelectric layer from the thermally conductive structure. between the one or more signal lines and the piezoelectric layer. A method of making a packaged acoustic wave component comprising: forming an acoustic wave device including forming or providing a substrate, forming or providing a piezoelectric layer over at least a portion of the substrate, and forming or providing one or more signal lines; forming a dielectric layer over an outer edge portion of the piezoelectric layer; and attaching a thermally conductive structure to the substrate and the one or more signal lines, the one or more signal lines interconnecting the piezoelectric layer and the thermally conductive structure, the dielectric layer interposed between the piezoelectric layer and the thermally conductive structure to thereby reduce a stress on the piezoelectric layer from the thermally conductive structure. 3. The method of claim 1 wherein forming the dielectric layer includes interposing the dielectric layer between the one or more signal lines and the piezoelectric layer. 2. The packaged acoustic wave component of claim 1 further comprising a functional layer interposed between the substrate and the piezoelectric layer. 2. The method of claim 1 wherein forming the acoustic wave device includes forming or providing a dielectric layer between the substrate and the piezoelectric layer. 4. The packaged acoustic wave component of claim 1 wherein the thermally conductive structure includes a metal portion set back from the piezoelectric layer so that one or more pillars are disposed between the metal portion and the piezoelectric layer. 5. The method of claim 1 wherein the thermally conductive structure includes a metal portion set back from the piezoelectric layer so that one or more pillars are disposed between the metal portion and the piezoelectric layer 5. The packaged acoustic wave component of claim 1 wherein an outer edge of the piezoelectric layer is spaced inward of an outer edge of the substrate. 6. The method of claim 1 wherein forming or providing the piezoelectric layer includes forming an outer edge of the piezoelectric layer so that it is spaced inward of an outer edge of the substrate. 6. The packaged acoustic wave component of claim 1 wherein the dielectric layer is disposed over the piezoelectric layer in non-electrically connected areas of the package. 9. The method of claim 1 wherein forming the dielectric layer includes forming the dielectric layer over the piezoelectric layer in non-electrically connected areas of the package. 7. The packaged acoustic wave component of claim 1 wherein the dielectric layer is disposed over the piezoelectric layer in non-electrically connected areas and electrically connected areas of the package. 10. The method of claim 1 wherein forming the dielectric layer includes forming the dielectric layer over the piezoelectric layer in non-electrically connected areas and electrically connected areas of the package. 8. The packaged acoustic wave component of claim 1 wherein the dielectric layer is disposed over the piezoelectric layer around an entire periphery of the package. 11. The method of claim 1 wherein forming the dielectric layer includes forming the dielectric layer over the piezoelectric layer around an entire periphery of the package. 9. A radio frequency module comprising: a package substrate; a packaged acoustic wave component including an acoustic wave device including a substrate, a piezoelectric layer disposed over at least a portion of the substrate and one or more signal lines, a thermally conductive structure attached to one or both of the substrate and the one or more signal lines, the one or more signal lines interconnecting the piezoelectric layer and the thermally conductive structure, and a dielectric layer disposed over an outer edge portion of the piezoelectric layer and interposed between the piezoelectric layer and the thermally conductive structure and between the one or more signal lines and the piezoelectric layer to thereby reduce a stress on the piezoelectric layer from the thermally conductive structure; and additional circuitry, the packaged acoustic wave component and additional circuitry disposed on the package substrate. 12. A method of making a radio frequency module comprising: forming or providing a package substrate; forming or providing a packaged acoustic wave component including an acoustic wave device including forming or providing a substrate, forming or providing a piezoelectric layer over at least a portion of the substrate, forming or providing one or more signal lines, forming a dielectric layer over an outer edge portion of the piezoelectric layer, and attaching a thermally conductive structure to the substrate and the one or more signal lines, the one or more signal lines interconnecting the piezoelectric layer and the thermally conductive structure, the dielectric layer interposed between the piezoelectric layer and the thermally conductive structure to thereby reduce a stress on the piezoelectric layer from the thermally conductive structure; and attaching additional circuitry and the packaged acoustic wave component to the package substrate. 14. The method of claim 12 wherein forming the dielectric layer includes interposing the dielectric layer between the one or more signal lines and the piezoelectric layer. . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Allowable Subject Matter Claims 17, 18 and 20-24 are allowed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY E GLENN whose telephone number is (571)272-1761. The examiner can normally be reached M-F 8:00 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. October 17, 2025 /K.E.G/Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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Prosecution Timeline

Dec 20, 2022
Application Filed
Apr 08, 2025
Non-Final Rejection — §DP
Jul 09, 2025
Response Filed
Oct 17, 2025
Non-Final Rejection — §DP (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
90%
Grant Probability
96%
With Interview (+6.4%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 1057 resolved cases by this examiner. Grant probability derived from career allow rate.

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