DETAILED ACTION
The current Office Action is in response to the papers submitted 06/12/2026. Claims 1 – 4 and 6 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 - 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Pat 9,431,064) referred to as Lee in view of Jim Handy (THE CACHE MEMORY BOOK) referred to as Handy.
Regarding claim 13, Lee teaches receiving, in a memory controller [240, Fig 2; 430, Fig 4A – 4C] of a memory side cache [220, Fig 2; 420, Figs 4A – 4C], a request from an intellectual property (IP) circuit, the IP circuit [610, Fig 6; 710, Fig 7; The device that sends the read and write requests is an IP circuit] aggregated with a data array of the memory side cache [220, Fig 2; 420, Figs 4A – 4C; The cache is a data array and the device that sends the requests to access the cache is aggregated with the data array of the cache allowing the device to access the data array], the memory controller [240, Fig 2; 430, Fig 4A – 4C] of the memory side cache [220, Fig 2; 420, Figs 4A – 4C] disaggregated from the data array of the memory side cache [220, Fig 2; 420, Figs 4A – 4C; The cache memory and controller are distinct from each other];
sending a cache command [610, 650, and 660, Fig 6; Fig 7; Accessing the cache shows a cache command is sent to the cache controller resulting in the cache being accessed at a certain address location] to a controller [240, Fig 2; 430, Fig 4A – 4C] aggregated with the data array [220, Fig 2; 420, Figs 4A – 4C; Each figure shows the controller 240 and data array 220 aggregated in packages 400A, 400B, or 400C in figures 4A – 4C], to cause the controller [240, Fig 2; 430, Fig 4A – 4C] to access data at a location in the data array [220, Fig 2; 420, Figs 4A – 4C].
However, Lee may not specifically disclose the limitation(s) of determining a cache address of a location in the data array based at least in part on a logical address of the request.
Handy discloses determining a cache address of a location in the data array based at least in part on a logical address of the request [Pages 50 – 53; When the cache is a physical cache the address in the cache is a physical address based on the logical address received in the access command].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Handy in Lee, because it prevents the issues that arise from address aliasing.
Regarding claim 14, Lee teaches when the request comprises a read request [610, Fig 6], the method further comprises:
in response to identifying a miss for the read request in the data array [650, Fig 6; Reaching 650 is a result of a miss in step 640], sending a memory read request to a memory of a memory hierarchy [210, Fig 2; 650, Fig 6; Column 6, Lines 29 – 40; A miss in the cache results in a read from memory 210 in the memory hierarchy of the system];
receiving the data from the memory [210, Fig 3; 650, Fig 6; Column 6, Lines 29 – 40; The missed data is read from memory 210] ; and
sending a write and forward cache command to the controller [240, Fig 2] with the data to cause the controller [240, Fig 2] to forward the data to the IP circuit [610 and 660, Fig 6; The device that sends the read request is an IP circuit] and store the data in the location in the data array [420, Fig 4A – 4C; 650, Fig 6].
Regarding claim 15, Lee teaches when the request comprises a read request [610, Fig 6], the method further comprises:
in response to identifying a hit for the read request in the data array [420, Fig 4A – 4C], sending a read and forward cache command to the controller [240, Fig 2] to cause the controller [240, Fig 2] to read the data from the location in the data array [420, Fig 4A – 4C] and forward the data to the IP circuit [610, 640, and 660, Fig 6; The device that sends the read request is an IP circuit. A Yes in step 640 indicates a hit in the cache causing the cache controller to read data out of the cache and send the read data to the device that initiated the read in step 610].
Regarding claim 16, Lee teaches when the request comprises a write request [710, Fig 7], the method further comprises:
sending a write pull cache command [710, Fig 1] to the controller [240, Fig 2; 430, Fig 4A – 4C] to cause the controller [240, Fig 2; 430, Fig 4A – 4C] to obtain the data from the IP circuit [610, Fig 6; 710, Fig 7; The device that sends the read and write requests is an IP circuit] and store the data in the location in the data array [220, Fig 2; 420, Figs 4A – 4C; Column 4, Lines 52 – 60; Write data in the write request is written into the cache data array].
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Pat 9,431,064) referred to as Lee in view of Jim Handy (THE CACHE MEMORY BOOK) referred to as Handy as applied to claim 13 above, and further in view of Lee (Pub. No.: US 2019/0267073) referred to as Lee2.
Regarding claim 17, Lee teaches the method further comprises:
receiving, from the controller, signals related to the cache command [Figs 6 – 7; Column 2, Lines 57 – 67; Column 3, Lines 1 – 13; The controller sends out control signals to read and write data to and from the cache in response to received cache command]
Handy maintaining an ordering of at least two transaction based at least in part on the signals [2.2.6 Write Buffers and Line Buffers, Pages 77 – 86; The buffers maintain an order of cache transactions].
However, Lee in view of Handy may not specifically disclose the limitation(s) of receiving, from the controller, a completion for the cache command.
Lee2 discloses receiving, from the controller, a completion for the cache command [Paragraph 0112; The controller sends out completion commands to switch the mode of the memory].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee2 in Lee in view of Handy, because it allows the memory to work in multiple modes and provides a way to switch the mode of the memory to prevent malfunction of the memory being in a mode different than the type of transaction it is used for [Paragraph 0112].
Allowable Subject Matter
Claims 1 – 4, 6 – 12, and 18 – 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 amendments now include the allowable subject matter from cancelled claim 5.
Claim 18 was indicated allowable in the previous office action on 03/12/2026.
All remaining claims are allowed for being dependent on an allowed base claim and thus incorporating the allowable subject matter.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 06/12/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 6 – 7 that claim 1 and 13 have been amended to include the limitations of cancelled claim 5 that was previously indicated allowable. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Claim 1 include the limitations of cancelled claim 5. The amendment to claim 13 does not include the limitations of cancelled claim 5. The rejection of claim 13 has been updated in response to the amendment to claim 13.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138
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