DETAILED ACTION
The current Office Action is in response to the papers submitted 12/21/2022. Claims 1 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
Claims 13 - 17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter.
As per claim 13, a broadest reasonable interpretation for the term “computer readable medium” would include both statutory embodiments and non-statutory embodiments such as signals. The specification does mention a computer-readable storage medium in paragraphs 0118 - 0119. There is no limitation in the cited paragraphs as to the type of medium the computer readable medium is. A computer readable medium includes a wireless energy signal. As such, the claim(s) is/are drawn to a form of energy. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation “maintaining an ordering of at least one transaction…” in line 4. It is unclear how a single transaction has an ordering. Maintaining an ordering of something requires more than one item since a single item has no order since there is nothing to set the order against. A single transaction, which is one transaction, does not have any particular order when compared to itself. This makes the limitation indefinite which makes the claim indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Pat 9,431,064) referred to as Lee in view of Gu et al. (Pub. No.: US 2018/0366442) referred to as Gu in view of Sumbul et al. (Pub. No.: US 2020/0026498) referred to as Sumbul.
Regarding claim 1, Lee teaches an apparatus [Figs 4A – 4C] comprising;
a first die [430, Figs 4A – 4C] comprising:
memory circuitry [230 and 240, Fig 2; 430, Fig 4; Column 2, Lines 31 – 67; Column 3, Lines 1 – 13; Column 4, Lines 64 – 67; Column 5, Lines 1 – 10; Item 430 contains both controllers in one die] comprising a memory controller [230, Fig 2] and a memory side cache controller [240, Fig 2] to maintain tag information and state information [Column 2, Lines 57 – 67; Column 3, Lines 1 – 13; Column 4, Lines 44 – 60; Column 7, Lines 18 – 28; 650, Fig 6; 740, Fig 7; The controller die maintains tag information in the form of address information to determine a hit or miss in the cache along with valid state information indicating if data in the cache is valid or not] for a data array [420, Fig 4A – 4C]; and
a second die [420, Figs 4A – 4C] coupled [450, Figs 4A – 4C] to the first die [430, Figs 4A – 4C; All the dies are coupled to each other through 440 and 450], the second die [420, Figs 4A – 4C] comprising:
the data array to cache data for at least one device [420, Figs 4A – 4C; The second die is a die of cache memory that cache data for a device in the system], wherein the memory side cache controller [240, Fig 2] is to control the data array [Column 2, Lines 57 – 67; Column 3, Lines 1 – 13; Column 4, Lines 44 – 60; Column 7, Lines 18 – 28; Figs 6 – 7; The controller die receives read and write commands and controls the cache array 420 and 410 to respond to the read and write commands].
However, Lee may not specifically disclose the limitation(s) of a first die comprising both a plurality of cores and a controller and the data array caching data for at least one accelerator, the at least one accelerator remote from the first die.
Gu discloses a first die [302, Fig 3] comprising a plurality of cores [110(0) – 110(1), Fig 3; Each processing unit is considered a core] and a controller [146, Fig 3; A controller is well known macroblock used to control memory].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gu in Lee, because adding the controllers to the same die as cores improves access times between the cores and the controller since they are on the same die thereby reducing the length of wires data signals need to pass through between the cores and the controllers as compared to having the controllers and cores on separate dies.
However, Lee in view of Gu may not specifically disclose the limitation(s) of the data array caching data for at least one accelerator, the at least one accelerator remote from the first die.
Sumbul discloses the data array caching data [520, Fig 5] for at least one accelerator [530 or 540, Fig 5; Paragraph 0098; Cache 520 is a memory array to store data from the accelerator 530], the at least one accelerator [530 or 540, Fig 5; Paragraphs 0091; The CIM is an accelerator including CNM circuitry] remote from the first die [510, Fig 5; Paragraphs 0046; The CIM can be on its own die separate from other dies in the system including the die with the processor].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sumbul in Lee in view of Gu, because the use of an accelerator moves the burden of certain processing from the main processor to the accelerator thereby accelerating algorithms and reducing energy overhead [Paragraph 0025].
Regarding claim 2, Lee teaches the second die [420, Figs 4A – 4C].
Sumbul discloses the second die [520, Fig 5] further comprises the at least one accelerator [530, Fig 5; The CIM 530 can be on the same die as the cache array].
Regarding claim 3, Lee teaches the second die [420, Figs 4A – 4C].
Gu discloses stacking dies [Figs 4A – 4B; The dies can be stacked].
Sumbul discloses a third die comprising the at least one accelerator [540, Fig 5; When the CIM is separate from cache 520 it is on its own die].
Regarding claim 4, Lee teaches comprising a die-to-die interconnect [252, 254, 256 – 258, Fig 2; 440, Figs 4A – 4B; The data paths shows interconnects between the circuits on the dies] to couple the first die [430, Figs 4A – 4C] and the second die [420, Figs 4A – 4C], the apparatus [Figs 4A – 4C] comprising a package [400A, Fig 4A; 400B, Fig 4B; 400C, Fig 4C] having the first die [430, Figs 4A – 4C] and the second die [420, Figs 4A – 4C; The package is the].
Claim(s) 13 - 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Pat 9,431,064) referred to as Lee in view of Jim Handy (THE CACHE MEMORY BOOK) referred to as Handy.
Regarding claim 13, Lee teaches receiving, in a memory controller [240, Fig 2; 430, Fig 4A – 4C] of a memory side cache [220, Fig 2; 420, Figs 4A – 4C], a request from an intellectual property (IP) circuit, the IP circuit [610, Fig 6; 710, Fig 7; The device that sends the read and write requests is an IP circuit] aggregated with a data array of the memory side cache [220, Fig 2; 420, Figs 4A – 4C; The cache is a data array and the device that sends the requests to access the cache is aggregated with the data array of the cache allowing the device to access the data array], the memory controller [240, Fig 2; 430, Fig 4A – 4C] of the memory side cache [220, Fig 2; 420, Figs 4A – 4C] disaggregated from the data array of the memory side cache [220, Fig 2; 420, Figs 4A – 4C; The cache memory and controller are distinct from each other];
sending a cache command [610, 650, and 660, Fig 6; Fig 7; Accessing the cache shows a cache command is sent to the cache controller resulting in the cache being accessed at a certain address location] to a controller [240, Fig 2; 430, Fig 4A – 4C] associated with the data array [220, Fig 2; 420, Figs 4A – 4C], to cause the controller [240, Fig 2; 430, Fig 4A – 4C] to access data at a location in the data array [220, Fig 2; 420, Figs 4A – 4C].
However, Lee may not specifically disclose the limitation(s) of determining a cache address of a location in the data array based at least in part on a logical address of the request.
Handy discloses determining a cache address of a location in the data array based at least in part on a logical address of the request [Pages 50 – 53; When the cache is a physical cache the address in the cache is a physical address based on the logical address received in the access command].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Handy in Lee, because it prevents the issues that arise from address aliasing.
Regarding claim 14, Lee teaches when the request comprises a read request [610, Fig 6], the method further comprises:
in response to identifying a miss for the read request in the data array [650, Fig 6; Reaching 650 is a result of a miss in step 640], sending a memory read request to a memory of a memory hierarchy [210, Fig 2; 650, Fig 6; Column 6, Lines 29 – 40; A miss in the cache results in a read from memory 210 in the memory hierarchy of the system];
receiving the data from the memory [210, Fig 3; 650, Fig 6; Column 6, Lines 29 – 40; The missed data is read from memory 210] ; and
sending a write and forward cache command to the controller [240, Fig 2] with the data to cause the controller [240, Fig 2] to forward the data to the IP circuit [610 and 660, Fig 6; The device that sends the read request is an IP circuit] and store the data in the location in the data array [420, Fig 4A – 4C; 650, Fig 6].
Regarding claim 15, Lee teaches when the request comprises a read request [610, Fig 6], the method further comprises:
in response to identifying a hit for the read request in the data array [420, Fig 4A – 4C], sending a read and forward cache command to the controller [240, Fig 2] to cause the controller [240, Fig 2] to read the data from the location in the data array [420, Fig 4A – 4C] and forward the data to the IP circuit [610, 640, and 660, Fig 6; The device that sends the read request is an IP circuit. A Yes in step 640 indicates a hit in the cache causing the cache controller to read data out of the cache and send the read data to the device that initiated the read in step 610].
Regarding claim 16, Lee teaches when the request comprises a write request [710, Fig 7], the method further comprises:
sending a write pull cache command [710, Fig 1] to the controller [240, Fig 2; 430, Fig 4A – 4C] to cause the controller [240, Fig 2; 430, Fig 4A – 4C] to obtain the data from the IP circuit [610, Fig 6; 710, Fig 7; The device that sends the read and write requests is an IP circuit] and store the data in the location in the data array [220, Fig 2; 420, Figs 4A – 4C; Column 4, Lines 52 – 60; Write data in the write request is written into the cache data array].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Pat 9,431,064) referred to as Lee in view of Gu et al. (Pub. No.: US 2018/0366442) referred to as Gu in view of Sumbul et al. (Pub. No.: US 2020/0026498) referred to as Sumbul as applied to claim 1 above, and further in view of Jim Handy (THE CACHE MEMORY BOOK) referred to as Handy.
Regarding claim 12, Lee teaches the memory side cache controller [240, Fig 2] is to receive a request from the device [610, Fig 6; 710, Fig 7], the request comprising an logical address, and in response to the request [610, Fig 6; 710, Fig 7], send a cache command with a cache address, the cache address comprising a location in the data array [420, Figs 4A – 4C] corresponding to the logical address [640, 650, and 660, Fig 6; 730 and 740, Fig 7; The checking of the cache, reading from the cache, and storing data in the cache all use an address to identify a location in the cache data array].
However, Lee in view of Gu in view of Sumbul may not specifically disclose the limitation(s) of the request comprising a logical address.
Handy discloses the request comprising a logical address [Pages 50 – 53; The logical address is used in a command to address the cache in a virtual cache].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Handy in Lee in view of Gu in view of Sumbul, because it allows access to the cache to be faster compared to accessing the cache using a physical address that needs to be translated from the logical address.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Pat 9,431,064) referred to as Lee in view of Jim Handy (THE CACHE MEMORY BOOK) referred to as Handy as applied to claim 13 above, and further in view of Lee (Pub. No.: US 2019/0267073) referred to as Lee2.
Regarding claim 17, Lee teaches the method further comprises:
receiving, from the controller, signals related to the cache command [Figs 6 – 7; Column 2, Lines 57 – 67; Column 3, Lines 1 – 13; The controller sends out control signals to read and write data to and from the cache in response to received cache command]
Handy maintaining an ordering of at least one transaction based at least in part on the signals [2.2.6 Write Buffers and Line Buffers, Pages 77 – 86; The buffers maintain an order of cache transactions].
However, Lee in view of Handy may not specifically disclose the limitation(s) of receiving, from the controller, a completion for the cache command.
Lee2 discloses receiving, from the controller, a completion for the cache command [Paragraph 0112; The controller sends out completion commands to switch the mode of the memory].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee2 in Lee in view of Handy, because it allows the memory to work in multiple modes and provides a way to switch the mode of the memory to prevent malfunction of the memory being in a mode different than the type of transaction it is used for [Paragraph 0112].
Allowable Subject Matter
Claims 5 - 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18 - 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art teaches systems setup with multiple dies, multiple processors and controllers on a die, and cache memory on a die. However, the prior art individually or in combination fails to disclose the limitations of…
(Claim 18) “…a second die comprising a data array of the memory side cache and a remote data agent to perform cache commands received from the memory side cache controller, wherein the remote data agent comprises an interface between the data array and at least one accelerator…”
The claims requires the data agent to receive commands from the memory side cache controller and perform the received commands and the data agent also comprises an interface. This means the data agent is not the interface itself, rather the data agent includes the interface and the data agent processes commands from the controller. In the prior art a cache controller usually receives and processes cache commands. The claims though require a cache controller that sends cache commands to a data agent, where the data agent comprises an interface, and the data agent is the device that processes the cache commands.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138