DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the Request for Continued Examination (RCE) on 09 January 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kiyomi (JP 2006/050698; rejection based on English translation), in view of Chen et al. (US 2018/0062638), hereinafter Chen.
Regarding claim 1, Kiyomi discloses (see figures 1-3) a power converter (figure 1[A], part 1) (paragraph [0024]; A full-bridge type bridge device 1), comprising: a printed circuit board (PCB) (figure 1[B], part 21) (paragraph [0028]; The printed circuit board 21 may be a dedicated circuit board only for mounting the semiconductor switch element and the capacitor constituting the bridge device 1 or may be a part of a large-area printed circuit board on which electronic components of other devices are mounted) having a first side (figure 1[B], part upper side of 21) and a second side (figure 1[B], part lower side of 21) opposite to one another (figure 1[B], part upper side of 21); a plurality of first commutation units (figure 1[A]/[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) disposed on the PCB (figure 1[B], part 21), each of the first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) comprising a first discrete component (figure 1[A]/1[B], part first discrete component 10A-10C) and a second discrete component (figure 1[A]/1[B], part second discrete component 11A-11C), a second end of the first discrete component (figure 1[A]/1[B], part lower end of first discrete component 10A-10C) being electrically coupled to a first end of the second discrete component (figure 1[A]/1[B], part upper end of second discrete component 11A-11C); and a first capacitor unit (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F) disposed on the PCB (figure 1[B], part 21), and the first capacitor unit (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F) being electrically coupled to a first end of the first discrete component (figure 1[A]/1[B], part upper end of first discrete component 10A-10C) and a second end of the second discrete component (figure 1[A]/1[B], part lower end of second discrete component 11A-11C) in each of the plurality of first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C), respectively, the first capacitor unit (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F) comprising a plurality of first capacitors (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F), wherein the first discrete components (figure 1[A]/1[B], part first discrete components 10A-10C) and the second discrete components (figure 1[A]/1[B], part second discrete components 11A-11C) in the plurality of first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) are arranged in a row (figure 1[B], part upper row of 10A-10C and 11A-11C; connected to T3), the first discrete component (figure 1[A]/1[B], part first discrete component 10A-10C) and the second discrete component (figure 1[A]/1[B], part second discrete component 11A-11C) in each of the first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) forms a commutation loop together with one of the first capacitors (figure 1[A]/1[B], part one of the first capacitor unit generated by 17A-17F) (paragraphs [0024]-[0034]; capacitors 17A, 17B, 17C, 17D, 17E, and 17F each having a capacity obtained by dividing a capacity substantially equal to the capacity of the input capacitor 17 into six parts are arranged in parallel and correspond. It is connected at a close distance to the connection point of the series semiconductor switch elements… the six capacitors 17A, 17B, 17C, 17D, 17E, and 17F are arranged between the conductive pattern of the input wiring 14 and the conductive pattern of the input wiring 15 as the input capacitor 17. The capacitor 17A is connected to the drain lead terminal D of the semiconductor switch element 10A and the source lead terminal S of the semiconductor switch element 11A by making the connection position of these capacitors appropriate. It is also possible to connect at a distance. Similarly, the capacitor 17B is the shortest distance between the drain lead terminal D of the semiconductor switch element 10B and the source lead terminal S of the semiconductor switch element 11B, and the capacitor 17C is the drain lead terminal D of the semiconductor switch element 10C and the semiconductor switch element. It is also possible to connect to the 11C source lead terminal S at the shortest distance. It is also possible to connect the capacitor 17D to the drain lead terminal D of the semiconductor switch element 12A and the source lead terminal S of the semiconductor switch element 13A at the shortest distance. Similarly, the capacitor 17E is the shortest distance between the drain lead terminal D of the semiconductor switch element 12B and the source lead terminal S of the semiconductor switch element 13B, and the capacitor 17F is the drain lead terminal D of the semiconductor switch element 12C and the semiconductor switch element. It is also possible to connect to the 13C source lead terminal S at the shortest distance… the full bridge circuit of this embodiment, not only can a line between a pair of upper and lower series semiconductor switches be connected in the shortest time, but also a pair of upper and lower series semiconductor switches and an input capacitor. As a result, the bridge device can be reduced in size and the wiring inductance can be reduced, so that the surge voltage generated during switching of the semiconductor switch can be reduced, and this bridge device can be used as an inverter).
Kiyomi does not expressly disclose the first discrete component and the second discrete component in each of the first commutation units form a commutation loop together with the first capacitor which is physically as close as possible to the first commutation unit on the PCB, and the first capacitor in the commutation loop is different from the first capacitor in any other commutation loop.
Chen teaches (see figures 1-19) the first discrete component (figures 3 and 11, parts T1) and the second discrete component (figures 3 and 11, parts T2) in each of the first commutation units (figures 3 and 11, part each first commutation units generated by T1 and T2) form a commutation loop (figures 3 and 11, part commutation loop generated by each T1, T2 and C) (paragraph [0033]; an input capacitor C, a first power switch T1 and a second power switch T2 form a close-loop commutation circuit) together with the first capacitor (figure 11, part C) which is physically as close as possible to the first commutation unit (figure 11, part first commutation unit by T1 and T2) on the PCB (figure 11, part PCB of power chip), and the first capacitor (figure 11, part C) in the commutation loop (figure 11, part commutation loop generated by each T1, T2 and C) is different from the first capacitor (figure 11, part C) in any other commutation loop (figure 11, part other commutation loop generated by each T1, T2 and C) (paragraph [0041]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the power converter of Kiyomi with the commutation loop arrangement as taught by Chen and obtain a power converter, comprising: a printed circuit board (PCB) having a first side and a second side opposite to one another; a plurality of first commutation units disposed on the PCB, each of the first commutation units comprising a first discrete component and a second discrete component, a second end of the first discrete component being electrically coupled to a first end of the second discrete component; and a first capacitor unit disposed on the PCB, and the first capacitor unit being electrically coupled to a first end of the first discrete component and a second end of the second discrete component in each of the plurality of first commutation units, respectively, the first capacitor unit comprising a plurality of first capacitors, wherein the first discrete components and the second discrete components in the plurality of first commutation units are arranged in a row, the first discrete component and the second discrete component in each of the first commutation units form a commutation loop together with the first capacitor which is physically as close as possible to the first commutation unit on the PCB, and the first capacitor in the commutation loop is different from the first capacitor in any other commutation loop, because it reduces the size of the commutation circuit loop in order to reduce the influence of the parasitic inductance and improves the efficiency of the power converter (paragraph [0041]).
Regarding claim 2, Kiyomi and Chen teach everything claimed as applied above (see claim 1). Further, Kiyomi discloses (see figures 1-3) the first discrete components (figure 1[A]/1[B], part first discrete components 10A-10C) in the plurality of first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) are electrically coupled in parallel (figure 1[A]/1[B], part first discrete components 10A-10C), and the second discrete components (figure 1[A]/1[B], part second discrete components 11A-11C) in the plurality of first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) are electrically coupled in parallel (figure 1[A]/1[B], part second discrete components 11A-11C).
Regarding claim 3, Kiyomi and Chen teach everything claimed as applied above (see claim 1). Further, Kiyomi discloses (see figures 1-3) the first discrete components (figure 1[A]/1[B], part first discrete components 10A-10C) and the second discrete components (figure 1[A]/1[B], part second discrete components 11A-11C) in the plurality of first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) are alternately arranged in a row (figure 1[B], part upper row of 10A-10C and 11A-11C; connected to T3).
Regarding claim 4, Kiyomi and Chen teach everything claimed as applied above (see claim 1). Further, Kiyomi discloses (see figures 1-3) the first discrete components (figure 1[A]/1[B], part first discrete components 10A-10C) and the second discrete components (figure 1[A]/1[B], part second discrete components 11A-11C) in the plurality of first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) are located on the first side of the PCB (figure 1[B], part upper side of 21).
Claims 7, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kiyomi (JP 2006/050698; rejection based on English translation), in view of Chen et al. (US 2018/0062638), hereinafter Chen, and further in view of Sathler et al. (H. Sathler et al. , "Design of three-level flying-capacitor commutation cells with four paralleled 650 V/60 A GalHEMTS", IEEE, 14 June 2021 (2021-06-14), pages2277-2284，XP033944918), hereinafter Sathler.
Regarding claim 7, Kiyomi and Chen teach everything claimed as applied above (see claim 1). Further, Kiyomi discloses (see figures 1-3) the PCB (figure 1[B], part 21); and the first capacitor unit (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F). However, Kiyomi does not expressly disclose a plurality of second commutation units and a second capacitor unit disposed on the PCB; each of the second commutation units comprising a third discrete component and a fourth discrete component; a first end of the third discrete component in each of the plurality of second commutation units being electrically coupled to a first end of the second capacitor unit, a second end of the third discrete component in each of the plurality of second commutation units being electrically coupled to a first end of the first capacitor unit, a second end of the fourth discrete component in each of the plurality of second commutation units being electrically coupled to a second end of the second capacitor unit, and a first end of the fourth discrete component in each of the plurality of second commutation units being electrically coupled to a second end of the first capacitor unit; wherein the third discrete components and the fourth discrete components in the plurality of second commutation units are arranged in a row, and the third discrete component and the fourth discrete component in each of the second commutation units form a commutation loop together with the second capacitor unit and the first capacitor unit.
Sathler teaches (see figures 1-18) a plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) and a second capacitor unit (figure 1, part second capacitor unit generated by CDM) disposed on the PCB (figure 6, part PCB) (page 2280; left column; C. Vertical commutation cell; first paragraph; Signals tracks (green arrows) are placed on the borders of the PCB, while power (yellow arrows) remains in the center. Half of all devices are placed on the bottom layer and measurement points were placed close to the power connector to evaluate commutation cell performance); each of the second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) comprising a third discrete component (figure 1, parts Q1-Q4) and a fourth discrete component (figure 1, parts Q5-Q8); a first end of the third discrete component (figure 1, parts upper end of Q1-Q4) in each of the plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) being electrically coupled to a first end of the second capacitor unit (figure 1, part upper end of second capacitor unit generated by CDM), a second end of the third discrete component (figure 1, parts lower end of Q1-Q4) in each of the plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) being electrically coupled to a first end of the first capacitor unit (figure 1, part upper end of CFC), a second end of the fourth discrete component (figure 1, parts lower end of Q5-Q8) in each of the plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) being electrically coupled to a second end of the second capacitor unit (figure 1, part lower end of second capacitor unit generated by CDM), and a first end of the fourth discrete component (figure 1, parts upper end of Q5-Q8) in each of the plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) being electrically coupled to a second end of the first capacitor unit (figure 1, part lower end of CFC); wherein the third discrete components (figure 1, parts Q1-Q4) and the fourth discrete components (figure 1, parts Q5-Q8) in the plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) are arranged in a row (figure 1, parts row generated from up to down of Q1-Q4 and Q5-Q8), and the third discrete component (figure 1, parts Q1-Q4) and the fourth discrete component (figure 1, parts Q5-Q8) in each of the second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) form a commutation loop together with the second capacitor unit (figure 1, part second capacitor unit generated by CDM) and the first capacitor unit (figure 1, part upper end of CFC).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the power converter of Kiyomi with the multi-level power converter features as taught by Sathler and obtain a plurality of second commutation units and a second capacitor unit disposed on the PCB; each of the second commutation units comprising a third discrete component and a fourth discrete component; a first end of the third discrete component in each of the plurality of second commutation units being electrically coupled to a first end of the second capacitor unit, a second end of the third discrete component in each of the plurality of second commutation units being electrically coupled to a first end of the first capacitor unit, a second end of the fourth discrete component in each of the plurality of second commutation units being electrically coupled to a second end of the second capacitor unit, and a first end of the fourth discrete component in each of the plurality of second commutation units being electrically coupled to a second end of the first capacitor unit; wherein the third discrete components and the fourth discrete components in the plurality of second commutation units are arranged in a row, and the third discrete component and the fourth discrete component in each of the second commutation units form a commutation loop together with the second capacitor unit and the first capacitor unit, because it provides more efficient power conversion with multi-level voltage for high power density and switching losses reduction (page 2277; left column; I; first paragraph).
Regarding claim 17, Kiyomi, Chen and Sathler teach everything claimed as applied above (see claim 7). However, Kiyomi does not expressly disclose the third discrete components in the plurality of second commutation units are electrically coupled in parallel, the fourth discrete components in the plurality of second commutation units are electrically coupled in parallel, and the second capacitor unit comprises a plurality of second capacitors and the plurality of second capacitors are electrically coupled in parallel.
Sathler teaches (see figures 1-18) the third discrete components (figure 1, parts Q1-Q4) in the plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) are electrically coupled in parallel (figure 1, parts Q1-Q4), the fourth discrete components (figure 1, parts Q5-Q8) in the plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8) are electrically coupled in parallel (figure 1, parts Q5-Q8), and the second capacitor unit (figure 1, part second capacitor unit generated by CDM) comprises a plurality of second capacitors (figures 1, 6 and 7, part plurality of second capacitor unit generated by CDM) and the plurality of second capacitors are electrically coupled in parallel (figures 1, 6 and 7, part plurality of second capacitor unit generated by CDM).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the power converter of Kiyomi with the multi-level power converter features as taught by Sathler and obtain the third discrete components in the plurality of second commutation units are electrically coupled in parallel, the fourth discrete components in the plurality of second commutation units are electrically coupled in parallel, and the second capacitor unit comprises a plurality of second capacitors and the plurality of second capacitors are electrically coupled in parallel, because it provides more efficient power conversion with multi-level voltage for high power density and switching losses reduction (page 2277; left column; I; first paragraph).
Regarding claim 18, Kiyomi, Chen and Sathler teach everything claimed as applied above (see claim 7). However, Kiyomi does not expressly disclose the third discrete components (figure 1[A]/1[B], part third discrete components 12A-12C) and the fourth discrete components (figure 1[A]/1[B], part fourth discrete components 13A-13C) are alternately arranged in a row (figure 1[B], part lower row of 12A-12C and 13A-13C; connected to T4). However, Kiyomi does not expressly disclose the third discrete components and the fourth discrete components in the plurality of second commutation units.
Sathler teaches (see figures 1-18) the third discrete components (figure 1, parts Q1-Q4) and the fourth discrete components (figure 1, parts Q5-Q8) in the plurality of second commutation units (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the power converter of Kiyomi with the multi-level power converter features as taught by Sathler and obtain the third discrete components and the fourth discrete components in the plurality of second commutation units are alternately arranged in a row, because it provides more efficient power conversion with multi-level voltage for high power density and switching losses reduction (page 2277; left column; I; first paragraph).
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kiyomi (JP 2006/050698; rejection based on English translation), in view of Chen et al. (US 2018/0062638), hereinafter Chen, and further in view of Sathler et al. (H. Sathler et al. , "Design of three-level flying-capacitor commutation cells with four paralleled 650 V/60 A GalHEMTS", IEEE, 14 June 2021 (2021-06-14), pages2277-2284，XP033944918), hereinafter Sathler, and further in view of Wenjie et al. (CN 113437908A; rejection based on English translation), hereinafter Wenjie.
Regarding claim 21, Kiyomi, Chen and Sathler teach everything claimed as applied above (see claim 7). Further, Kiyomi discloses (see figures 1-3) the first capacitor unit (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F) is arranged in a row (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F; row between T1 and T2), and the first discrete components (figure 1[A]/1[B], part first discrete components 10A-10C) and the second discrete components (figure 1[A]/1[B], part second discrete components 11A-11C) in the first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C) are arranged in a row (figure 1[B], part upper row of 10A-10C and 11A-11C; connected to T3) and located on the first side of the PCB (figure 1[B], part upper side of 21). However, Kiyomi does not expressly disclose the first capacitor unit and the second capacitor unit are arranged in a row, and the first discrete components and the second discrete components in the first commutation units and the third discrete components and the fourth discrete components in the plurality of second commutation units are arranged in a row and located on the first side of the PCB.
Sathler teaches (see figures 1-18) the first capacitor unit (figure 1, part CFC) and the second capacitor unit (figure 1, part second capacitor unit generated by CDM) are arranged in a row (figure 6, part CFC and CDM; middle row of the PCB), and the first discrete components (figure 1, parts Q9-Q12) and the second discrete components (figure 1, parts Q13-Q16) in the first commutation units (figure 1, part first commutation units generated by Q9-Q12 and Q13-Q16) and the third discrete components (figure 1, parts Q1-Q4) and the fourth discrete components (figure 1, parts Q5-Q8) in the plurality of second commutation units are (figure 1, part plurality of second commutation units generated by Q1-Q4 and Q5-Q8).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the power converter of Kiyomi with the multi-level power converter features as taught by Sathler, because it provides more efficient power conversion with multi-level voltage for high power density and switching losses reduction (page 2277; left column; I; first paragraph).
Wenjie teaches (see figures 1-25) the capacitor unit (figures 1, 13, 14, , 17 and 18, part 9) are arranged in a row (figures 1, 13, 14, , 17 and 18, part 9; upper row), and the third discrete components (figures 1, 13, 14, , 17 and 18, part 1) and the fourth discrete components (figures 1, 13, 14, , 17 and 18, part 2) in the plurality of second commutation units (figures 1, 13, 14, , 17 and 18, part second commutation units generated by 1 and 2) are arranged in a row and located on the first side of the PCB (figures 1, 13, 14, , 17 and 18, part 1 and 2; arranged at lower row) (paragraphs [0079]-[0084]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Kiyomi, Chen and Sathler with the switch layout structure features as taught by Wenjie and obtain the first capacitor unit and the second capacitor unit are arranged in a row, and the first discrete components and the second discrete components in the first commutation units and the third discrete components and the fourth discrete components in the plurality of second commutation units are arranged in a row and located on the first side of the PCB, because it reduces the stray inductance of the switching circuit, and the performance and efficiency of the converter applying the switching circuit are improved (Abstract).
Regarding claim 22, Kiyomi, Chen, Sathler and Wenjie teach everything claimed as applied above (see claim 21). Further, Kiyomi discloses (see figures 1-3) the plurality of first capacitors (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F) are arranged in a row (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F; row between T1 and T2), wherein the plurality of first capacitors (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F) are close to the first discrete components (figure 1[A]/1[B], part first discrete components 10A-10C) and the second discrete components (figure 1[A]/1[B], part second discrete components 11A-11C) in the first commutation units (figure 1[A]/1[B], part first commutation units generated by first discrete component 10A-10C and second discrete component 11A-11C). However, Kiyomi does not expressly disclose the second capacitor unit comprises a plurality of second capacitors; the plurality of first capacitors and the plurality of second capacitors are arranged in a row; and the plurality of second capacitors are close to the third discrete components and the fourth discrete components in the plurality of second commutation units or the second capacitor unit comprises a plurality of second capacitors; the plurality of first capacitors and the plurality of second capacitors are arranged in a row, wherein a first part of the plurality of first capacitors are close to the first discrete components and the second discrete components in the first commutation units, and a second part of the plurality of first capacitors and the plurality of second capacitors are alternately arranged in a row and close to the third discrete components and the fourth discrete components in the plurality of second commutation units.
Sathler teaches (see figures 1-18) the second capacitor unit (figure 1, part second capacitor unit generated by CDM) comprises a plurality of second capacitors (figures 1 and 6-8, part plurality of second capacitor unit generated by CDM); the plurality of first capacitors (figures 1 and 6-8, part CFC, CFC’ and CFC’’) and the plurality of second capacitors (figures 1 and 6-8, part plurality of second capacitor unit generated by CDM) are arranged in a row (figure 8, parts CFC, CFC’ and CFC’’ and plurality of second capacitor unit generated by CDM; middle row from left to right), wherein the plurality of first capacitors (figures 1 and 8, part CFC) are close to the first discrete components (figures 1 and 8, parts Q9-Q12) and the second discrete components in the first commutation units (figures 1 and 8, part Q13-Q16), and the plurality of second capacitors (figures 1 and 8, part second capacitor unit generated by CDM) are close to the third discrete components (figures 1 and 8, parts Q1-Q4) and the fourth discrete components in the plurality of second commutation units (figures 1 and 8, parts Q5-Q8).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the power converter of Kiyomi with the multi-level power converter features as taught by Sathler and obtain the second capacitor unit comprises a plurality of second capacitors; the plurality of first capacitors and the plurality of second capacitors are arranged in a row, wherein the plurality of first capacitors are close to the first discrete components and the second discrete components in the first commutation units, and the plurality of second capacitors are close to the third discrete components and the fourth discrete components in the plurality of second commutation units; or the second capacitor unit comprises a plurality of second capacitors; the plurality of first capacitors and the plurality of second capacitors are arranged in a row, wherein a first part of the plurality of first capacitors are close to the first discrete components and the second discrete components in the first commutation units, and a second part of the plurality of first capacitors and the plurality of second capacitors are alternately arranged in a row and close to the third discrete components and the fourth discrete components in the plurality of second commutation units, because it provides more efficient power conversion with multi-level voltage for high power density and switching losses reduction (page 2277; left column; I; first paragraph).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Kiyomi (JP 2006/050698; rejection based on English translation), in view of Chen et al. (US 2018/0062638), hereinafter Chen, and further in view of Kitanaka (US 2014/0301041).
Regarding claim 30, Kiyomi and Chen teach everything claimed as applied above (see claim 1). Further, Kiyomi discloses (see figures 1-3) the first capacitor unit (figure 1[A]/1[B], part first capacitor unit generated by 17A-17F), the first discrete components (figure 1[A]/1[B], part first discrete components 10A-10C) and the second discrete components (figure 1[A]/1[B], part second discrete components 11A-11C). However, Kiyomi does not expressly disclose an enclosed cavity, the enclosed cavity comprising a middle chamber and a first side chamber connected to the middle chamber; the first capacitor unit being accommodated in the middle chamber, the first discrete components and the second discrete components being accommodated in the first side chamber, and the first side chamber being provided with a first heat sink.
Kitanaka teaches (see figures 1-14) an enclosed cavity (figures 13/14[B], part enclosed cavity 100), the enclosed cavity (figures 13/14[B], part enclosed cavity 100) comprising a middle chamber (figures 13/14[B], part middle chamber of the enclosed cavity 100) and a first side chamber (figures 13/14[B], part left side chamber at 70a of the enclosed cavity 100) connected to the middle chamber (figures 13/14[B], part middle chamber of the enclosed cavity 100); the first capacitor unit (figures 13/14[B], part 30) being accommodated in the middle chamber (figures 13/14[B], part middle chamber of the enclosed cavity 100), the first discrete components and the second discrete components (figures 1, 3 and 13/14[B], part first discrete components and the second discrete components 25 inside of 40a-40d) being accommodated in the first side chamber (figures 13/14[B], part left side chamber at 70a of the enclosed cavity 100) (paragraph [0116]-[0118]), and the first side chamber (figures 13/14[B], part left side chamber at 70a of the enclosed cavity 100) being provided with a first heat sink (figures 13/14[B], part first heat sink generated at 72a/72b) (paragraphs [0043]-[0044]; The semiconductor elements 25 are arranged on a semiconductor element attachment surface (the right side in the figure) of a cooler 28 including a cooler base section 27 and a cooler fin section 26).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the power converter of Kiyomi with the enclosed cavity features as taught by Kitanaka and obtain an enclosed cavity, the enclosed cavity comprising a middle chamber and a first side chamber connected to the middle chamber; the first capacitor unit being accommodated in the middle chamber, the first discrete components and the second discrete components being accommodated in the first side chamber, and the first side chamber being provided with a first heat sink, because it suppress an increase in the size, the weight, and the costs of the power conversion circuit even when a forced air cooling-type power conversion device of a system for individually driving a plurality of motors is configured (paragraph [0015]).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838