Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Conrad(US 2014/0189402).
Regarding claim 1, Conrad discloses a system comprising: a device; a voltage regulator coupled to the device to supply a voltage level to the device when the device is idle; and a power control unit to communicate to the voltage regulator the voltage level to supply to the device(Fig. 1, Paragraph 11, a voltage regulator controller that controls a voltage regulator (VR), which typically is external to the processor), the voltage level including a shutdown level and an operational level(Paragraph 11, first and second modification plan, Modification of the processor power level can be executed according to the selected power modification plan), the power control unit to determine the voltage level based on a demotion threshold wherein the demotion threshold is a time at which a first energy cost is equal to a second energy cost(Paragraph 26, The energy usage logic 130 may perform a comparison of the first energy cost to the second energy cost and may select the power management plan with the smaller energy cost. The VR controller 162 may perform the power modification according to the selected power modification plan. As stated in the specification, demotion threshold is typically the point where the energy cost for maintaining power to the device is approximately the same as or exceeds the energy cost of removing power to the device), wherein the first energy cost is a first amount of energy for the voltage regulator to maintain the operational voltage level to the device and the second energy cost is a second amount of energy for the voltage regulator to change the voltage level to the shutdown level(Paragraph 35, the energy usage logic is to determine an energy cost associated a first power modification plan (e.g., passive decay phase, and possibly unregulated idle phase). The energy usage logic is to determine an energy cost associated a second modification plan (e.g., actively managed voltage reduction by voltage regulator controller, active control of voltage at idle power state). The energy usage logic is to compare a passive plan energy cost associated with the passive modification plan to an active plan energy cost associated with the active modification plan. If the passive plan energy cost is greater than the active plan energy cost, the energy usage logic is to select the active power modification plan. If the active plan energy cost is greater than the passive plan energy cost, the energy usage logic is to select the passive power modification plan. Other examples may include consideration of other power modification plans, e.g., additional voltage reduction steps prior to arrival at an intended processor idle state).
Regarding claim 2, Conrad discloses system of claim 1, wherein the power control unit further to set the voltage level to the operational voltage level when the first energy cost is less than the second energy cost(Paragraph 35, the energy usage logic is to determine an energy cost associated a first power modification plan (e.g., passive decay phase, and possibly unregulated idle phase). The energy usage logic is to determine an energy cost associated a second modification plan (e.g., actively managed voltage reduction by voltage regulator controller, active control of voltage at idle power state). The energy usage logic is to compare a passive plan energy cost associated with the passive modification plan to an active plan energy cost associated with the active modification plan. If the passive plan energy cost is greater than the active plan energy cost, the energy usage logic is to select the active power modification plan. If the active plan energy cost is greater than the passive plan energy cost, the energy usage logic is to select the passive power modification plan. Other examples may include consideration of other power modification plans, e.g., additional voltage reduction steps prior to arrival at an intended processor idle state).
Regarding claim 3, Conrad discloses system of claim 1, the power control unit further to determine the demotion threshold, wherein to determine the demotion threshold the power control unit to determine a capacitor decay voltage value over a time frame(Paragraphs 11, 30, The energy usage logic 130 is to determine the selection of the power modification plan based on available information, e.g., initial decay data, processor history, and hysteresis data. In an embodiment, the processor may receive an indication of a wake-up event during the voltage decay phase and may abort the decay to ramp up the processor voltage to the active voltage, which may affect actual energy usage of the system 100. Voltage reduction may be achieved through bleed-off of stored charge in the processor and the capacitors).
Regarding claim 4, Conrad discloses system of claim 3, wherein the capacitor decay voltage value over the time frame is to be stored in a look-up table(Paragraph 22, power modification plan is stored in a table of power modification plans, and each power modification plan may be associated with a corresponding processor application).
Regarding claim 5, Conrad discloses system of claim 3, wherein to determine the demotion threshold the power control unit further to calculate the second energy cost using the capacitor decay voltage(Paragraphs 11, 30, The energy usage logic 130 is to determine the selection of the power modification plan based on available information, e.g., initial decay data, processor history, and hysteresis data. In an embodiment, the processor may receive an indication of a wake-up event during the voltage decay phase and may abort the decay to ramp up the processor voltage to the active voltage, which may affect actual energy usage of the system 100. Voltage reduction may be achieved through bleed-off of stored charge in the processor and the capacitors).
Regarding claim 6, Conrad discloses system of claim 3, wherein the power control unit to redetermine the demotion threshold if an operating voltage of the device is changed(Paragraph 35, Other examples may include consideration of other power modification plans, e.g., additional voltage reduction steps prior to arrival at an intended processor idle state).
Regarding claim 7, Conrad discloses system of claim 1, wherein the power control unit further to compare the demotion threshold with an average idle cycle time, the power control unit to set the operational level to the device if the average idle cycle time is less than the demotion threshold(Paragraph 23, the prediction of the energy cost of the voltage reduction phase of a power modification plan may be based on data received from the VR controller 162 or stored in another location, e.g., voltage v. time for a previous voltage reduction, e.g., a length of time for the processor voltage to reach an idle voltage beginning at an active voltage in a previous power modification. For example, data may be recorded and stored for a most recent power modification (associated with a program application) including voltage reduction to a processor idle state, maintenance of the processor at the processor idle power for an idle time period, and reinstatement of the processor to an active processor state).
Regarding claim 8, Conrad discloses system of claim 7, wherein the power control unit further to track idle cycle times while the device is in operation to determine the average idle cycle time(Paragraph 23, the prediction of the energy cost of the voltage reduction phase of a power modification plan may be based on data received from the VR controller 162 or stored in another location, e.g., voltage v. time for a previous voltage reduction, e.g., a length of time for the processor voltage to reach an idle voltage beginning at an active voltage in a previous power modification. For example, data may be recorded and stored for a most recent power modification (associated with a program application) including voltage reduction to a processor idle state, maintenance of the processor at the processor idle power for an idle time period, and reinstatement of the processor to an active processor state).
Regarding claim 9, Conrad discloses apparatus comprising: a power control unit to communicate to a voltage regulator a voltage level to supply to a device(Fig. 1, Paragraph 11, a voltage regulator controller that controls a voltage regulator (VR), which typically is external to the processor), the voltage level including a shutdown level and an operational level, the voltage level based on a demotion threshold(Paragraph 11, first and second modification plan, Modification of the processor power level can be executed according to the selected power modification plan); wherein the demotion threshold is a time at which a first energy cost is equal to a second energy cost(Paragraph 26, The energy usage logic 130 may perform a comparison of the first energy cost to the second energy cost and may select the power management plan with the smaller energy cost. The VR controller 162 may perform the power modification according to the selected power modification plan. As stated in the specification, demotion threshold is typically the point where the energy cost for maintaining power to the device is approximately the same as or exceeds the energy cost of removing power to the device), wherein the first energy cost is a first amount of energy for the voltage regulator to supply the operational voltage level to the device and the second energy cost is a second amount of energy for the voltage regulator to supply the shutdown level to the device(Paragraph 35, the energy usage logic is to determine an energy cost associated a first power modification plan (e.g., passive decay phase, and possibly unregulated idle phase). The energy usage logic is to determine an energy cost associated a second modification plan (e.g., actively managed voltage reduction by voltage regulator controller, active control of voltage at idle power state). The energy usage logic is to compare a passive plan energy cost associated with the passive modification plan to an active plan energy cost associated with the active modification plan. If the passive plan energy cost is greater than the active plan energy cost, the energy usage logic is to select the active power modification plan. If the active plan energy cost is greater than the passive plan energy cost, the energy usage logic is to select the passive power modification plan. Other examples may include consideration of other power modification plans, e.g., additional voltage reduction steps prior to arrival at an intended processor idle state).
Regarding claim 10, Conrad discloses apparatus of claim 9, wherein the power control unit further to set the voltage level to the operational voltage level when the first energy cost is less than the second energy cost l(Paragraph 35, the energy usage logic is to determine an energy cost associated a first power modification plan (e.g., passive decay phase, and possibly unregulated idle phase). The energy usage logic is to determine an energy cost associated a second modification plan (e.g., actively managed voltage reduction by voltage regulator controller, active control of voltage at idle power state). The energy usage logic is to compare a passive plan energy cost associated with the passive modification plan to an active plan energy cost associated with the active modification plan. If the passive plan energy cost is greater than the active plan energy cost, the energy usage logic is to select the active power modification plan. If the active plan energy cost is greater than the passive plan energy cost, the energy usage logic is to select the passive power modification plan. Other examples may include consideration of other power modification plans, e.g., additional voltage reduction steps prior to arrival at an intended processor idle state).
Regarding claim 11, Conrad discloses apparatus of claim 9, the power control unit further to determine the demotion threshold, wherein to determine the demotion threshold the power control unit to determine a capacitor decay voltage value over a time frame(Paragraphs 11, 30, The energy usage logic 130 is to determine the selection of the power modification plan based on available information, e.g., initial decay data, processor history, and hysteresis data. In an embodiment, the processor may receive an indication of a wake-up event during the voltage decay phase and may abort the decay to ramp up the processor voltage to the active voltage, which may affect actual energy usage of the system 100. Voltage reduction may be achieved through bleed-off of stored charge in the processor and the capacitors).
Regarding claim 12, Conrad discloses apparatus of claim 11, wherein to determine the demotion threshold the power control unit further to calculate the second energy cost using the capacitor decay voltage(Paragraphs 11, 30, The energy usage logic 130 is to determine the selection of the power modification plan based on available information, e.g., initial decay data, processor history, and hysteresis data. In an embodiment, the processor may receive an indication of a wake-up event during the voltage decay phase and may abort the decay to ramp up the processor voltage to the active voltage, which may affect actual energy usage of the system 100. Voltage reduction may be achieved through bleed-off of stored charge in the processor and the capacitors).
Regarding claim 13, Conrad discloses apparatus of claim 9, wherein the power control unit further to compare the demotion threshold with an average idle cycle time, the power control unit to set the operational level to the device if the average idle cycle time is less than the demotion threshold(Paragraph 23, the prediction of the energy cost of the voltage reduction phase of a power modification plan may be based on data received from the VR controller 162 or stored in another location, e.g., voltage v. time for a previous voltage reduction, e.g., a length of time for the processor voltage to reach an idle voltage beginning at an active voltage in a previous power modification. For example, data may be recorded and stored for a most recent power modification (associated with a program application) including voltage reduction to a processor idle state, maintenance of the processor at the processor idle power for an idle time period, and reinstatement of the processor to an active processor state).
Regarding claim 14, Conrad discloses apparatus of claim 13, wherein the power control unit further to track idle cycle times while the device is in operation to determine the average idle cycle time(Paragraph 23, the prediction of the energy cost of the voltage reduction phase of a power modification plan may be based on data received from the VR controller 162 or stored in another location, e.g., voltage v. time for a previous voltage reduction, e.g., a length of time for the processor voltage to reach an idle voltage beginning at an active voltage in a previous power modification. For example, data may be recorded and stored for a most recent power modification (associated with a program application) including voltage reduction to a processor idle state, maintenance of the processor at the processor idle power for an idle time period, and reinstatement of the processor to an active processor state).
Regarding claim 15, Conrad discloses method comprising: communicating to a voltage regulator a voltage level to supply to a device when the device is idle(Fig. 1, Paragraph 11, a voltage regulator controller that controls a voltage regulator (VR), which typically is external to the processor), the voltage level including a shutdown level and an operational level(Paragraph 11, first and second modification plan, Modification of the processor power level can be executed according to the selected power modification plan), the voltage level based on a demotion threshold; wherein the demotion threshold is a time at which a first energy cost is equal to a second energy cost(Paragraph 26, The energy usage logic 130 may perform a comparison of the first energy cost to the second energy cost and may select the power management plan with the smaller energy cost. The VR controller 162 may perform the power modification according to the selected power modification plan. As stated in the specification, demotion threshold is typically the point where the energy cost for maintaining power to the device is approximately the same as or exceeds the energy cost of removing power to the device), wherein the first energy cost is a first amount of energy for the voltage regulator to supply the operational voltage level to the device and the second energy cost is a second amount of energy for the voltage regulator to supply the shutdown level to the device l(Paragraph 35, the energy usage logic is to determine an energy cost associated a first power modification plan (e.g., passive decay phase, and possibly unregulated idle phase). The energy usage logic is to determine an energy cost associated a second modification plan (e.g., actively managed voltage reduction by voltage regulator controller, active control of voltage at idle power state). The energy usage logic is to compare a passive plan energy cost associated with the passive modification plan to an active plan energy cost associated with the active modification plan. If the passive plan energy cost is greater than the active plan energy cost, the energy usage logic is to select the active power modification plan. If the active plan energy cost is greater than the passive plan energy cost, the energy usage logic is to select the passive power modification plan. Other examples may include consideration of other power modification plans, e.g., additional voltage reduction steps prior to arrival at an intended processor idle state).
Regarding claim 16, Conrad discloses method of claim 15, further comprising setting the voltage level to the operational voltage level when the first energy cost is less than the second energy cost l(Paragraph 35, the energy usage logic is to determine an energy cost associated a first power modification plan (e.g., passive decay phase, and possibly unregulated idle phase). The energy usage logic is to determine an energy cost associated a second modification plan (e.g., actively managed voltage reduction by voltage regulator controller, active control of voltage at idle power state). The energy usage logic is to compare a passive plan energy cost associated with the passive modification plan to an active plan energy cost associated with the active modification plan. If the passive plan energy cost is greater than the active plan energy cost, the energy usage logic is to select the active power modification plan. If the active plan energy cost is greater than the passive plan energy cost, the energy usage logic is to select the passive power modification plan. Other examples may include consideration of other power modification plans, e.g., additional voltage reduction steps prior to arrival at an intended processor idle state).
Regarding claim 17, Conrad discloses method of claim 15, further comprising determining a capacitor decay voltage value over a time frame(Paragraphs 11, 30, The energy usage logic 130 is to determine the selection of the power modification plan based on available information, e.g., initial decay data, processor history, and hysteresis data. In an embodiment, the processor may receive an indication of a wake-up event during the voltage decay phase and may abort the decay to ramp up the processor voltage to the active voltage, which may affect actual energy usage of the system 100. Voltage reduction may be achieved through bleed-off of stored charge in the processor and the capacitors).
Regarding claim 18, Conrad discloses method of claim 17, further comprising storing the capacitor decay voltage value over the time frame in a look-up table(Paragraph 22, power modification plan is stored in a table of power modification plans, and each power modification plan may be associated with a corresponding processor application).
Regarding claim 19, Conrad discloses method of claim 17, wherein to determine the demotion threshold further comprising calculating the second energy cost using the capacitor decay voltage(Paragraphs 11, 30, The energy usage logic 130 is to determine the selection of the power modification plan based on available information, e.g., initial decay data, processor history, and hysteresis data. In an embodiment, the processor may receive an indication of a wake-up event during the voltage decay phase and may abort the decay to ramp up the processor voltage to the active voltage, which may affect actual energy usage of the system 100. Voltage reduction may be achieved through bleed-off of stored charge in the processor and the capacitors).
Regarding claim 20, Conrad discloses method of claim 15, further comprising comparing the demotion threshold with an average idle cycle time, and setting the operational level to the device at the beginning of an idle cycle if the average idle cycle time is less than the demotion threshold(Paragraph 23, the prediction of the energy cost of the voltage reduction phase of a power modification plan may be based on data received from the VR controller 162 or stored in another location, e.g., voltage v. time for a previous voltage reduction, e.g., a length of time for the processor voltage to reach an idle voltage beginning at an active voltage in a previous power modification. For example, data may be recorded and stored for a most recent power modification (associated with a program application) including voltage reduction to a processor idle state, maintenance of the processor at the processor idle power for an idle time period, and reinstatement of the processor to an active processor state).
Conclusion
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/NIMESH G PATEL/Primary Examiner, Art Unit 2187