Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments & arguments, see Pg. 11 second to last paragraph, filed 11/4/2025, with respect to the rejection(s) of claim(s) 1-24 under Huang et al., US Application 20080316660A1 (hereinafter referred to as Huang) have been fully considered and are persuasive. Therefore, the previous rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Huang et al., US Application 20080316660A1 (hereinafter referred to as Huang) in view of Salcedo et al., US Application 20180158814A1 (hereinafter referred to as Salcedo). Salcedo teaches of modifying the ESD trigger circuit to include a resistor in conjunction with transistors to create a dynamic protection circuit that does not add capacitance to the integrated circuit.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 8, 10-12, & 15-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al., US Application 20080316660A1 (hereinafter referred to as Huang) in view of Salcedo et al., US Application 20180158814A1 (hereinafter referred to as Salcedo).
In regards to claim 1, Huang teaches of an electrostatic discharge (ESD) circuit (ESD circuit 500), comprising: an integrated circuit terminal (first conductive path 510; [Fig. 5B]); a pass transistor (switch unit 504; [Fig. 5B]) having a drain coupled to the integrated circuit terminal ([Fig. 5b]); a voltage node (VDD 530; [Fig. 5b]); a first ESD diode (transistor O6; [Fig. 5b]) (Examiner’s Note: The first ESD diode is equivalent to the transistor O6 because the gate and source are shorted together and functions the same as a diode.) coupled between the integrated circuit terminal and the voltage node ([Fig. 5b]); and an ESD trigger circuit (ESD detecting unit 503; [Fig. 5b]) coupled between a gate of the pass transistor and the voltage node, the ESD trigger circuit being configured to electrically couple the gate of the pass transistor to the voltage node in response to an electrostatic shock of the integrated circuit terminal (Examiner’s Note: Huang teaches the voltage node (VDD) coupled to the gate of transistor 01 and during an ESD event closes transistor 01 to direct the ESD voltage pulse to pass to the gate of the pass transistor (03). During normal operation, the voltage node will be high and the gate of the pass transistor (03) is supplied by the return (VSS) which means the gate is isolated from the voltage node. Huang teaches in [0047] of the ESD current being bypassed through switch 505b to conductive path 530. Therefore, it is understood that Huang teaches the ESD trigger circuit being electrically coupled to the gate of the pass transistor.) and to isolate the gate of the pass transistor from the voltage node in an absence of the electrostatic shock of the integrated circuit terminal ([0050] & [Fig. 5B] e.g., ESD, positive pulse, “transistor O3 is not conducted”) (Examiner’s Note: Paragraph 0050 describes an ESD event on the pad 501 which is tied to the first conductive path 510 and how the one of the pass transistors O3 does not conduct and prevents the ESD event from being passed to the core circuit.).
Huang does not teach wherein the ESD trigger circuit is configured such that its coupling does not impose a capacitive load on the integrated circuit terminal.
Salcedo teaches wherein the ESD trigger circuit (low capacitance protection circuit 16/246; [Fig. 1B & 5A]) is configured such that its coupling (implicit; [Fig. 1B]) does not impose (low; [0054]) a capacitive load (capacitance; [0054]) on the integrated circuit terminal (node between 4 and load terminal of transistor 12/2; [Fig. 1B & 5A]) (Examiner’s Note: It is understood that the protection circuit 16 does not impose its low capacitance onto the integrated circuit, internal circuit 4, because of the dynamically activated trigger signal.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified Huang in order to incorporate wherein the ESD trigger circuit is configured such that its coupling does not impose a capacitive load on the integrated circuit terminal as taught by Salcedo. It is understood that the resistor in the low capacitance protection circuit and reduces the capacitance to a low value of the circuit and the capacitance left is the parasitic capacitance in the transistor (Salcedo, [0027] & [0030]). The motivation for doing so is to improve the circuit to have robust overstress protection and excellent signaling performance as taught by Salcedo in [0054].
In regards to claim 2, the limitations have been taught above in claim 1. In addition, Huang further teaches wherein the pass transistor is an n-type metal-oxide-semiconductor (NMOS) pass transistor ([Fig. 5B] e.g., transistor O4, switch unit 504).
In regards to claim 3, the limitations have been taught above in claim 1 & 2. In addition, Huang further teaches wherein the voltage node is a power supply node for a power supply voltage ([Fig. 5B] e.g., VDD 530).
In regards to claim 4, the limitations have been taught above in claim 1 & 2. In addition, Huang further teaches wherein the integrated circuit terminal is a data terminal for a universal serial bus (USB) interface ([0006] e.g., program voltage, “voltage with time variation”). The limitation of a connection to a data terminal on a USB interface cannot be relied upon to distinguish over Huang because such is directed to either the intended use or manner of operating the circuitry of the instant invention.
In regards to claim 5, the limitations have been taught above in claim 1, 2, & 3. In addition, Huang further teaches the circuit further comprising: a negative voltage node (VSS 520) for a negative voltage; and a second ESD diode (transistor O5) coupled between the integrated circuit terminal and the negative voltage node ([Fig. 5B]).
In regards to claim 8, the limitations have been taught above in claim 1, 2, & 3. In addition, Huang further teaches wherein the ESD trigger circuit includes a first PMOS transistor (transistor O2) having a source coupled to the power supply node and a drain coupled to the gate of the pass transistor ([Fig. 5B]).
In regards to claim 10, the limitations have been taught above in claim 1. In addition, Huang further teaches wherein the pass transistor is a PMOS transistor ([Fig. 5B] e.g., transistor O3).
In regards to claim 11, the limitations have been taught above in claim 1 & 10. In addition, Huang further teaches wherein the voltage node is a negative voltage node for a negative voltage ([Fig. B] e.g., VSS 520). VSS is commonly understood as being the most negative voltage. Huang teaches that VSS is less than VDD.
In regards to claim 12, the limitations have been taught above in claim 1 & 10. In addition, Huang further teaches the circuit further comprising: a second ESD diode (transistor O5) coupled between the integrated circuit terminal and a power supply node for a power supply voltage ([Fig. 5B] e.g., transistor O5, VDD 530, first conductive path 510). The second ESD diode is equivalent to the transistor O5 because the transistor has the source and gate tied together which makes the transistor function as a diode.
In regards to claim 15, Huang teaches a method of electrostatic discharge (ESD) circuit (ESD circuit 500), comprising: receiving a charge at a terminal (pad; [Fig. 5B]) of an integrated circuit from an electrostatic shock (ESD; [0050]); conducting the charge from the terminal through a diode (transistor O6; [0050]) (Examiner’s Note: The first ESD diode is equivalent to the transistor O6 because the gate and source are shorted together and functions the same as a diode.) to a voltage node (VDD 530; [0050]) to pulse a voltage of the voltage node; and electrically coupling the voltage node through an ESD trigger circuit (ESD detecting unit 503; [0050]) to a gate of a pass transistor (switch unit 504; [0050]) having a drain coupled to the terminal in response to a detection of the pulse of the voltage of the voltage node ([0047], [0050] & [Fig. 5B] e.g., ESD, positive pulse) (Examiner’s Note: Huang teaches the voltage node (VDD) coupled to the gate of transistor 01 and during an ESD event closes transistor 01 to direct the ESD voltage pulse to pass to the gate of the pass transistor (03). During normal operation, the voltage node will be high and the gate of the pass transistor (03) is supplied by the return (VSS) which means the gate is isolated from the voltage node. Huang teaches in [0047] of the ESD current being bypassed through switch 505b to conductive path 530. Therefore, it is understood that Huang teaches the ESD trigger circuit being electrically coupled to the gate of the pass transistor.); and isolating the voltage node from the gate of the pass transistor after a dissipation of the electric shock ([0050] & [Fig. 5B] e.g., ESD, positive pulse, “transistor O3 is not conducted”) (Examiner’s Note: Paragraph 0050 describes an ESD event on the pad 501 which is tied to the first conductive path 510 and how the one of the pass transistors O3 does not conduct and prevents the ESD event from being passed to the core circuit.).
Huang does not teach wherein the ESD trigger circuit is configured such that its coupling does not impose a capacitive load on the integrated circuit terminal.
Salcedo teaches wherein the ESD trigger circuit (low capacitance protection circuit 16/246; [Fig. 1B & 5A]) is configured such that its coupling (implicit; [Fig. 1B]) does not impose (low; [0054]) a capacitive load (capacitance; [0054]) on the integrated circuit terminal (node between 4 and load terminal of transistor 12/2; [Fig. 1B & 5A]) (Examiner’s Note: It is understood that the protection circuit 16 does not impose its low capacitance onto the integrated circuit, internal circuit 4, because of the dynamically activated trigger signal.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified Huang in order to incorporate wherein the ESD trigger circuit is configured such that its coupling does not impose a capacitive load on the integrated circuit terminal as taught by Salcedo. It is understood that the resistor in the low capacitance protection circuit and reduces the capacitance to a low value of the circuit and the capacitance left is the parasitic capacitance in the transistor (Salcedo, [0027] & [0030]). The motivation for doing so is to improve the circuit to have robust overstress protection and excellent signaling performance as taught by Salcedo in [0054].
In regards to claim 16, the claim limitations have been taught above in claim 15. In addition, Huang further teaches wherein receiving the charge at the terminal comprises receiving a positive charge, and wherein conducting the charge from the terminal through the diode to the voltage node comprises conducting the positive charge from the terminal to a power supply node for a power supply voltage ([0050] & [Fig. 5B] e.g., pad 501, VDD 530, transistor O6).
In regards to claim 17, the claim limitations have been taught above in claim 15. In addition, Huang further teaches wherein receiving the charge at the terminal comprises receiving a negative charge, and wherein conducting the charge from the terminal through the diode to the voltage node comprises conducting the negative charge from the terminal to a negative voltage node for a negative voltage ([0049] & [Fig. 5B] e.g., VSS 520, pad 501, ESD current, bypassed).
In regards to claim 18, Huang teaches an electrostatic discharge (ESD) circuit (500; [Fig. 5B]), comprising: an integrated circuit terminal (510; [Fig. 5B]); a node for a high-speed data signal (pad 501; [Fig. 5B]); a pass transistor (switch unit 504; [Fig. 5B]) coupled between the node for the high-speed data signal and the integrated circuit terminal; and an ESD trigger circuit (ESD detecting unit 503; [Fig. 5B]) configured to electrically couple a power supply node (VDD; [Fig. 5B]) for a power supply voltage (VDD; [Fig. 5B]) to a gate of the pass transistor in response to a positive electrostatic shock to the integrated circuit terminal ([0050] & [Fig. 5B] e.g., ESD, positive pulse) (Examiner’s Note: Huang teaches the voltage node (VDD) coupled to the gate of transistor 01 and during an ESD event closes transistor 01 to direct the ESD voltage pulse to pass to the gate of the pass transistor (03). During normal operation, the voltage node will be high and the gate of the pass transistor (03) is supplied by the return (VSS) which means the gate is isolated from the voltage node. Huang teaches in [0047] of the ESD current being bypassed through switch 505b to conductive path 530. Therefore, it is understood that Huang teaches the ESD trigger circuit being electrically coupled to the gate of the pass transistor.) and configured to isolate the gate of the pass transistor from the power supply node in an absence of the positive electrostatic shock ([0050] & [Fig. 5B] e.g., ESD, positive pulse, “transistor O3 is not conducted”) (Examiner’s Note: Paragraph 0050 describes an ESD event on the pad 501 which is tied to the first conductive path 510 and how the one of the pass transistors O3 does not conduct and prevents the ESD event from being passed to the core circuit.).
Huang does not teach wherein the ESD trigger circuit is configured such that its coupling does not impose a capacitive load on the integrated circuit terminal.
Salcedo teaches wherein the ESD trigger circuit (low capacitance protection circuit 16/246; [Fig. 1B & 5A]) is configured such that its coupling (implicit; [Fig. 1B]) does not impose (low; [0054]) a capacitive load (capacitance; [0054]) on the integrated circuit terminal (node between 4 and load terminal of transistor 12/2; [Fig. 1B & 5A]) (Examiner’s Note: It is understood that the protection circuit 16 does not impose its low capacitance onto the integrated circuit, internal circuit 4, because of the dynamically activated trigger signal.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified Huang in order to incorporate wherein the ESD trigger circuit is configured such that its coupling does not impose a capacitive load on the integrated circuit terminal as taught by Salcedo. It is understood that the resistor in the low capacitance protection circuit and reduces the capacitance to a low value of the circuit and the capacitance left is the parasitic capacitance in the transistor (Salcedo, [0027] & [0030]). The motivation for doing so is to improve the circuit to have robust overstress protection and excellent signaling performance as taught by Salcedo in [0054].
In regards to claim 19, the claim limitations have been taught above in claim 18. In addition, Huang further teaches the circuit further comprising: a diode (O6) having an anode coupled to the integrated circuit terminal and a cathode coupled to the power supply node ([Fig. 5B] e.g., first conductive path 510, VDD 530, transistor O6).
In regards to claim 20, the claim limitations have been taught above in claim 18. In addition, Huang further teaches wherein the integrated circuit terminal is an integrated circuit terminal for an integrated circuit included within a cellular telephone. The limitation of “within a cellular telephone” cannot be relied upon to distinguish over Huang because such is directed to either the intended use or manner of operating the circuitry of the instant invention.
In regards to claim 21, the claim limitations have been taught above in claim 18. In addition, Huang further teaches wherein the pass transistor is an NMOS pass transistor ([Fig. 5B] e.g., transistor O4, switch unit 504).
In regards to claim 22, Huang teaches an electrostatic discharge (ESD) circuit (500; [Fig. 5b]), comprising: an integrated circuit terminal (510; [Fig. 5b]); a node for a high-speed data signal (pad 501; [Fig. 5b]); a pass transistor (switch unit 504; [Fig. 5b]) coupled between the node for the high-speed data signal and the integrated circuit terminal; and an ESD trigger circuit configured to electrically couple a negative voltage node (VSS; [Fig. 5b]) for a negative voltage (VSS; [Fig. 5b]) to a gate of the pass transistor in response to a negative electrostatic shock to the integrated circuit terminal ([0050] & [Fig. 5B] e.g., ESD, positive pulse) (Examiner’s Note: Huang teaches the voltage node (VDD) coupled to the gate of transistor 01 and during an ESD event closes transistor 01 to direct the ESD voltage pulse to pass to the gate of the pass transistor (03). During normal operation, the voltage node will be high and the gate of the pass transistor (03) is supplied by the return (VSS) which means the gate is isolated from the voltage node. Huang teaches in [0047] of the ESD current being bypassed through switch 505b to conductive path 530. Therefore, it is understood that Huang teaches the ESD trigger circuit being electrically coupled to the gate of the pass transistor.) and configured to isolate the gate of the pass transistor from the power supply node in an absence of the positive electrostatic shock ([0050] & [Fig. 5B] e.g., ESD, positive pulse, “transistor O3 is not conducted”) (Examiner’s Note: Paragraph 0050 describes an ESD event on the pad 501 which is tied to the first conductive path 510 and how the one of the pass transistors O3 does not conduct and prevents the ESD event from being passed to the core circuit.).
In regards to claim 23, the limitations have been taught above in claim 22. In addition, Huang further teaches of the circuit further comprising: a diode (transistor O5) having an anode coupled to the negative voltage node and a cathode coupled to the integrated circuit terminal ([Fig. 5B] e.g., VSS 520, first conductive path 510). The diode is equivalent to the transistor O5 because the gate and source are tied together which makes the transistor function as a diode.
In regards to claim 24, the claim limitations have been taught above in claim 22. In addition, Huang further teaches wherein the pass transistor is a PMOS pass transistor ([Fig. 5B] e.g., switch circuit 504, transistor O3).
Claim(s) 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al., US Application 20080316660A1 (hereinafter referred to as Huang) in view of Salcedo et al., US Application 20180158814A1 (hereinafter referred to as Salcedo) and in further view of Sivakumar et al., US Application 20230148160A1 (hereinafter referred to as Sivakumar).
In regards to claim 6, the limitations have been taught above in claims 1-3 & 5. Huang & Salcedo do not explicitly disclose, but, Sivakumar teaches the circuit further comprising: a first transistor (S3 transistor 306) coupled between the negative voltage node (VSS 312) and the gate of the pass transistor (S1 transistor 302); and a controller (En_sw 314) configured to switch on the first transistor to charge the gate of the pass transistor to the negative voltage during an audio mode of operation ([Fig. 3] e.g., S3, S1, VSS, En_sw, 308).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang & Salcedo to incorporate the teachings of Sivakumar to substitute the switch unit 503 with voltage divider 308 and S3. The limitation of “during an audio mode of operation” cannot be relied upon to distinguish over Huang, Salcedo and Sivakumar because such is directed to either the intended use or manner of operating the circuitry of the instant invention. The motivation for substituting the switch unit 503 with the voltage divider 308 and transistor S3 is have a reliable ESD damping circuit when the enable circuit may unintentionally rise due to a string of buffer amplifiers as taught by Sivakumar in paragraph [0047].
In regards to claim 7, the limitations have been taught above in claims 1-3 & 5-6. Huang & Salcedo do not explicitly disclose, but, Sivakumar further teaches the circuit further comprising: a second transistor (S2) coupled between the negative voltage node (VSS 312) and a bulk of the pass transistor, wherein the controller (En_sw 314) is further configured to switch on the second transistor during the audio mode of operation ([Fig. 3] e.g., S2, VSS 312, En_sw 314).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang & Salcedo to incorporate the teachings of Sivakumar to substitute the switch unit 503 with voltage divider 308, S3 and S2. The limitation of “during an audio mode of operation” cannot be relied upon to distinguish over Huang, Salcedo and Sivakumar because such is directed to either the intended use or manner of operating the circuitry of the instant invention. The motivation for substituting the switch unit 503 with the voltage divider 308 and transistors S3 & S2 is have a reliable ESD damping circuit when the enable circuit may unintentionally rise due to a string of buffer amplifiers as taught by Sivakumar in paragraph [0047].
Claim(s) 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al., US Application 2008316660A1 (hereinafter referred to as Huang) in view of Salcedo et al., US Application 20180158814A1 (hereinafter referred to as Salcedo) and in further view of Harit Mathur et al., US Application 20200153241A1 (hereinafter referred to as Harit Mathur).
In regards to claim 6, the limitations have been taught above in claims 1-3 & 5. Huang & Salcedo do not explicitly disclose, but, Harit Mathur teaches the circuit further comprising: a first transistor (transistor M3) coupled between the negative voltage node (VSSO 606) and the gate of the pass transistor (transistor M7); and a controller (First Timer Circuit 608) configured to switch on the first transistor to charge the gate of the pass transistor to the negative voltage during an audio mode of operation ([0056] & [Fig. 7] e.g., initial activation circuit 612, first driver circuit 614, second driver circuit 632, M3, VSSO, M7, ESDECT).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang & Salcedo to incorporate the teachings of Harit Mathur to substitute the switch unit 503 with the first driver circuit 614. The limitation of “during an audio mode of operation” cannot be relied upon to distinguish over Huang, Salcedo and Harit Mathur because such is directed to either the intended use or manner of operating the circuitry of the instant invention. The signal ESDECT controls when the ESD circuit is activated as discussed in paragraph [0056]. The signal originates from the first timer circuit 608. Therefore, the first timer circuit 608 is the controller. The pass transistor M7 is a PMOS. Claim 2 says that the pass transistor must be an NMOS. It is an engineering design choice to have the pass transistor as an N-type. It is common in the art for one to substitute a normally open for a normally closed switch. The motivation for substituting the switch unit 503 with the first driver circuit is to control the timing of an ESD event to be ON only when an ESD event is occurring as taught by Harit Mathur in paragraph [0067] & [0072].
In regards to claim 7, the limitations have been taught above in claims 1-3 & 5-6. Huang & Salcedo do not explicitly disclose, but, Harit Mathur further teaches the circuit further comprising: a second transistor (transistor M8) coupled between the negative voltage node (VSS 312) and a bulk of the pass transistor, wherein the controller (first timer circuit 608) is further configured to switch on the second transistor during the audio mode of operation ([Fig. 7] e.g., initial activation circuit 612, first driver circuit 614, second driver circuit 632, M7, M3, M8, VSSO, ESDECT).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang & Salcedo to incorporate the teachings of Harit Mathur to substitute the switch unit 503 with the first and second drivers 614 and 632. The limitation of “during an audio mode of operation” cannot be relied upon to distinguish over Huang, Salcedo and Harit Mathur because such is directed to either the intended use or manner of operating the circuitry of the instant invention. The motivation for substituting the switch unit 503 with the first and second drivers 614 and 632 is to control the timing of an ESD event to be ON only when an ESD event is occurring and the second drive 632 keeps the ESD protection on for a short while after the ESD event has occurred as taught by Harit Mathur in paragraph [0067] & [0072].
Claim(s) 9 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al., US Application 2008316660A1 (hereinafter referred to as Huang) in view of Salcedo et al., US Application 20180158814A1 (hereinafter referred to as Salcedo) and in further view of Kwong et al., US Application 20030071662A1 (hereinafter referred to as Kwong).
In regards to claim 9, the limitations have been taught above in claims 1-3. Huang does not explicitly disclose, but, Kwong teaches wherein the ESD trigger circuit further comprises a low-pass filter ([0020] & [Fig. 2] e.g., I/O protection circuit 18).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang & Salcedo to incorporate the teachings of Kwong to add the I/O protection circuit (low-pass filter circuit) 18 to the ESD trigger circuit. A low-pass filter can be a type of RC circuit and the I/O protection circuit is an RC circuit. The motivation for adding the I/O protection circuit is to add additional protection to a sensitive input as taught by Kwong in paragraph [0021]. Kwong’s teaching has the additional benefit of the protection circuit being there only during ESD events, so as not to interfere with the normal operation.
In regards to claim 13, the limitations have been taught above in claims 1, 10, and 12. Huang does not explicitly disclose, but, Kwong teaches the circuit further comprising: a first PMOS transistor (66) coupled between the gate of the pass transistor (56) and the power supply node (I/O VDD); and a controller (I/O GND) configured to switch on the first PMOS transistor during an audio mode of operation ([Fig. 2] e.g., transistors 66 & 56, I/O VDD, I/O GND).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted Huang and Salcedo’s teachings of a switch unit 504 and an ESD trigger circuit 503 with Kwong’s teaching of an ESD protection circuit 50. The limitation of “during an audio mode of operation” cannot be relied upon to distinguish over Huang, Salcedo and Kwong because such is directed to either the intended use or manner of operating the circuitry of the instant invention. The motivation for the substitution would be to have the ability to disconnect the ESD protection from the RC network during normal operation as taught by Kwong in paragraph [0021].
In regards to claim 14, the limitations have been taught above in claims 1, 10, and 12-13. Huang does not explicitly disclose, but, Kwong teaches the circuit further comprising: a second PMOS transistor (52) coupled between a bulk of the pass transistor and the power supply node, wherein the controller is further configured to switch on the second PMOS transistor during the audio mode of operation ([Fig. 2] e.g., transistors 66 & 56, I/O VDD, I/O GND).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted Huang and Salcedo’s teachings of a switch unit 504 and an ESD trigger circuit 503 with Kwong’s teaching of an ESD protection circuit 50. The limitation of “during an audio mode of operation” cannot be relied upon to distinguish over Huang, Salcedo and Kwong because such is directed to either the intended use or manner of operating the circuitry of the instant invention. The motivation for the substitution would be to have the ability to disconnect the ESD protection from the RC network during normal operation as taught by Kwong in paragraph [0021].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMANTHA L FAUBERT whose telephone number is (703)756-1311. The examiner can normally be reached Monday - Friday 8AM - 5PM.
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SAMANTHA LYNETTE FAUBERT
Examiner
Art Unit 2836
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838