Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendments to claims 1, 2, 11, 21 and 24 submitted on July 1, 2026 are acknowledged and have since been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 22 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 22 cites the air core inductor comprising “a plurality of conductive loops” but the specification and drawings to not clearly point out what is intended to be interpreted as “conductive loops.” Examiner notes that the first conductive structure and second conductive structures comprise a conductive material looped around the core substrate. For examination purposes, “conductive loops” are interpreted to refer to a conductive material of the first and second conductive structure “looping” around the core substrate as part of the air core inductor.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 10 and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chatterjee (US 20190206780 A1).
Regarding Claim 1, Chatterjee teaches a package core (300, shown Figs. 3a-3h), comprising:
a core substrate (301) comprising glass (see [0040]);
a first opening (304 left, shown Fig. 3h) through the core substrate;
a second opening (304 right, shown Fig. 3h) through the core substrate and adjacent to the first opening;
a first structure (layers 306, 314 and 316, a first structure being around a middle portion shown in Fig. 3e) around the core substrate between the first opening and the second opening (shown Fig. 3e and Fig. 3h), wherein the first structure is electrically conductive (306 and 314 being a magnetic material, see also [0032] and 316 being a conductive material like copper, see [0043]); and
a second structure around the core substrate outside of the first opening and the second opening (shown Fig. 3h), wherein the second structure is electrically conductive (the second structure being materially the same as the first structure), wherein the first structure and the second structure are in direct contact with a top, sides, and a bottom of the glass of the core substrate (shown Fig. 3h).
Regarding Claim 2, Chatterjee teaches the package core of claim 1, wherein a seed layer (306, see [0041]) is included in the first structure and the second structure.
Regarding Claim 3, Chatterjee teaches the package core of claim 1, wherein the first structure and the second structure comprise an inductor (see [0042]).
Regarding Claim 4, Chatterjee teaches the package core of claim 1, wherein an air gap is provided between the first structure and the second structure (see [0041]).
Regarding Claim 10, Chatterjee teaches the package core of claim 1, wherein the package core is coupled to a processor of a computing system (see[0050]).
Regarding Claim 21, Chatterjee teaches a package substrate (see Figs. 3a-3h), comprising:
a core (301), wherein the core comprises glass (see [0040]);
buildup layers (311) above and below the core (shown Fig. 3h); and
an air core inductor embedded in the core (see [0040] describing an “in-package inductor” defined by magnetic layers 314 and air gaps 304), wherein the air core inductor comprises a first conductive structure (portions of 306, 314 and 316 surrounding a central portion of the glass substrate, see also Fig. 3e) and a second conductive structure (remaining portions of 306, 314 and 316) that are separated from each other by an air gap (304, see [0041]) wherein the first structure and the second structure are in direct contact with a top, sides, and a bottom of the glass of the core (shown Fig. 3h).
Regarding Claim 22, Chatterjee teaches the package substrate of claim 21, wherein the air core inductor comprises a plurality of conductive loops (interpreted as loops of conductive material surrounding the air gaps, see also [0042]).
Regarding Claim 23, Chatterjee teaches the package substrate of claim 21, wherein the first conductive structure and the second conductive structure pass through a thickness of the core (shown Fig. 3h).
Regarding Claim 24, Chatterjee teaches an electronic system, comprising:
a board (not shown, see [0049] describing the shown package structures further being coupled to any suitable type of structure, such as a circuit board);
a package substrate (300, shown Fig. 3h) coupled to the board (see [0049]), wherein the package substrate comprises:
an air core inductor embedded in the core (see [0040] describing an “in-package inductor” defined by magnetic layers 314 and air gaps 304) the core comprising glass (see [0040], wherein the air core inductor is in direct contact with a top, sides, and a bottom of the glass core (shown Fig. 3h), of the package substrate; and
a die (see [0049] further describing a die being coupled to the package structure) coupled to the package substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-7, 9 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chatterjee (US 20190206780 A1) in further view of Garner (US 20210359185 A1).
Regarding Claim 6, Chatterjee teaches the package core of claim 1, wherein a sidewall of the first structure and a sidewall of the second structure are substantially vertical (shown Fig. 3h).
Chatterjee further illustrates embodiments (see 100 and 200 of Figs. 1 and 2i respectively) wherein sidewalls of vias extending through a glass core substrate are tapered.
Garner further teaches a device wherein vias may be tapered along multiple directions similar to the vias shown in Figs. 1 and 2i of Chatterjee (see also Garner: [0032] and Fig. 2D).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a suitable shape for minimizing an inner diameter of a via of the device of Chatterjee as this would enable close proximity to adjacent components thus minimizing overall device footprint (see also Garner: [0032-0034]).
More specifically, this modification would teach that the sidewall of the first structure and the sidewall of the second structure are tapered.
Regarding Claim 7, Chatterjee as modified by Garner teaches the package core of claim 6, wherein the sidewall of the first structure and the sidewall of the second structure are each tapered in a first direction and a second direction.
Regarding Claim 9, Chatterjee teaches the package core of claim 1, but is silent regarding a thickness of the core substrate and aspect ratio of the first and second openings. Garner teaches a method of forming vias (see Figs. 2A-2D) similar to the opening of Chatterjee used in electronic components, like inductors (see Garner: [0034]) wherein a thickness of a glass substrate may be 300 microns (see [0028]) and an aspect ratio of the vias may be greater than 5:1 (see also [0032]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the dimensions and techniques described by Garner to the device of Chatterjee as this would enable relaxed alignment tolerances during manufacturing and close proximity between electronic components, thus reducing overall device footprint (see also [0033-0034]).
Specifically, Garner as applied to Chatterjee would teach a thickness of the core substrate being between 50 microns and 1000 microns and wherein aspect ratios of the first opening and the second opening are approximately 5:1 or greater.
Regarding Claim 25, Chatterjee teaches the electronic system of claim 24, wherein the air core inductor passes through a thickness of the core (shown Fig. 3h), and wherein sidewalls of the air core inductor are substantially vertical (shown Fig. 3h).
Chatterjee further illustrates embodiments (see 100 and 200 of Figs. 1 and 2i respectively) wherein sidewalls of vias extending through a glass core substrate are tapered.
Garner further teaches a device wherein vias may be tapered along multiple directions similar to the vias shown in Figs. 1 and 2i of Chatterjee (see also Garner: [0032] and Fig. 2D).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a suitable shape for minimizing an inner diameter of a via of the device of Chatterjee as this would enable close proximity to adjacent components thus minimizing overall device footprint (see also Garner: [0032-0034]).
More specifically, this modification would teach that the sidewall of the first structure and the sidewall of the second structure are tapered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 21 and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.P.B./Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights