Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 23, 2026 has been entered.
Response to Amendment
Amendments to claims 1, 2, 4, 11, 13 and 16 submitted January 23, 2026 are acknowledged and have since been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 11 and 16 recite the limitation "the same material" in reference to a material of the phase change material layers. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes, “the same material” is interpreted to mean “a same material” wherein a material of a first phase change material layer and a second phase change material layer are a same material composition. Claims 2-10, 12-15 and 17-20 are further rejected due to their dependence on claims 1, 11 and 16 respectively and lack of further clarity.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210313397 A1) in further view of Goux (US 20120069645 A1) and Ding (CN 108987567 A).
Regarding Claim 1, Lee teaches a variable resistance memory device (1000, shown Fig. 14A), comprising:
a substrate (110);
a first conductive line (120-1) extending in a first horizontal direction on the substrate (see also perspective of Fig. 3A);
a second conductive line (180-1) extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction (shown Fig. 14A); and
a memory cell (ML-1) at an intersection between the first conductive line and the second conductive line, the memory cell having a selection element layer (140), an intermediate electrode layer (134), and a variable resistance layer (150).
Lee further describes the variable resistance layer comprising multiple phase change material layers and a diffusion barrier layer between at least two phase change material layers with different physical properties, wherein a horizontal width is decreased toward a center of the variable resistance layer. The width of each phase change material layer is dependent on a location of the respective phase change material layer in the stack wherein a profile of the variable resistance layer has a minimum width in the first horizontal direction at a center of the stack and a maximum width in the first horizontal direction at opposing ends of the stack in the vertical direction. Lee does not explicitly teach the variable resistance layer having a stepped profile and comprising a plurality of diffusion barrier layers, wherein a width of each of the diffusion barrier layers in the first horizontal direction is dependent on a position of the respective diffusion barrier layer in the vertical direction to form the stepped profile of the variable resistance layer.
Goux teaches a similar phase change memory cell (shown Fig. 6) wherein a plurality of phase change material layers (layers 50, 52, 54, 56 and 58) are clearly defined in a step structure, which makes up a variable resistance layer due to a central first constriction, second constriction and third constriction (see described in [0060]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the defined constriction regions of phase change material layers within the variable resistance layer of Lee as this would allow each memory cell to store more than one bit thus increasing data storage (see [0007]).
As applied to Lee, this modification would teach the variable resistance layer comprising multiple defined phase change material layers which comprise sidewalls having a stair profile.
Lee as modified by Goux does not explicitly describe a width of a diffusion barrier layer or a plurality of diffusion barrier layers disposed alternating with the plurality of phase change material layers.
Ding teaches a memory device comprising a phase change memory layer (102, see Fig. 1) wherein a plurality of diffusion barrier layers (1b) are implemented between a plurality of phase change material layers (1a) and a width of each diffusion barrier layer matches a width of a corresponding phase change material layer (shown Fig. 1). It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to ensure a width along a horizontal direction of each diffusion barrier layer is at least the same as a width of an adjoining phase change material layer to ensure diffusion between each of the phase change material layers is effectively inhibited. Furthermore, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a plurality of diffusion barrier layers between multiple phase change material layers as this would reduce power consumption while inhibiting element diffusion during the repeated phase transition process, thus improving stability of the memory layer.
More specifically Lee as modified by Goux and Ding would teach the variable resistance layer has a stepped profile and comprises a plurality of phase change material layers and a plurality of diffusion barrier layers stacked alternately in a vertical direction,
wherein the width of each of the phase change material layers in the first horizontal direction is dependent on a location of the respective phase change material layer in the stack and a width of each of the diffusion barrier layers in the first horizontal direction is dependent on a position of the respective diffusion barrier layer in the vertical direction to form the stepped profile of the variable resistance layer,
wherein the stepped profile has a minimum width in the first horizontal direction at a center of the stack in the vertical direction and a maximum width in the first horizontal direction at opposing ends of the stack in the vertical direction,
wherein each phase change material layer is formed of the same material;
wherein adjacent phase change material layers formed of the same material are separated by a respective diffusion barrier layer, and
wherein the phase change material layer at the center of the stack in the vertical direction has a width in the first horizontal direction that is less that the minimum width in the horizontal direction of the diffusion barrier layers.
Regarding Claim 2, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 1, wherein the phase change material layers include a first phase change material layer at a lowermost end of the variable resistance layer and a second phase change material layer at an uppermost end of the variable resistance layer (shown Ding: Fig. 1).
Regarding Claim 3, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 2, wherein, as seen from a side view, widths of the phase change material layers and of the diffusion barrier layers decrease toward a center of the stack (as modified by Goux, wherein the profile of the diffusion barrier layers corresponds to that of the phase change material layers as suggested in Lee).
Regarding Claim 4, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 2, further comprising an upper electrode layer (136) on the variable resistance layer, wherein a voltage applied from the upper electrode layer and the intermediate electrode layer to the variable resistance layer is respectively distributed to the phase change material layers as different voltages in accordance with the capacitance of the phase change material layers (as modified by Goux, see also [0058-0060]).
Regarding Claim 5, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 4, wherein a first voltage (see described in [0032], drawn to an earlier embodiment of Goux wherein a higher voltage is applied to initiate a phase change of the outermost phase change material layers, see further [0031-0033] and Fig. 1) distributed to the first and second phase change material layers is greater than a second voltage distributed to other ones of the phase change material layers (described in Goux: [0031-0033]).
Regarding Claim 6, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 5, wherein, in accordance with a difference between the first voltage and the second voltage, the memory cell is a multi-level cell (see [0007] of Goux).
Regarding Claim 7, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 2, wherein the phase change material layers include at least one of Sb2Te3 and Bi2Te3 (see [0050] describing at least an Sb-Te layer, which is known in the art as antimony telluride having the chemical formula Sb2Te3). As modified by Ding, at least one of TiTe2, NiTe2, MoTe2, and ZrTe2 are implemented as a material of the diffusion barrier layers.
Regarding Claim 8, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 1, further comprising a spacer (160) surrounding sidewalls of the variable resistance layer, the spacer having an internal sidewall having a shape complementary with respect to the shape of stairs of the variable resistance layer (shown Fig. 14A).
Regarding Claim 9, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 8, wherein the variable resistance layer has a confined heterostructure (as modified by Goux above).
Regarding Claim 10, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 1, wherein the selection element layer includes an ovonic threshold switching (OTS) material (see Lee: [0046]).
Regarding Claim 11, Lee teaches a variable resistance memory device (1000, shown Fig. 14A), comprising:
a substrate (110);
a first conductive line (120-1) extending in a first horizontal direction (as viewed in Fig. 14A, see also perspective of Fig. 3A) on the substrate;
a second conductive line (180-1) extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction (shown Fig. 14A, see also perspective of Fig. 3A); and
a memory cell (ML-1) at an intersection between the first conductive line and the second conductive line (shown Fig. 14A), the memory cell including a variable resistance layer (150) having a stack of alternating phase change material layers and at least one diffusion barrier layer (see described in [0050]) between at least two phase change material layers, areas of the phase change material layers decreasing toward a center of the variable resistance layer (see Fig. 14A and [0044] describing a recess 150R formed at the sidewalls of the variable resistance memory layer).
Goux teaches a similar phase change memory cell (shown Fig. 6) wherein a plurality of phase change material layers (layers 50, 52, 54, 56 and 58) are clearly defined in a step structure, which makes up a variable resistance layer due to a central first constriction, second constriction and third constriction (see described in [0060]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the defined constriction regions of phase change material layers within the variable resistance layer of Lee as this would allow each memory cell to store more than one bit thus increasing data storage (see [0007]).
As applied to Lee, this modification would teach the variable resistance layer comprising multiple defined phase change material layers which comprise sidewalls having a stair profile.
Lee as modified by Goux does not explicitly describe a width of a diffusion barrier layer or a plurality of diffusion barrier layers disposed alternating with the plurality of phase change material layers.
Ding teaches a memory device comprising a phase change memory layer (102, see Fig. 1) wherein a plurality of diffusion barrier layers (1b) are implemented between a plurality of phase change material layers (1a) and a width of each diffusion barrier layer matches a width of a corresponding phase change material layer (shown Fig. 1). It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to ensure a width along a horizontal direction of each diffusion barrier layer is at least the same as a width of an adjoining phase change material layer to ensure diffusion between each of the phase change material layers is effectively inhibited. Furthermore, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a plurality of diffusion barrier layers between multiple phase change material layers as this would reduce power consumption while inhibiting element diffusion during the repeated phase transition process, thus improving stability of the memory layer.
More specifically Lee as modified by Goux and Ding would teach the variable resistance layer has a stepped profile and comprises a plurality of phase change material layers and a plurality of diffusion barrier layers stacked alternately in a vertical direction,
wherein the width of each of the phase change material layers in the first horizontal direction is dependent on a location of the respective phase change material layer in the stack and a width of each of the diffusion barrier layers in the first horizontal direction is dependent on a position of the respective diffusion barrier layer in the vertical direction to form the stepped profile of the variable resistance layer,
wherein the stepped profile has a minimum width in the first horizontal direction at a center of the stack in the vertical direction and a maximum width in the first horizontal direction at opposing ends of the stack in the vertical direction,
wherein each phase change material layer is formed of the same material;
wherein adjacent phase change material layers formed of the same material are separated by a respective diffusion barrier layer, and
wherein the phase change material layer at the center of the stack in the vertical direction has a width in the first horizontal direction that is less that the minimum width in the horizontal direction of the diffusion barrier layers.
Regarding Claim 12, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 11, further comprising:
a first electrode layer (136, an upper electrode) on the variable resistance layer; and
a second electrode layer (134, an intermediate electrode, see [0045]) under the variable resistance layer, the variable resistance layer being between the first electrode layer and the second electrode layer, and the first electrode layer contacting a first phase change material layer of the stack of phase change material layers and the second electrode layer contacting a second phase change material layer (shown Fig. 14A) of the stack of phase change material layers.
Regarding Claim 13, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 12, wherein:
in accordance with a difference among the areas of the phase change material layers (see Fig. 14A, wherein a cross-sectional area decreases toward a center of the variable resistance layer).
Lee describes joule heating generated by a voltage applied to both ends of the variable resistance memory layer which causes a phase change of the material used in the variable resistance memory layer, such that data is stored therein (see [0047]). Furthermore, Lee teaches the variable resistance layer comprising multiple phase change material layers (see [0050]).
Goux further teaches a similar phase change memory cell (shown Fig. 6) wherein multiple bits may be stored in a plurality of phase change material layers (layers 50, 52, 54, 56 and 58), which makes up a variable resistance layer due to a central first constriction, second constriction and third constriction (see described in [0060]). Furthermore, by applying a voltage to electrodes (4 and 6) a difference among areas of the phase change material layers causes a phase change to occur from the center (50, at a central first constriction, see also [0058-0060]) and toward the electrodes (see described in [0059]) in the vertical direction and the phase change memory cell is a multi-level cell (i.e., capable of storing multiple bits, see also [0006-0007]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the defined constriction regions of phase change material layers within the variable resistance layer of Lee as this would allow each memory cell to store more than one bit thus increasing data storage (see [0007]).
Specifically, this modification would teach a phase change occurring at a first voltage applied to the first electrode layer and the second electrode layer for the first phase change material layer and the second phase change material layer and at a second voltage for a third phase change material layer located at the center of the variable resistance material layer and that the memory cell is a multilevel cell.
Regarding Claim 14, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 11, wherein each of the diffusion barrier layers has an area equal to an area of an adjacent one of the phase change material layers (see Fig. 14A). Examiner notes that the variable resistance layer shown does not clearly define a first phase change material layer, a diffusion barrier layer, and a second phase change material layer, however this is the sequence described in paragraph [0050]. Given the profile of the variable resistance layer shown in Fig. 14A, it is understood that at least one surface of the diffusion barrier layer will have a cross-sectional area equal to an adjacent surface of one of the phase change material layers at the material interface.
Regarding Claim 15, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 11, wherein the variable resistance layer has a cross-sectional shape of an hourglass (shown Fig. 14A), but does not explicitly teach having sidewalls with a stair profile.
Goux teaches a similar phase change memory cell (shown Fig. 6) wherein a plurality of phase change material layers (layers 50, 52, 54, 56 and 58) are clearly defined in a step structure, which makes up a variable resistance layer due to a central first constriction, second constriction and third constriction (see described in [0060]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the defined constriction regions of phase change material layers within the variable resistance layer of Lee as this would allow each memory cell to store more than one bit thus increasing data storage (see [0007]).
As applied to Lee, this modification would teach the variable resistance layer comprising multiple defined phase change material layers which comprise sidewalls having a stair profile.
Regarding Claim 16, Lee teaches a variable resistance memory device (1000, shown Fig. 14A), comprising:
a substrate (110);
first conductive lines (120-1) extending on the substrate in a first horizontal direction (shown, see also perspective of Fig. 3A);
second conductive lines (180-1) extending on the first conductive lines in a second horizontal direction perpendicular to the first horizontal direction (shown);
third conductive lines (120-2) extending on the second conductive lines in the first horizontal direction;
first memory cells (ML-1) at intersections between the first conductive lines and the second conductive lines; and
second memory cells (ML-2) at intersections between the second conductive lines and the third conductive lines,
wherein each of the first memory cells and the second memory cells includes a selection element layer (140), an intermediate electrode layer (134), and a variable resistance layer (150) that are stacked in the stated order (shown Fig. 14A), and
wherein the variable resistance layer includes a stack of alternating phase change material layers (see [0050] and at least one diffusion barrier layer (described in [0050]), the variable resistance layer having a concave center (shown Fig. 14A).
Lee further describes the variable resistance layer comprising multiple phase change material layers and a diffusion barrier layer therebetween, wherein a horizontal width is decreased toward a center of the variable resistance layer. Paragraph [0051] further states that the variable resistance layer “may include various materials having resistance change characteristics” which suggests that more than two phase change material layers may be implemented, in which case a diffusion barrier layer would be necessary between each alternately stacked phase change material layer to prevent diffusion of materials between the layers (as described in [0050]).
Goux teaches a similar phase change memory cell (shown Fig. 6) wherein a plurality of phase change material layers (layers 50, 52, 54, 56 and 58) are clearly defined in a step structure, which makes up a variable resistance layer due to a central first constriction, second constriction and third constriction (see described in [0060]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the defined constriction regions of phase change material layers within the variable resistance layer of Lee as this would allow each memory cell to store more than one bit thus increasing data storage (see [0007]).
As applied to Lee, this modification would teach the variable resistance layer comprising multiple defined phase change material layers which comprise sidewalls having a stair profile.
Lee as modified by Goux does not explicitly describe a width of a diffusion barrier layer or a plurality of diffusion barrier layers disposed alternating with the plurality of phase change material layers.
Ding teaches a memory device comprising a phase change memory layer (102, see Fig. 1) wherein a plurality of diffusion barrier layers (1b) are implemented between a plurality of phase change material layers (1a) and a width of each diffusion barrier layer matches a width of a corresponding phase change material layer (shown Fig. 1). It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to ensure a width along a horizontal direction of each diffusion barrier layer is at least the same as a width of an adjoining phase change material layer to ensure diffusion between each of the phase change material layers is effectively inhibited. Furthermore, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a plurality of diffusion barrier layers between multiple phase change material layers as this would reduce power consumption while inhibiting element diffusion during the repeated phase transition process, thus improving stability of the memory layer.
More specifically Lee as modified by Goux and Ding would teach the variable resistance layer has a stepped profile and comprises a plurality of phase change material layers and a plurality of diffusion barrier layers stacked alternately in a vertical direction,
wherein the width of each of the phase change material layers in the first horizontal direction is dependent on a location of the respective phase change material layer in the stack and a width of each of the diffusion barrier layers in the first horizontal direction is dependent on a position of the respective diffusion barrier layer in the vertical direction to form the stepped profile of the variable resistance layer,
wherein the stepped profile has a minimum width in the first horizontal direction at a center of the stack in the vertical direction and a maximum width in the first horizontal direction at opposing ends of the stack in the vertical direction,
wherein each phase change material layer is formed of the same material;
wherein adjacent phase change material layers formed of the same material are separated by a respective diffusion barrier layer, and
wherein the phase change material layer at the center of the stack in the vertical direction has a width in the first horizontal direction that is less that the minimum width in the horizontal direction of the diffusion barrier layers.
Regarding Claim 17, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 16, wherein the phase change material layers include at least one of Sb2Te3 and Bi2Te3 (see [0050] describing at least an Sb-Te layer, which is known in the art as antimony telluride having the chemical formula Sb2Te3). As modified by Ding, at least one of TiTe2, NiTe2, MoTe2, and ZrTe2 are implemented as a material of the diffusion barrier layers.
Regarding Claim 18, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 16, wherein a first voltage (see described in [0032], drawn to an earlier embodiment of Goux wherein a higher voltage is applied to initiate a phase change of the outermost phase change material layers, see further [0031-0033] and Fig. 1) distributed to an uppermost (58, as modified by Goux) and a lowermost (56, as modified by Goux) of the phase change material layers is greater than a second voltage distributed to remaining ones of the phase change material layers (described in Goux: [0031-0033]).
Regarding Claim 19, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 18, wherein:
a phase change occurs in at least some of the phase change material layers in accordance with a difference between the first and second voltages, and the first memory cells and the second memory cells are multi-level cells (see as modified by Goux: [0007] and [0031-0033]).
Regarding Claim 20, Lee as modified by Goux and Ding teaches the variable resistance memory device as claimed in claim 16, wherein the selection element layer includes an ovonic threshold switching (OTS) material (see Lee: [0046]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893