DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Amended Claim 11 recites the limitation " the fifth port " in line 14. There is insufficient antecedent basis for this limitation in the claim. Claims 12-20 depend from Claim 11 and rejected due to dependency to a rejected claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kube (US 2018/0097390) in view of Tzinker et al. (US 2013/0140896).
Regarding Claim 1, Kube discloses a fault protection apparatus, applied to a system based on a common direct current bus (Figures 1-7), the fault protection apparatus comprising:
a first diode (comprising DL, Figures 1, 2a, 2b);
a first switch component (comprising TE, Figures 1, 2a, 2b);
a control unit (comprising 11, Figures 1, 4);
a first port, wherein the first port is configured to be connected to one of a plurality of connections on a positive common direct current bus of the common direct current bus (a first port configured to be connected to one of a plurality of connections on DC bus coupled to positive terminal of inverter 4/load 5, Figure 1);
a second port, wherein the second port is configured to be connected to one of a plurality of connections on a negative common direct current bus of the common direct current bus (a second port configured to be connected to one of a plurality of connections on DC bus coupled to negative terminal of inverter 4/load 5, Figure 1);
a third port, wherein the third port is configured to be connected to a positive local bus of a branch on which the fault protection apparatus is located (a third port configured to be connected to DC bus coupled to positive terminal of battery 2, 3, Figure 1);
a fourth port, wherein the fourth port is configured to be connected to a negative local bus of the branch on which the fault protection apparatus is located (a fourth port configured to be connected to DC bus coupled to negative terminal of battery 2, 3, Figure 1); and
a fifth port, wherein one side of the fifth port is configured to be connected to a control terminal of the first switch component and the other side of the fifth port is configured to be connected to the control unit (a fifth port connected to the gate of TE and to the control unit 11, Figure 1);
the first diode and the first switch component are configured to be connected to a power system through the first port, the second port, the third port, and the fourth port (DL, TE configured to be connected to a battery 2, 3 and inverter 4/load 5, Figure 1), and the control unit is configured to send a drive signal to control the first switch component (Figures 1, 4, Paragraph 32), wherein the control unit is configured to, wherein when the current exceeds a normal range, the control unit is configured to stop sending the drive signal to the fifth port, and when the current is within the normal range, the control unit is configured to send the drive signal to the fifth port (Figures 1, 4, Paragraph 32, “……The transistors TE and the relay 8 are actuated by the control unit 11…”, Paragraph 33, “…the transistors TE are blocked since, in the inverse operation, they have a higher resistance than the diodes DL …the current flow can only be actively switched by the transistors TE in the discharging direction); and
wherein the first diode is configured so that when a voltage between the third port and the fourth port is lower than a voltage between the first port and the second port, the first diode is configured to be forward conducted (Figures 1, 2a, 2b, Paragraph 33, “….In the charging direction, the current ILAD flows into the battery 2. For this purpose, the transistors TE are blocked since, in the inverse operation, they have a higher resistance than the diodes DL.. solved by the transistors TE since they can switch within the μs range. Therefore, in the case of a short circuit, the current can be switched off via the transistors TE before the current carrying capacity limit of the relay 8 is reached…”);
when a voltage between the third port and the fourth port is higher than a voltage between the first port and the second port, and the fifth port is configured to receive the drive signal and the first switch component is configured to be forward conducted (Figures 1, 2a, 2b, Paragraph 33, “…when the transistors TE are in the discharging direction, that is to say, when current IELAD is flowing out of the battery 2, they are actuated so as to be in the conductive state. Since the diodes DL are polarized in the blocking direction, the current IELAD flows exclusively via the transistors TE…”); and
when a voltage between the third port and the fourth port is higher than a voltage between the first port and the second port, and the fifth port does not receive the drive signal, the first diode is configured to be reversely cut off and the first switch component is configured to be forward cut off wherein the fault protection apparatus is configured to implement bidirectional electric energy flow between the branch the local bus of the branch and the common direct current bus (when voltage between the third port and the fourth port is higher than a voltage between the first port and the second port diode DL is reverse biased/cutoff and TE is cutoff/switched off when not activated by the control signal at the gate/fifth port, Figure 1);
wherein the fault protection apparatus is configured to implement bidirectional electric energy flow between the branch the local bus of the branch and the common direct current bus (Figures 2a, 2b shows bidirectional current flow, Figure 2a shows forward current path from battery and Figure 2b shows reverse current flow to battery, Paragraph 33),
wherein the common direct current bus is configured to connect a plurality of fault protection apparatus, a plurality of direct current sources, and an inverter unit (common direct current bus connecting plurality of DL, TE, plurality of 3 and inverter unit in 4, Figures 1, 2a, 2b) and wherein a first capacitor is configured to be connected in parallel between the first port and the second port to suppress a surge current of the fault protection apparatus (comprising Czk connected across the first and second terminals suppress surge currents across the terminals/function as a smoothing capacitor, Figure 1).
Regarding the recited “photovoltaic” system in the preamble, it is noted that it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987), and furthermore it has been held that a preamble is denied the effect of a limitation where the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Kube does not specifically disclose the control unit being configured to detect a current in a circuit, additional inverter units to have plurality of inverter units, and a second capacitor configured to be connected in parallel between the third port and the fourth port to reduce inrush current of the fault protection apparatus during power-on.
Tzinker discloses power converter (200, Figure 2) comprising a transistor (205, Figure 2) coupled to a load (212, Figure 2) via a first port and a second port and an a source (201, Figure 2) via a third port and a fourth port, a control circuit (206, Figure 2) configured to detect a current in the circuit (comprising 209, 212, 222 with output to 206, Figure 2, Paragraph 89), a first capacitor is configured to be connected in parallel between the first port and the second port to suppress a surge current (comprising 210, Figure 2) and a second capacitor is configured to be connected in parallel between the third port and the fourth port to reduce an inrush current during power-on (comprising 204, Figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the fault protection apparatus of Kube, a current detecting circuit, and a second capacitor as taught by Tzinker, to suppress transients between the third and fourth ports (input ports) to provide stable voltage/signal between the input ports also, similarly to the output ports, to increase the accuracy and the reliability of current detected and switch control, and to provide additional inverter unit to have plurality of first inverter units such that plurality of load devices can be powered via dedicated inverter units.
Regarding Claim 2, combination of Kube and Tzinker discloses the fault protection apparatus according to Claim 1, wherein the first diode further comprises: a plurality of diodes configured to be connected in parallel (a first DL and a second DL connected in parallel, Figures 1, 2a, 2b); and the first switch component further comprises: a plurality of switch components configured to be connected in parallel (a first TE and a second TE connected in parallel, Figures 1, 2a, 2b).
Regarding Claim 3, combination of Kube and Tzinker discloses the fault protection apparatus according to Claim 1, wherein the first switch component is either an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET) (IGBTs TE, Figures 1, 2a, 2b, IGBTs, TE and MOSFETs, TE, Figure 7).
Regarding Claim 4, combination of Kube and Tzinker discloses the fault protection apparatus according to Claim 3, wherein when the first switch component is the MOSFET, a body diode in the MOSFET is the first diode or a body diode is a diode in the first diode (TE, MOSFETs connected in parallel, Figure 7, Paragraph 33, “…if the transistors are configured as MOSFETs, intrinsic diodes (also known as body diodes) of the transistors TE can be used”).
Regarding Claim 5, combination of Kube and Tzinker discloses the fault protection apparatus according to Claim 3, wherein an anode of the first diode is configured to be connected to the first port, a cathode of the first diode is configured to be connected to the third port (anode of DL connected to the first port and cathode of DL connected to the third port, Figure 1), an emitter of the IGBT or a source of the MOSFET is configured to be connected to the first port, a collector of the IGBT or a drain of the MOSFET is configured to be connected to the third port (emitter of TE connected to the first port and collector of TE connected to the third port, Figure 1), and the second port is configured to be connected to the fourth port (second port is configured to be connected to the fourth port via 8, Figure 1); or
a cathode of the first diode is configured to be connected to the second port, an anode of the first diode is configured to be connected to the fourth port, a collector of the IGBT or a drain of the MOSFET is configured to be connected to the second port, an emitter of the IGBT or a source of the MOSFET is configured to be connected to the fourth port (Figure 1 shows TE, DL connection between the first port and third port, and 8 in Figure 1 replaced by TE, DL for the corresponding current directions, have the cathode of DL connected to the second port and anode of DL connected to the fourth port, collector of TE connected to the second port, emitter of TE connected to the fourth port, Paragraph 32, “…..The essential difference from the embodiment of FIG. 4 is that the relay 8 was replaced by a parallel connection of several transistors TE…”), and the first port is configured to be connected to the third port (first port is configured to connected to the third port via TE, DL, Figure 1).
Regarding Claim 7, Kube discloses a fault protection apparatus, applied to system based on a common direct current bus(Figures 1-7), the fault protection apparatus comprising:
a second diode (comprising DL, Figures 1, 2a, 2b),
a sixth port, wherein the sixth port is configured to be connected to one of a plurality of connections on a positive common direct current bus of the common direct current bus (a sixth port configured to be connected to one of a plurality of connections on DC bus coupled to positive terminal of inverter 4/load 5, Figure 1);
a seventh port, wherein the seventh port is configured to be connected to one of a plurality of connections on a negative common direct current bus of the common direct current bus (a seventh port configured to be connected to one of a plurality of connections on DC bus coupled to negative terminal of inverter 4/load 5, Figure 1);
an eighth port, wherein the eighth port is configured to be connected to a positive local bus of a branch on which the fault protection apparatus is located (an eighth port configured to be connected to DC bus coupled to positive terminal of battery 2, 3, Figure 1); and
a ninth port, wherein the ninth port is configured to be connected to a negative local bus of the branch on which the fault protection apparatus is located (a ninth port configured to be connected to DC bus coupled to negative terminal of battery 2, 3, Figure 1), and the second diode is configured to be connected to a power system through the sixth port, the seventh port, the eighth port, and the ninth port (DL configured to be connected to a battery 2, 3 and inverter 4/load 5 through the sixth, seventh, eighth and the ninth ports, Figure 1); and
wherein the second diode is configured so that when a voltage between the eighth port and the ninth port is lower than a voltage between the sixth port and the seventh port, the second diode is configured to be forward conducted (Figures 1, 2a, 2b, Paragraph 33, “.In the charging direction, the current ILAD flows into the battery 2. For this purpose, the transistors TE are blocked since, in the inverse operation, they have a higher resistance than the diodes DL..”); and
when a voltage between the eighth port and the ninth port is higher than a voltage between the sixth port and the seventh port, the second diode is configured to be reversely cut off (Figures 1, 2a, 2b, Paragraph 33, “…when the transistors TE are in the discharging direction, that is to say, when current IELAD is flowing out of the battery 2, they are actuated so as to be in the conductive state. Since the diodes DL are polarized in the blocking direction, the current IELAD flows exclusively via the transistors TE…”),
wherein the fault protection apparatus is configured to implement bidirectional electric energy flow between the branch the local bus of the branch and the common direct current bus (Figures 2a, 2b shows bidirectional current flow, Figure 2a shows forward current path from battery and Figure 2b shows reverse current flow to battery, Paragraph 33);
wherein the common direct current bus is configured to connect a plurality of fault protection apparatus, a plurality of direct current sources, and an inverter unit (common direct current bus connecting plurality of DL, TE, plurality of 3 and inverter unit in 4, Figures 1, 2a, 2b) and wherein a third capacitor is configured to be connected in parallel between the sixth port and the seventh port to suppress a surge current of the fault protection apparatus (comprising Czk, Figure 1).
Regarding the recited “photovoltaic” system in the preamble, it is noted that it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987), and furthermore it has been held that a preamble is denied the effect of a limitation where the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Kube does not specifically disclose additional inverter units to have plurality of inverter units and a fourth capacitor is configured to be connected in parallel between the eighth port and the nineth port to reduce inrush current of the fault protection apparatus during power-on.
Tzinker discloses power converter (200, Figure 2) comprising a transistor (205, Figure 2) coupled to a load (212, Figure 2) via a first port and a second port and an a source (201, Figure 2) via a third port and a fourth port, a control circuit (206, Figure 2) configured to detect a current in the circuit (comprising 209, 212, 222 with output to 206, Figure 2, Paragraph 89), a first capacitor is configured to be connected in parallel between the first port and the second port to suppress a surge current (comprising 210, Figure 2) and a second capacitor is configured to be connected in parallel between the third port and the fourth port to reduce an inrush current during power-on (comprising 204, Figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the fault protection apparatus of Kube, and an additional capacitor as taught by Tzinker, to suppress transients between the eighth and nineth ports (input ports) to provide stable voltage/signal between the input ports also, similarly to the output ports to increase the accuracy and the reliability of current detected and switch control, and additional inverter unit to have plurality of first inverter units such that plurality of load devices can be powered via dedicated inverter units.
Regarding Claim 8, combination of Kube and Tzinker discloses the fault protection apparatus according to Claim 7, wherein the second diode further comprises: a plurality of diodes configured to be connected in parallel (a first DL and a second DL connected in parallel, Figures 1, 2a, 2b).
Regarding Claim 9, combination of Kube and Tzinker discloses the fault protection apparatus according to Claim 7, wherein an anode of the second diode is configured to be connected to the sixth port, a cathode of the second diode is configured to be connected to the eighth port, and the seventh port is configured to be connected to the ninth port (anode of DL connected to the sixth port and cathode of DL connected to the seventh port, Figure 1); or a cathode of the second diode is configured to be connected to the seventh port, an anode of the second diode is configured to be connected to the ninth port (Figure 1 shows TE, DL connection between the first port and third port, and 8 in Figure 1 replaced by TE, DL for the corresponding current directions, have the cathode of DL connected to the second port and anode of DL connected to the fourth port, collector of TE connected to the second port, emitter of TE connected to the fourth port, Paragraph 32, “…..The essential difference from the embodiment of FIG. 4 is that the relay 8 was replaced by a parallel connection of several transistors TE…”), and the sixth port is configured to be connected to the eighth port (sixth port is configured to connected to the eighth port via TE, DL, Figure 1).
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kanemaru et al. (US 2016/0181799) in view of Kube (US 2018/0097390), and Tzinker et al. (US 2013/0140896).
Regarding Claim 11, Kanemaru discloses a photovoltaic system (Figures 1-21), comprising:
a common direct current bus (20, Figures 1, 14, see also Figures 4, 6, 8, 10, 12, 12, 13 and 15-17, 19 used in the description for the details of the operation of Figures 1, 14),
a plurality of first fault protection apparatuses (comprising 2A, 3A, 100A, 2B, 3B, 100B, 2C, 3C, 100C, Figures 1, 14), wherein each first fault protection apparatus comprises a first diode (5, Figures 14-17, 19, Paragraph 51), a first switch component (2, Figures 1, 14), and a control unit (100, Figures 1, 14);
a plurality of first direct current source units (1A, 1B, 1C, Figures 1, 14), and
an first inverter unit (4, Figures 1, 14), wherein a branch on which each first direct current source unit or the first inverter unit is located is configured to be connected to the common direct current bus by using a respective first fault protection apparatus (1A, 1B, 1C connected to 20 by using a respective 2, 3, 5,100, Figure 14); and
when each first diode is configured to be forward conducted, the common direct current bus is configured to supply power to the branch (when 5 is forward conducted common direct current bus receives power from DC source and supply to inverter unit, Figure 14, Paragraphs 44-45, 51); and
when each control unit is configured to control each first switch component to be conducted, the branch is configured to supply energy to the common direct current bus (when the first switch 2 is closed/forward conducting, branch supply energy from the DC source 1 to the common direct current bus 20, Figure 14, Paragraph 51), wherein each control unit is configured to detect a current in a circuit (voltage-current sensor 3 sending output to 100, Figure 14); or
when each first diode is configured to be cut off, and each control unit is configured to control the first switch component to be forward cut off, the branch is configured to be disconnected from the common direct current bus (when the switch is reversely cutoff and switch is open, each branch is disconnected from the common direct current bus 20, Figure 14, Paragraph 51),
wherein the plurality of fault protection apparatus are configured to implement bidirectional electric energy flow (Paragraphs 44-45, 51).
Kanemaru does not specifically disclose additional inverter unit to have plurality of inverter units and does not specifically disclose the switch component being configured to be forward conducting and/or reversely cutoff and comprising limitations of a first to a fifth port and a capacitor configured as recited), and when the current exceeds a normal range, each control unit being configured to stop sending a drive signal to the fifth port, and when the current is within the normal range, each control unit is configured to send the drive signal to the fifth port.
Kube discloses a fault protection apparatus, applied to a system based on a common direct current bus (Figures 1-7), the fault protection apparatus comprising: a first diode (comprising DL, Figures 1, 2a, 2b), a first switch component (comprising TE, Figures 1, 2a, 2b), and a control unit (comprising 11, Figures 1, 4);
the first diode and the first switch component are configured to be connected to a power system through the first port, the second port, the third port, and the fourth port (DL, TE configured to be connected to a battery 2, 3 and inverter 4/load 5, Figure 1), and the control unit is configured to send a drive signal to a fifth port to control the first switch component (Figures 1, 4, Paragraph 32), wherein the control unit is configured to, wherein when the current exceeds a normal range, the control unit is configured to stop sending the drive signal to the fifth port, and when the current is within the normal range, the control unit is configured to send the drive signal to the fifth port (Figures 1, 4, Paragraph 32, “……The transistors TE and the relay 8 are actuated by the control unit 11…”, Paragraph 33, “…the transistors TE are blocked since, in the inverse operation, they have a higher resistance than the diodes DL …the current flow can only be actively switched by the transistors TE in the discharging direction); and
when a voltage between the third port and the fourth port is lower than a voltage between the first port and the second port, the first diode is configured to be forward conducted (Figures 1, 2a, 2b, Paragraph 33, “.In the charging direction, the current ILAD flows into the battery 2. For this purpose, the transistors TE are blocked since, in the inverse operation, they have a higher resistance than the diodes DL..”); when a voltage between the third port and the fourth port is higher than a voltage between the first port and the second port, and the fifth port is configured to receive the drive signal and the first switch component is configured to be forward conducted (Figures 1, 2a, 2b, Paragraph 33, “…when the transistors TE are in the discharging direction, that is to say, when current IELAD is flowing out of the battery 2, they are actuated so as to be in the conductive state. Since the diodes DL are polarized in the blocking direction, the current IELAD flows exclusively via the transistors TE…”); when a voltage between the third port and the fourth port is higher than a voltage between the first port and the second port, and the fifth port does not receive the drive signal, the first diode is configured to be reversely cut off and the first switch component is configured to be forward cut off (when voltage between the third port and the fourth port is higher than a voltage between the first port and the second port diode DL is reverse biased/cutoff and TE is cutoff/switched off when activated by the control signal at the gate/fifth port, Figure 1), wherein the fault protection apparatus is configured to implement bidirectional electric energy flow between the branch the local bus of the branch and the common direct current bus (Figures 2a, 2b shows bidirectional current flow, Figure 2a shows forward current path from battery and Figure 2b shows reverse current flow to battery, Paragraph 33);
wherein the fault protection apparatus further comprises:
the first port, wherein the first port is configured to be connected to the positive common direct current bus of the common direct current bus (a first port configured to be connected to one of a plurality of connections on DC bus coupled to positive terminal of inverter 4/load 5, Figure 1);
the second port, wherein the second port is configured to be connected to the negative common direct current bus of the common direct current bus (a second port configured to be connected to one of a plurality of connections on DC bus coupled to negative terminal of inverter 4/load 5, Figure 1);
the third port, wherein the third port is configured to be connected to a positive local bus of a branch on which the fault protection apparatus is located (a third port configured to be connected to DC bus coupled to positive terminal of battery 2, 3, Figure 1);
the fourth port, wherein the fourth port is configured to be connected to a negative local bus of the branch on which the fault protection apparatus is located (a fourth port configured to be connected to DC bus coupled to negative terminal of battery 2, 3, Figure 1); and
the fifth port, wherein one side of the fifth port is configured to be connected to a control terminal of the first switch component and the other side of the fifth port is configured to be connected to the control unit (a fifth port connected to the gate of TE and to the control unit 11, Figure 1); and
wherein a first capacitor is configured to be connected in parallel between the first port and the second port to a surge suppress current of the fault protection apparatus (comprising Czk, Figure 1).
Tzinker discloses power converter (200, Figure 2) comprising a transistor (205, Figure 2) coupled to a load (212, Figure 2) via a first port and a second port and an a source (201, Figure 2) via a third port and a fourth port, a control circuit (206, Figure 2) configured to detect a current in the circuit (comprising 209, 212, 222 with output to 206, Figure 2, Paragraph 89), a first capacitor is configured to be connected in parallel between the first port and the second port to suppress a surge current (comprising 210, Figure 2) and a second capacitor is configured to be connected in parallel between the third port and the fourth port to reduce an inrush current during power-on (comprising 204, Figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the photovoltaic system of Kanemaru, additional inverter unit to have plurality of first inverter units such that plurality of load devices can be powered via dedicated inverter units, and provide the switch component of Kanemaru, having a switch and diode configuration and port connections and a capacitor connection as taught by Kube such that current flow can be controlled in both forward and reverse directions (configured for bidirectional current flow, including ports configured for forward and reverse current flow and switch control) during normal operation and during fault conditions and to provide an additional capacitor in the combination as taught by Tzinker, to suppress transients between the third and fourth ports (input ports) to provide stable voltage/signal between the input ports also, similarly to the output ports, to increase the accuracy and the reliability of current detected and switch control.
Regarding Claim 12, combination of Kanemaru, Kube and Tzinker discloses the photovoltaic system according to Claim 11, wherein each first diode further comprises: a plurality of diodes, configured to be connected in parallel (a first DL and a second DL connected in parallel, Figures 1, 2a, 2b of Kube in the combination); and each first switch component further comprises: a plurality of switch configured to be connected in parallel components (Kube, a first TE and a second TE connected in parallel, Figures 1, 2a, 2b of Kube in the combination).
Regarding Claim 13, combination of Kanemaru, Kube and Tzinker discloses the photovoltaic system according to Claim 11, wherein each first switch component is either an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET) (Kube, IGBTs TE, Figures 1, 2a, 2b, IGBTs, TE and MOSFETs, TE, Figure 7).
Regarding Claim 14, combination of Kanemaru, Kube and Tzinker discloses the photovoltaic system according to Claim 13, wherein when each first switch component is the MOSFET, a body diode in the MOSFET is the first diode, or a body diode is a diode in the first diode (Kube, TE, MOSFETs connected in parallel, Figure 7, Paragraph 33, “…if the transistors are configured as MOSFETs, intrinsic diodes (also known as body diodes) of the transistors TE can be used”).
Regarding Claim 15, combination of Kanemaru, Kube and Tzinker discloses the photovoltaic system according to Claim 11, wherein each first fault protection apparatus is configured to be connected between a positive local bus of the branch on which each first direct current source unit or each first inverter unit is located and a positive common direct current bus of the common direct current bus (2,3,5,100 including elements in the positive local bus, Figure 14); or each first fault protection apparatus is configured to be connected between a negative local bus of the branch on which the first direct current source unit or the first inverter unit is located and a negative common direct current bus of the common direct current bus (2,3,5,100 including elements in the negative local bus, Figure 14).
Claim 16 basically recites each fault protection apparatus of Claim 15 including the limitations of Claim 3 and Claim 5, and Kube in the combination discloses the limitations as discussed in the rejection of Claims 3, 5 above.
Claims 17-19 basically recite the photovoltaic system according to Claim 11, further comprising second set of elements as recited in Claim 11, 12, 15 respectively, except for excluding the switch component and control unit in the fault protection apparatus, and corresponding limitations including the excluded limitations.
Combination of Kanemaru, Kube and Tzinker does not specifically disclose the additional/second set of limitations recited in Claims 17-18. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the combination partly duplicate elements (simplified additional set of same limitations), to meet the requirements of the different types of loads.
Claim 20 basically recite the photovoltaic system according to Claim 19, wherein each second fault protection apparatus further comprises corresponding limitations of Claim 7, lines 6-16 and Claim 9 combined. Combination of Kanemaru, Kube and Tzinker discloses the limitation of Claim 7, lines 6-16 and Claim 9 as discussed above.
Response to Arguments
Applicant's arguments filed on 5/13/2026 have been fully considered but they are not persuasive and/or rendered moot in view of new grounds of rejection necessitated by amendments.
Regarding Applicant’s arguments, on Page 14 of the Remarks toward capacitor Czk of Kube, examiner respectfully notes that capacitor Czk being connected in parallel between the first port and the second port as claimed and function as a smoothing capacitor to suppresses any surge/transients appears across the terminals.
The Applicant argues, on Pages 13-15 of the Remarks that Kube does not teach a control unit that is configured to detect a current in a circuit and conditionally send or stop sending a drive signal based on whether the current is within or exceeds a normal range.
In response, examiner respectfully notes that Kube discloses conditionally send or stop sending a drive signal based on whether the current is within or exceeds a normal range in Paragraph 33, “….In the charging direction, the current ILAD flows into the battery 2. For this purpose, the transistors TE are blocked since, in the inverse operation, they have a higher resistance than the diodes DL.. solved by the transistors TE since they can switch within the μs range. Therefore, in the case of a short circuit, the current can be switched off via the transistors TE before the current carrying capacity limit of the relay 8 is reached…”.
Examiner respectfully agrees that Kube does not specifically disclose the control circuit being configured to detect a current in a circuit and the newly applied secondary reference Tzinker discloses a control configured to detect a current and to control a switch based on the detected current.
The Applicant argues, on Pages 13-15 of the Remarks that Kube does not disclose a second capacitor configured to reduce an inrush current of the fault protection apparatus during power-on.
In response, examiner respectfully notes that the newly applied secondary reference Tzinker discloses capacitors both between the input ports and the output ports of a switch to meet the argued upon limitations of a second capacitor.
Regarding Applicant’s Arguments, toward dependent Claims 2-5, 8-9 and 12-20, please see the response to arguments toward Claim 1 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kubouchi (US 9,893,606) discloses a fault protection apparatus, applied to a system based on a common direct current bus (comprising bidirectional protection switch apparatus 201 applied to three level chopper system, Figures 1-20), the fault protection apparatus comprising:
a first diode (comprising 303, 304, Figures 3-4); a first switch component (comprising 301, 302, Figures 3-4); a control unit (comprising 1b (1a, 1d), Figures 3-4);
a first port (comprising Po, Figure 3), wherein the first port is configured to be connected to a positive common direct current bus of the common direct current bus (Po configured to be connected to DC bus coupled to positive terminal of inverter 91/load 9, Figure 3);
a second port (comprising No, Figure 3), wherein the second port is configured to be connected to a negative common direct current bus of the common direct current bus (No configured to be connected to DC bus coupled to negative terminal of inverter 91/load 9, Figure 3);
a third port (comprising N1, Figure 3), wherein the third port is configured to be connected to a positive local bus of a branch on which the fault protection apparatus is located (N1 Po configured to be connected to DC bus coupled to positive terminal of DC source 8, Figure 3);
a fourth port (comprising N2, Figure 3), wherein the fourth port is configured to be connected to a negative local bus of the branch on which the fault protection apparatus is located (N2 configured to be connected to DC bus coupled to negative terminal of DC source 8, Figure 3); and a fifth port (comprising port coupled to gate/control terminal of 301, 302, Figure 3), wherein one side of the fifth port is configured to be connected to a control terminal of the first switch component and the other side of the fifth port is configured to be connected to the control unit (fifth port connected to the gate of 301, 302 and to the control unit 1b (1c, 1d), Figures 3-4, Column 10, lines 17-24);
the first diode and the first switch component are configured to be connected to a power system through the first port, the second port, the third port, and the fourth port (303, 304 and 301, 302 configured to be connected to the power system comprising DC source 8 and load 9, Figure 3), and the control unit is configured to send a drive signal to control the first switch component (Column 10, lines 17-24, Column 13, lines 9-11); and when a voltage between the third port and the fourth port is lower than a voltage between the first port and the second port, the first diode is configured to be forward conducted (Figure 3, Column 13, lines 53-60, “…the switch 101 is turned on while the switch 102 is turned off such that a capacitor 402 is charged. In this state, the IGBT 302 of the protection switch 201a becomes forward biased, and hence it is required that the gate of the IGBT 302 be turned on to allow a current to flow therein. On the other hand, the IGBT 301 becoming reversely biased may be turned off or on since a current flows through the diode 303”); or when a voltage between the third port and the fourth port is higher than a voltage between the first port and the second port, and the fifth port is configured to receive the drive signal and the first switch component is configured to be forward conducted (Figure 3, Column 13, lines 61-67, “…switch 101 is turned off while the switch 102 is turned on such that a capacitor 401 is charged. In this state, the IGBT 301 of the protection switch 201a becomes forward biased, and hence it is required that the gate of the IGBT 301 be turned on to allow a current to flow therein. On the other hand, the IGBT 302 becoming reversely biased may be turned off or on since a current flows through the diode 304”);
Morioka (US 2020/0366282) discloses a current flow control device in Figure 1 comprising plurality of switching units and diode circuits (10a, 10a, 10a, 10b comprising MOSFETs and diodes in parallel) connected in parallel between a power source and load (10a, 10a, 10a, 10b connected in parallel between power source 20 and load 30).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY M THOMAS whose telephone number is (571)272-6002. The examiner can normally be reached Mon-Fri 9:30 am - 5:30 pm.
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/LUCY M THOMAS/ Examiner, Art Unit 2838, 6/22/2026
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838
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