DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/10/2023 and 7/10/2024 have been considered by the examiner.
Drawings
The drawings received on 11/30/2022 have been accepted by the examiner.
Claim Rejections - 35 USC § 112
Claims 3, 10, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation drawn to the first area being independent from the second area renders the claims as indefinite because the term “independent” has not been properly defined. It is not clear what applicant means by the term. Does it mean non-overlapping, separate in address range, or having different characteristics? Further clarification is required. As written, the metes and bounds of the claims cannot be determined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Malladi et al. [US 2022/0358042]
Claim 1, Malladi et al. discloses an apparatus [Fig. 2A, 205] comprising: a host managed device memory, the host managed device memory shared between a first host system and a second host system [CXL memory 205 that supports many-to-one switching and connecting multiple root ports to one end point, par. 0045 and 0060]; and control circuitry [controller 137 or 230, par. 0047 and 0050], the control circuitry to allow direct memory access from the first host system and the second host system to the host managed device memory [controller facilitates RDMA requests between CXL memory devices on different servers and supports CXL.mem protocols for direct memory semantics, par. 0043 and 0047], to synchronize host initiated write requests to the same memory addresses in the host managed device memory received from the first host system and the second host system to provide memory coherency for the host managed device memory [handling the ordering of read and write operations to ensure they are synchronized even if they arrive out of order, par. 0005 and 0054; cache coherent controller, par. 0006 and scoreboard to determine and resolve ordering on the device side to maintain coherency, par. 0054].
Claim 2, Malladi et al. discloses an apparatus of claim 1, wherein the control circuitry to store disk cache blocks in the host managed device memory [enhanced switch can store data of different characteristics, par. 0044; device microarchitecture including nonvolatile memory and volatile memory, par. 0050; work stealing between DRAM and low latency SSDs, par. 0057].
Claim 3, Malladi et al. discloses an apparatus of claim 1, wherein the control circuitry to store write logs for the first host system in a first area of the host managed device memory and to store write logs for the second host system in a second area of the host managed device memory, the first area independent from the second area [par. 0045, 0054-0055 and 0058; teaches the use of isolated logical devices and separate per device queues within a staging area partitioning the memory into independent areas to store the transaction history for each specific host].
Claim 4, Malladi et al. discloses the apparatus of claim 1, wherein the control circuitry is a Field Programmable Gate Array [par. 0047-0048].
Claim 5, Malladi et al. discloses the apparatus of claim 1, wherein upon failure of the first host system, to allow the second host system to access memory addresses in the host managed memory written by the first host system [see par. 0045, 0061; supports dynamic off-lining/on-lining of resources and recognizing topology changes; allows the remaining hosts in the many-to-one configuration to map and access the memory regions previously used by the failed entity].
Claim 6, Malladi et al. discloses the apparatus of claim 1, wherein the control circuitry to communicate with the first host system and the second host system over a communications bus using a Compute Express Link (CXL).mem protocol [par. 0043] over a Express (PCIe) bus [see par. 0042, 0043, 0054].
Claim 7, Malladi et al. discloses the apparatus of claim 1, wherein the control circuitry to communicate with the first host system and the second host system over a communications bus using a Compute Express Link (CXL).cache protocol [par. 0004-0005] over a t Express (PCIe) bus [par. 0042-0043 and 0063].
Claims 8-14 are rejected using the same rationale as Claims 1-7.
Claims 15-21 are rejected using the same rationale as Claims 1-7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
MODY et al. [US 2020/0210351]; Image Processing Accelerator. See par. 0034.
Jung et al. [US 2025/0061077]; Memory Expander, Computing Systems, and Operating Method of the Host Device. See par. 0057-0064.
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/MIDYS ROJAS/Primary Examiner, Art Unit 2133
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