Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ueno et al. (US 20070003194 A1) hereafter referred to as Ueno in view of Rock et al. (US 20240003995 A1) hereafter referred to as Rock
In regard to claim 1 Ueno teaches [see Fig. 14a see paragraph 0119 “optical module mounted on the circuit board”] a semiconductor package, comprising:
a semiconductor die [see paragraph 0086 “In each of the described embodiments, the optical module 10 uses the light emitting element 13 as the optical semiconductor. However, it is possible to construct the optical module 10 with a light receiving element. In such case, a circuit portion including, for example, an amplifier circuit shall be used instead of the drive IC 14” , see “Further, though the optical semiconductor (light emitting element 13 or a light receiving element) and the circuit portion (drive IC 14 or the amplifier circuit) are provided in different positions of the lead frame 11, a construction, in which an optical semiconductor is mounted on the circuit portion, or a construction, in which the optical semiconductor and the circuit portion are provided integrally, may be used”] including an ambient light sensor, the ambient light sensor facing [see Fig. 14b, the 13 is facing horizontal direction] a horizontal direction;
first and second conductive terminals [12Ab, 12 Bb see paragraph 0103 “The leads 12Ba to 12Bd in the rear line are connected to terminals of the drive IC 14 through bonding wires 18a. The drive IC 14 and the light emitting element 13 are connected each other by a bonding wire 18b and the drive IC 14 and the lead frame 11 are connected each other by a bonding wire 18c”] wirebonded to the semiconductor die, each of the first and second conductive terminals [see in Figs. 14a, 14b, 14c see inside and outside “sealing members 15”] having first and second segments; and
a clear mold compound [see paragraph 0101 “a first sealing member 15 formed of transparent resin for sealing a mounting portion of the lead frame 11, on which the light emitting element 13 and the drive IC 14 are mounted”] covering the semiconductor die and portions [see in Figs. 14a, 14b, 14c ] of the first and second conductive terminals,
wherein the first segments of the first and second conductive terminals extend vertically [see in Figs. 14a, 14b, 14c] through the clear mold compound to an exterior of the clear mold compound, and
wherein the second segments [see in Figs. 14a, 14b, 14c that 12Ab and 12Bb come out of 15] of the first and second conductive terminals are positioned exterior to the clear mold compound,
extend horizontally [see in Figs. 14a, 14b, 14c that 12Ab and 12Bb come out of 15 and then there is a horizontal extension i.e. even though there is an angle, they extend horizontally and the resulting horizontal separation can be seen, see that 12Ab goes horizontally left, 12Bb goes horizontally right , see paragraph 0121 “This embodiment differs from the fourth embodiment in that the space between the leads 12A in the front line is expanded by bending the leads 12Ba to 12Bd in the rear line backward as shown in FIG. 14(b)” ] in opposing directions, and are adapted to be coupled [see “circuit board 20” in Fig. 14b] to a printed circuit board
but does not teach the new limitation that the “extend horizontally in opposing directions” is “terminating at an end portion of each of the first and second conductive terminals”.
However see that this is common in the art see paragraph 0009 “FIGS. 19(a) to 19(c) show a related art ZIP type optical module 200” “This optical module 200 is called as ZIP type optical module having a plurality of zigzag arranged leads”.
See Rock Figures 1-7, see in Fig. 1 see that the leads alternately face opposite directions for surface mount, see comparison of surface mount and through-hole mounting, see paragraph 0037 “The terminal ends 38b-46b of the elongated leads 38-46 are configured for electrical connection to a substrate, such as a printed circuit board (PCB) as shown in FIGS. 6, 6A and 7. Lead ends 38b-46b can be formed according to the type of mounting desired. For example, lead ends 38b-46b can be bent as shown in FIGS. 1-1B for surface mount attachment to a PCB. Alternatively, as shown in FIGS. 6 and 6A, lead ends 38b-46b can be straight for through-hole mounting to a PCB”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueno to include wherein the semiconductor package is a surface mount type package i.e. to modify Ueno to include limitation that the “extend horizontally in opposing directions” is “terminating at an end portion of each of the first and second conductive terminals”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that surface mount is known to give excellent connection to circuit board and to free the portions of the board below the surface to be used for interconnections and also to optimize spacing between leads by alternately facing opposite directions.
In regard to claim 2 Ueno and Rock as combined teaches further comprising third and fourth conductive terminals [see Ueno Fig. 14a see six leads are shown] coupled to the semiconductor die and having first and second segments [see Fig. 14a, Fig. 14b see portions inside and outside “first sealing member 15”], the first segment of the second conductive terminal between [see six terminals are shown and see combination Rock the outer lead portions are bent alternately in opposite directions, see that they can be numbered as 1 to 6] the first segments of the first and third conductive terminals, and the first segment of the third conductive terminal between the first segments of the second and fourth conductive terminals, the second segments of the first and third conductive terminals extending in a first horizontal direction [see combination Rock, see opposite directions], and the second segments of the second and fourth conductive terminals extending in a second horizontal direction.
In regard to claim 3 Ueno and Rock as combined teaches wherein [see Ueno Fig. 14b see Rock Fig. 1 see combination] the first and second horizontal directions oppose each other.
In regard to claim 4 Ueno and Rock as combined teaches [see Fig. 14a , see Fig. 14b] wherein the first and second conductive terminals extend through a same surface of the clear mold compound.
In regard to claim 5 Ueno and Rock as combined teaches wherein [see Ueno Fig. 14b see Rock Fig. 1 see combination] the semiconductor package is a surface mount type package.
Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ueno et al. (US 20070003194 A1) hereafter referred to as Ueno in view of Haimerl et al. (DE 102005025754 A1) hereafter referred to as Haimerl and further in view of Rock et al. (US 20240003995 A1) hereafter referred to as Rock
In regard to claim 6 Ueno teaches [see Fig. 14a see paragraph 0119 “optical module mounted on the circuit board”] a semiconductor package, comprising:
a semiconductor die [see paragraph 0086 “In each of the described embodiments, the optical module 10 uses the light emitting element 13 as the optical semiconductor. However, it is possible to construct the optical module 10 with a light receiving element. In such case, a circuit portion including, for example, an amplifier circuit shall be used instead of the drive IC 14” , see “Further, though the optical semiconductor (light emitting element 13 or a light receiving element) and the circuit portion (drive IC 14 or the amplifier circuit) are provided in different positions of the lead frame 11, a construction, in which an optical semiconductor is mounted on the circuit portion, or a construction, in which the optical semiconductor and the circuit portion are provided integrally, may be used”] having a device side [the Examiner’s position is that Ueno means that the device side is shown as having the bonding wires attached to it, and that there is nothing to suggest otherwise, however a 103 combination is also provided to clarify that this is not a novelty in the art] including an ambient light sensor, the ambient light sensor facing [see Fig. 14b, the 13 is facing horizontal direction] a first direction;
first and second conductive terminals, [12Ab, 12 Bb see paragraph 0103 “The leads 12Ba to 12Bd in the rear line are connected to terminals of the drive IC 14 through bonding wires 18a. The drive IC 14 and the light emitting element 13 are connected each other by a bonding wire 18b and the drive IC 14 and the lead frame 11 are connected each other by a bonding wire 18c”] each of the first and second conductive terminals [see in Figs. 14a, 14b, 14c see inside and outside “sealing members 15”] having first and second segments,
the first segments connected to the device side [see in Figs. 14a, 14b see the wires] of the semiconductor die, the first segments extending away from the semiconductor die in a second direction [see Fig. 14b, vertical] approximately perpendicular to the first direction,
the second segments extending in opposing [see in Figs. 14a, 14b, 14c that 12Ab and 12Bb come out of 15 and then there is a horizontal extension i.e. even though there is an angle, they extend horizontally and the resulting horizontal separation can be seen, see that 12Ab goes horizontally left, 12Bb goes horizontally right , see paragraph 0121 “This embodiment differs from the fourth embodiment in that the space between the leads 12A in the front line is expanded by bending the leads 12Ba to 12Bd in the rear line backward as shown in FIG. 14(b)” ] directions, each of the opposing directions approximately [they are approximately horizontal] perpendicular to the second direction, the second segments adapted to be coupled [see “circuit board 20” in Fig. 14b] to a printed circuit board; and
a clear mold compound [see paragraph 0101 “a first sealing member 15 formed of transparent resin for sealing a mounting portion of the lead frame 11, on which the light emitting element 13 and the drive IC 14 are mounted”] covering the semiconductor die and portions of the first segments
but does not state that the connected is soldered and that the “second segments extending in opposing directions” are “terminating at an end of each of the first and second conductive terminals”.
With regard to the “device side”, see Haimerl Fig. 1 see “semiconductor sensor component 1 has a sensor chip 3 with a back 7 and an active top 6 on, being on the active top 6 a sensor area 8th is arranged and in the edge region of the active top 6 contact surfaces 27 available. On the contact surfaces 27 the active top 6 of the semiconductor chip 3 are flip-chip contacts 9”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueno to include that the device side is theone shown as having the bonding wires attached to it.
The motivation is so that light can directly reach the device side for best response and that connections to the devices from the wire bonding can be easily made to get good electrical connection.
Ueno and Haimerl as combined does not state that the connected is soldered and that the “second segments extending in opposing directions” are “terminating at an end of each of the first and second conductive terminals”.
However solder is common in the art, see Haimerl Fig. 1 see method “flip-chip contacts ( 9 ) on the circuit structure ( 10 ) are fixed by means of soldering” “semiconductor sensor component 1 has a sensor chip 3 with a back 7 and an active top 6 on, being on the active top 6 a sensor area 8th is arranged and in the edge region of the active top 6 contact surfaces 27 available. On the contact surfaces 27 the active top 6 of the semiconductor chip 3 are flip-chip contacts 9 fixed over which the semiconductor chip 3 or the active top 6 of the semiconductor chip 3 with a circuit structure 10 made of flat conductors 15 communicates” “transparent rubber-elastic plastic compound 5 as a housing 4 of the semiconductor sensor component 1 on, with the inner flat conductor 17 and the entire sensor chip 3 with his back 7 , its edge sides 29 and 30 as well as with its active top 6 , the central sensor area 8th and the edge regions and the flip-chip contacts arranged thereon 9 in the transparent, rubber-elastic plastic compound 5 are embedded” “sensor area 8th that of the interior ladders 17 is thus able to detect both optical and mechanical waves and via the flip-chip contacts 9 and the inner flat conductors 17 as measuring signals on the outer flat conductor 16 transfer”.
See that Ueno Fig. 14(a) teaches different shapes for the leads 12 as desired to connect to the components 13, 14 and see above the optical semiconductor and the circuit portion are provided integrally.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueno to include that the connected is soldered .
The motivation is that direct soldered connections to lead frame are simple, are strong and are known to give excellect conduction for connecting components to leads in a package.
Ueno and Haimerl as combined does not teach that the “second segments extending in opposing directions” are “terminating at an end of each of the first and second conductive terminals”.
However see that this is common in the art see paragraph 0009 “FIGS. 19(a) to 19(c) show a related art ZIP type optical module 200” “This optical module 200 is called as ZIP type optical module having a plurality of zigzag arranged leads”.
See Rock Figures 1-7, see in Fig. 1 see that the leads alternately face opposite directions for surface mount, see comparison of surface mount and through-hole mounting, see paragraph 0037 “The terminal ends 38b-46b of the elongated leads 38-46 are configured for electrical connection to a substrate, such as a printed circuit board (PCB) as shown in FIGS. 6, 6A and 7. Lead ends 38b-46b can be formed according to the type of mounting desired. For example, lead ends 38b-46b can be bent as shown in FIGS. 1-1B for surface mount attachment to a PCB. Alternatively, as shown in FIGS. 6 and 6A, lead ends 38b-46b can be straight for through-hole mounting to a PCB”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueno to include wherein the semiconductor package is a surface mount type package i.e. to modify Ueno to include limitation that the “second segments extending in opposing directions” are “terminating at an end of each of the first and second conductive terminals”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that surface mount is known to give excellent connection to circuit board and to free the portions of the board below the surface to be used for interconnections and also to optimize spacing between leads by alternately facing opposite directions.
In regard to claim 7 Ueno, Haimerl and Rock as combined teaches further comprising third and fourth conductive terminals [see Ueno Fig. 14a see six leads are shown] coupled to the semiconductor die and having first and second segments [see Fig. 14a, Fig. 14b see portions inside and outside “first sealing member 15”], the first segment of the second conductive terminal between [see six terminals are shown and see combination Rock the outer lead portions are bent alternately in opposite directions, see that they can be numbered as 1 to 6] the first segments of the first and third conductive terminals, and the first segment of the third conductive terminal between the first segments of the second and fourth conductive terminals, the second segments of the first and third conductive terminals extending in a first horizontal direction [see combination Rock, see opposite directions], and the second segments of the second and fourth conductive terminals extending in a second horizontal direction.
In regard to claim 8 Ueno, Haimerl and Rock as combined teaches wherein [see Ueno Fig. 14b see Rock Fig. 1 see combination] the first and second horizontal directions oppose each other.
In regard to claim 9 Ueno, Haimerl and Rock as combined teaches wherein the first and second conductive terminals extend through a same [see Ueno Fig. 14a, Fig. 14b ] surface of the clear mold compound.
In regard to claim 10 Ueno, Haimerl and Rock as combined teaches wherein [see Ueno Fig. 14b see Rock Fig. 1 see combination] the semiconductor package is a surface mount type package.
Claim(s) 11-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ueno et al. (US 20070003194 A1) hereafter referred to as Ueno in view of Rock et al. (US 20240003995 A1) hereafter referred to as Rock
In regard to claim 11 Ueno teaches [see Fig. 14a see paragraph 0119 “optical module mounted on the circuit board”] a method for manufacturing a semiconductor die [see paragraph 0086 “In each of the described embodiments, the optical module 10 uses the light emitting element 13 as the optical semiconductor. However, it is possible to construct the optical module 10 with a light receiving element. In such case, a circuit portion including, for example, an amplifier circuit shall be used instead of the drive IC 14” , see “Further, though the optical semiconductor (light emitting element 13 or a light receiving element) and the circuit portion (drive IC 14 or the amplifier circuit) are provided in different positions of the lead frame 11, a construction, in which an optical semiconductor is mounted on the circuit portion, or a construction, in which the optical semiconductor and the circuit portion are provided integrally, may be used”], comprising:
providing a lead frame [“lead frame 11”] having a die pad [see Fig. 14a “a light emitting element 13 as an optical semiconductor mounted on the lead frame 11, a drive IC 14 as a circuit portion mounted on the lead frame 11”, see die description above] and an array [see Fig. 14a see six leads are shown] of conductive terminals, each of the conductive terminals in the array of conductive terminals having [see Fig. 14a, Fig. 14b see inside and outside “first sealing member 15”] first and second segments;
coupling a semiconductor die [see above “Further, though the optical semiconductor (light emitting element 13 or a light receiving element) and the circuit portion (drive IC 14 or the amplifier circuit) are provided in different positions of the lead frame 11, a construction, in which an optical semiconductor is mounted on the circuit portion, or a construction, in which the optical semiconductor and the circuit portion are provided integrally, may be used”] to the die pad and to the array of conductive terminals, the semiconductor die having an ambient light sensor facing [see facing horizontally to the left] a first direction;
covering the semiconductor die and portions of the first segments of the conductive terminals in the array of conductive terminals with [see paragraph 0101 “a first sealing member 15 formed of transparent resin for sealing a mounting portion of the lead frame 11, on which the light emitting element 13 and the drive IC 14 are mounted”] a clear mold compound;
bending the second segments of a first set of conductive terminals in the array of conductive terminals in a [see in Figs. 14a, 14b, 14c that 12Ab and 12Bb come out of 15 and then there is a horizontal extension i.e. even though there is an angle, they extend horizontally and the resulting horizontal separation can be seen, see that 12Ab goes horizontally left, 12Bb goes horizontally right , see paragraph 0121 “This embodiment differs from the fourth embodiment in that the space between the leads 12A in the front line is expanded by bending the leads 12Ba to 12Bd in the rear line backward as shown in FIG. 14(b)”] second direction; and
bending the second segments of a second set of conductive terminals in the array of conductive terminals [see that 12Ab goes horizontally left, 12Bb goes horizontally right ] in the first direction,
but does not clearly state that the bending the second segments of a first set of conductive terminals in the array of conductive terminals in a second direction is “terminating at first ends of the first set of conductive terminals” and the bending the second segments of a second set of conductive terminals in the array of conductive terminals in the first direction is “terminating at second ends of the second set of conductive terminals” and that “the conductive terminals bent in the first direction interleaved with the conductive terminals bent in the second direction”.
However see that this is common in the art see paragraph 0009 “FIGS. 19(a) to 19(c) show a related art ZIP type optical module 200” “This optical module 200 is called as ZIP type optical module having a plurality of zigzag arranged leads”.
See Rock Figures 1-7, see in Fig. 1 see that the leads alternately face opposite directions for surface mount, see comparison of surface mount and through-hole mounting, see paragraph 0037 “The terminal ends 38b-46b of the elongated leads 38-46 are configured for electrical connection to a substrate, such as a printed circuit board (PCB) as shown in FIGS. 6, 6A and 7. Lead ends 38b-46b can be formed according to the type of mounting desired. For example, lead ends 38b-46b can be bent as shown in FIGS. 1-1B for surface mount attachment to a PCB. Alternatively, as shown in FIGS. 6 and 6A, lead ends 38b-46b can be straight for through-hole mounting to a PCB”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueno to include wherein the semiconductor package is a surface mount type package i.e. to modify Ueno to include limitation that the bending the second segments of a first set of conductive terminals in the array of conductive terminals in a second direction is “terminating at first ends of the first set of conductive terminals” and the bending the second segments of a second set of conductive terminals in the array of conductive terminals in the first direction is “terminating at second ends of the second set of conductive terminals” and that “the conductive terminals bent in the first direction interleaved with the conductive terminals bent in the second direction”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that surface mount is known to give excellent connection to circuit board and to free the portions of the board below the surface to be used for interconnections and also to optimize spacing between leads by alternately facing opposite directions.
In regard to claim 12 Ueno and Rock as combined teaches wherein the first and second sets of conductive terminals are interleaved [see combination the leads alternately face opposite directions] in the array of conductive terminals.
In regard to claim 13 Ueno and Rock as combined teaches [see Ueno Fig. 14b see Rock Fig. 1 see combination] wherein the first and second directions are opposing horizontal directions.
In regard to claim 14 Ueno and Rock as combined teaches [see Ueno Fig. 14b see Rock Fig. 1 see combination] wherein the first and second sets of conductive terminals extend through a same surface of the clear mold compound.
In regard to claim 15 Ueno and Rock as combined teaches [see Ueno Fig. 14b see Rock Fig. 1 see combination] wherein the semiconductor die is within a surface mount type semiconductor package.
In regard to claim 16 Ueno and Rock as combined teaches [see Ueno paragraph 0103 “The leads 12Ba to 12Bd in the rear line are connected to terminals of the drive IC 14 through bonding wires 18a. The drive IC 14 and the light emitting element 13 are connected each other by a bonding wire 18b and the drive IC 14 and the lead frame 11 are connected each other by a bonding wire 18c”] wherein coupling the semiconductor die to the array of conductive terminals comprises wirebonding the semiconductor die to the array of conductive terminals.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ueno and Rock as combined and further in view of Haimerl et al. (DE 102005025754 A1) hereafter referred to as Haimerl
In regard to claim 17 Ueno and Rock as combined does not specifically teach wherein coupling the semiconductor die to the array of conductive terminals comprises soldering the semiconductor die to the array of conductive terminals.
However solder is common in the art, see Haimerl Fig. 1 see method “flip-chip contacts ( 9 ) on the circuit structure ( 10 ) are fixed by means of soldering” “semiconductor sensor component 1 has a sensor chip 3 with a back 7 and an active top 6 on, being on the active top 6 a sensor area 8th is arranged and in the edge region of the active top 6 contact surfaces 27 available. On the contact surfaces 27 the active top 6 of the semiconductor chip 3 are flip-chip contacts 9 fixed over which the semiconductor chip 3 or the active top 6 of the semiconductor chip 3 with a circuit structure 10 made of flat conductors 15 communicates” “transparent rubber-elastic plastic compound 5 as a housing 4 of the semiconductor sensor component 1 on, with the inner flat conductor 17 and the entire sensor chip 3 with his back 7 , its edge sides 29 and 30 as well as with its active top 6 , the central sensor area 8th and the edge regions and the flip-chip contacts arranged thereon 9 in the transparent, rubber-elastic plastic compound 5 are embedded” “sensor area 8th that of the interior ladders 17 is thus able to detect both optical and mechanical waves and via the flip-chip contacts 9 and the inner flat conductors 17 as measuring signals on the outer flat conductor 16 transfer”.
See that Ueno Fig. 14(a) teaches different shapes for the leads 12 as desired to connect to the components 13, 14 and see above the optical semiconductor and the circuit portion are provided integrally.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueno to include wherein coupling the semiconductor die to the array of conductive terminals comprises soldering the semiconductor die to the array of conductive terminals.
The motivation is that direct soldered connections to lead frame are simple, are strong and are known to give excellect conduction for connecting components to leads in a package.
Response to Arguments
Applicant's arguments filed 1/30/2026 have been fully considered but they are not persuasive.
On page 1 the Applicant argues “Claim 1 as amended recites "wherein the second segments of the first and second conductive terminals are positioned exterior to the clear mold compound, extend horizontally in opposing directions terminating at an end portion of each of the first and second conductive terminals". Ueno fails to teach at least these limitations. For example, the end of the leads 12Ab and 12Bb do not extending horizontally, and instead are extending vertically down”.
The Examiner responds that this is taught by secondary reference Rock see Fig. 1, see combination.
On page 2 the Applicant argues “As the combination of references fails to teach all of the limitations of Claim 6, it is believed Claim 6 and Claims dependent thereon are allowable over Ueno and Motz. In addition, the Examiner admits that Ueno fails to teach the limitation "the first segments soldered to the device side of the semiconductor die" or Claim 6. The Examiner then relies on Motz to teach this limitation and alleges that it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueno to include that the connected is soldered "soldered connections for lead frame are simple and are known to give (sic) excellect conduction for connecting components to leads in a package" (page 8 of the Office Action). Applicant submits that there is no motivation for a person of ordinary skill in the art to modify Ueno because it not a simple way of interconnection to and from a die as the Examiner alleges. For example, if the leads 12a/b are to be connected to the die 14, it would mean bending the leads horizontally and rearranging them to be extended in a way so as to have all the four pins (Fig. 14(a)) to connect to multiple bond pads of the die 14 that are close to each other. Doing so, would increase complexity of manufacturing for one, and increases the cost of the device. Modifying Ueno would also mean bending the leads vertically to be able to connect to the top of the die 14. Bending a portion of the lead that is outside the mold compound 15 is easy and can be achieved during trim and form process, but bending the leads inside the mold compound before or after molding is technically impossible, and therefore, a person of ordinary skill in the art would not be motivated to modify Ueno with Motz. Otherwise, a special lead frame is required that is pre-bent and only the instant application teaches such a lead frame. Such a pre-bent lead frame would require copper posts underneath and only the instant application teaches such a post. Claim 6 and Claims dependent thereon are allowable over the combination of references for the foregoing reasons. The Examiner responds to the above arguing that a person of ordinary skill in the art knows that the primary reference is teaching that the device side of the integrated circuit is the side on which the active devices and contacts are formed, and there is no suggestion in the prior art to the contrary. The Examiner responds that see rejection see primary reference teaches the bending the pins and that this is common in the art. The Examiner responds that see rejection the secondary reference clearly teaches benefits to using solder to making the electrical connection, and solder is well known in the art and the Applicant's argument that solder is bad has noAppl. support in the art. Applicant submits that the argument was directed at the combination of references as to why a person of ordinary skill in the art would not be motivated to modify Ueno with Motz for the benefits alleged by the Examiner. As noted above a special lead frame is required that is pre-bent and only the instant application teaches such a lead frame and therefore its is improper hindsight gleaned from Applicant's own disclsoure. Such a pre-bent lead frame would require copper posts underneath and only the instant application teaches such a post”.
The Examiner responds that a person of ordinary skill in the art knows that the primary reference is teaching that the device side of the integrated circuit is the side on which the active devices and contacts are formed, and there is no suggestion in the prior art to the contrary. In addition secondary reference teaches this to be obvious.
With respect to the solder, the Examiner notes that solder is very common in the art, and provides a both physical strength and excellent electrical connectivity, see secondary reference provided for soldering to a lead, and that a plurality of lead frames to provide connection of the correct shape and the correct bending are shown by many embodiments of the primary reference and not novel, see the prior art shows that a lead frame can be formed to reach the bonding locations desired and in the combination, in Ueno the soldered connections are on the same locations as the wire bonding.
With respect to copper, the Examiner notes that the structural limitations of the claims have been shown to be obvious in view of the prior art combination.
On page 3 the Applicant argues “Claim 11 as amended recites "bending the second segments of a first set of conductive terminals in the array of conductive terminals in a second direction terminating at first ends of the first set of conductive terminals; and bending the second segments of a second set of conductive terminals in the array of conductive terminals in the first direction terminating at second ends of the second set of conductive terminals". As explained above in connection with Claims 1 and 6, Ueno fails to teach at least these limitations and Motz fails to cure this deficiency with respect to Ueno”.
The Examiner responds that this is taught by secondary reference Rock see Fig. 1, see combination.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893