DETAILED ACTION
The Office Action is sent in response to Applicant’s Communication received on 11/30/2022 for application number 18/072,463. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/declaration, IDS, and Claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the set of configurable registers must be shown or the feature canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-20 are objected to as failing to comply with 37 CFR 1.75(a) because of the following informalities:
In claim 1, ll.6, “the rational p/q” should read as “the constant rational p/q”. Claims 2-16, and 18-20 inherit the same deficiency as claim 1 based on dependence.
In claim 1, ll.6, “CSD” should read as “canonical signed digit (CSD)”. Claims 2-16, and 18-20 inherit the same deficiency as claim 1 based on dependence.
In claim 17, ll.7, “the rational p/q” should read as “the constant rational p/q”.
In claim 17, ll.7, , “CSD” should read as “canonical signed digit (CSD)”.
Appropriate correction is required
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1 (and 17), the claim recites “registers defining a plurality of corrective constants”. However it is unclear how the “registers” define the plurality of corrective constants, as “registers” are known to store data not define data. See Stallings (NPL: “Computer Organization and Architecture: Designing for Performance”), see Sec.1.2 Simple Single-Processor Computer and glossary for Registers, Stallings discloses “Registers: Provides storage internal to the CPU” and “High-speed memory internal to the CPU”, and see Sec.16.6 and Glossary that “control register contains bits that control the operation” and “control registers[,] CPU registers employed to control CPU operations”. Claims 2-16, and 18-20 inherit the same deficiency as claim 1 based on dependence. Claim 4, also further recites the same limitation.
For purposes of examination, registers are considered to be storing the data.
Regarding claim 3, the claim recites “wherein the selection logic is configured to select the respective corrective constant for the rounding mode by appropriately configuring a plurality of gates of the fixed logic circuit”. However, it is unclear how the selection logic “select[s]” the corrective constant by “configuring” a plurality of gates. Claims 4-5 inherit the same deficiency as claim 3 based on dependence.
Regarding claim 5, the claim recites “a set of configurable registers arranged to control a plurality of gates”. However it is unclear how the “registers” controls the plurality of gates, as “registers” are known to store data not control gates, rather the bits in the data are used for control. See Stallings Sec.1.2, Sec.16.6 and glossary.
Regarding claim 10, the claim recites “mode registers configurable at run time so as to indicate the rounding mode”. However, it is unclear how the “registers” indicates the rounding modes, as “registers” are known to store data not indicating modes, rather the bits in the data are used for indicating status/states. See Stallings Sec.1.2, Sec.16.6 and glossary.
Regarding claim 19, the claim recites “a … system configured a graphic processing system as set forth in claim 1. However, it is unclear of the relationship between “a graphic processing system” and “a fixed logic circuit”, as claim 1 does not mention “a graphic processing system”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 8-9, and 11-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims 1-2, 8-9, and 11-13 recites a fixed logic circuit and, therefore, is an article of manufacture. Claim 14 recites a processor and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 1 recites:
A fixed logic circuit for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode, where p, q are coprime integers, and x is an m-bit input, the fixed logic circuit comprising:
a truncated summation array of a finite sequence of most significant bits of an infinite CSD expansion of the rational p/q operating on the bits of the input x, the truncated summation array satisfying
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where, for all x,
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is the maximum sum of the partial products of the bits of the infinite CSD expansion not included in the array and
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is the minimum sum of the partial products of the bits of the infinite CSD expansion not included in the array;
registers defining a plurality of corrective constants for a respective plurality of rounding modes, each corrective constant being for use in the fixed logic circuit when the fixed logic circuit is operating in the rounding mode such that the output y is correct for all x; and
selection logic configured to, in dependence on a rounding mode in which the truncated summation array is to operate, select the respective corrective constant for that rounding mode.
The above underlined limitations are related to performing multiplication of an input with a constant rational and adding a correction constant which amount to mathematical relationships, formulas, and calculations that fall under the abstract ideas of “mathematical concepts”, and also falls under “mental steps” as it can be performed as shown in figure 4. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a fixed logic circuit”, “registers”, and “selection logic”. However, the additional elements of “registers”, and “selection logic” are recited at a high-level of generality (i.e., as a generic computer component for storing data; and as a generic computer component for selecting constants) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “a fixed logic circuit” comprises merely generally linking the judicial exception to a particular technological environment. The additional element of “registers” to store data is merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “registers”, and “selection logic” are recited at a high-level of generality (i.e., as a generic computer component for storing data; and as a generic computer component for selecting constants) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “a fixed logic circuit” comprises merely generally linking the judicial exception to a particular technological environment. The additional element of “registers” to store data is merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 2, 8-9, and 11-13 recite further steps and details to performing multiplication of an input with a constant rational and adding a correction constant and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 2 merely states that the corrective constants are used for addition with the output of the summation array. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 8 merely defines a precision of the corrective constant with respect to the summation array. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 9 merely defines various formulas/ranges of the constant c. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 11 merely defines a correction logic used for summing the corrective constant with the output of the summation array. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a correction logic”. However, the additional element of “a correction logic” is recited at a high-level of generality (i.e., as a generic computer component for summing two numbers) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a correction logic” is recited at a high-level of generality (i.e., as a generic computer component for summing two numbers) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claims 12 and 13 merely defines various rounding modes. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 1, claim 14 recites:
A processor comprising the fixed logic circuit as claimed in claim 1.
The claim is related to claim 1, wherein the limitations in claim 1 are directed to performing multiplication of an input with a constant rational and adding a correction constant which amount to mathematical relationships, formulas, and calculations that fall under the abstract ideas of “mathematical concepts”, and also falls under “mental steps” as it can be performed as shown in figure 4. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claim recites an abstract idea.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1 (and 17):
Rose (US 10,235,136 B2) discloses a logic circuit for performing multiplication of an input by a coprime constant rational p/q based on rounding modes with adding a constant, truncated array. various max/min ranges, output registers, and manufacturing/fabrication of the logic circuit, see col.3, 5-6, 8-10, and 19-20, and figures 4, 6, and 7, however Rose does not explicitly disclose
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, registers for storing the corrective constants, CSD, and selection logic.
Drane (US 10,310,816 B2) discloses a logic circuit for performing multiplication of an input by a coprime constant rational p/q using a CSD representation wherein the circuit is truncated and corrected using a constant, logic includes registers, and manufacturing/fabrication of the logic circuit, see col. 5-8, 11, and 14-17, and figure 3, however Drane does not explicitly disclose
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, registers for storing the corrective constants, and selection logic.
Han et al. (US 11,662,981 B2) discloses a truncated array, various controllers/processors, various buffers i.e. constant buffer, and various truncation modes, see figures 1B, 2A-2B and 5, col.17, 18-20, and 30, however Han et al. does not explicitly disclose
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, CSD, and coprime constant rational p/q.
Drane et al. (US 9,933,997 B2) discloses various rounding modes for a rational x/d and manufacturing RTL representations.
Drane et al. (US 8,943,447 B2) discloses various truncated multipliers and RTL synthesizer, see figures 2 and 6-13.
Rose (US 10,409,556 B2) discloses x/d ratio with respect to a rounding scheme, see figures 5, and 12.
Drane (US 2017/0371621 A1) discloses various truncated multipliers, CSD, and RTL synthesizer, see figures 2, 5-6, and 9.
Drane et al. (NPL: “On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays”) discloses various truncations of the multipliers, including a “ragged” truncated multiplier, see figures 1-7.
Bottcher et al. (NPL: “Resource Optimal Truncated Multipliers”) discloses a truncated multiplier, see figure 2.
The prior art of record does not teach or suggest a combination as claimed comprising: “…satisfying
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, where, for all x…”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xia et al. (NPL: “Improved Stochastic Rounding”) discloses various rounding modes, see table 1.
IEEE Computer Society (NPL: “IEEE Standard for Floating-Point Arithmetic”) discloses various rounding modes, See Sec.4.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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