DETAILED ACTION
Claims 1-20 are presented for examination. Claims 1, 5, and 11 stand currently amended.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Finality of Office Action
The following is a brief summary description of new ground(s) of rejection (if any) and the reason why those new ground(s) are made necessary by this amendment:
Claims 1, 5, and 11 have been amended to clarify “the simulation state information comprising register state information, virtual memory state information, or a combination thereof.” This change in claim scope necessitated swapping the previous Aharon reference with US patent 6,006,028 Aharon, et al. [herein “Patent ‘028”]. Respective rejections of other limitations and dependent claims adjusted accordingly.
Response to Arguments
Applicant's remarks filed 29 July 2026 have been fully considered and Examiner’s response is as follows:
Applicant remarks page 10 argues:
(ii) Aharon's trace vector is used in a separate, post-hoc evaluation phase, not used in "generating [a] memory access instruction based on ... the simulation state information" as also recited in claim 1.
Examiner agrees; as currently recited Aharon’s trace vector is not simulation state information as now amended. Accordingly, Applicant’s argument here is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US patent 7,395,196 B2 Emek [herein “Emek”] in view of US patent 6,006,028 Aharon, et al. [herein “Patent ‘028”].
Applicant remarks page 12 further argues:
The Applicant notes that the Office Action provides no specifics regarding how Emek discloses "generating [a] memory access instruction based on the target address range [and] the specification of valid address locations." Instead, the Office Action makes only the general assertion that Emek's disclosure of "choice from a set of available resources" corresponding to "those satisfying respective constraints" somehow discloses generating memory access instructions "based on the target address range, the specification of valid address locations" as recited in claim 1.
Emek is relevant for all that it discloses and not merely the cited portions specifically quoted. However, here Examiner’s previous rejection has specifically further cited Emek column 6 lines 52-53 which state “Transaction examples are a processor accessing a certain memory location.” Accordingly, Emek clearly teaches generating memory access instructions.
Regarding basing those generated memory access instructions, Examiners rejection is based upon a combination of references, and a §103 combination was cited regarding the target address range and valid address locations specifically. Herein, Examiner’s rejection is updated according to the amended claim scope and accordingly Examiner’s rejection now cites Patent ‘028 in significant part regarding this limitation rendering the second-half of Applicant’s argument here moot in light of the new ground of rejection.
Applicant remarks page 12 further argues:
Further, the Office Action's rejection provides no description of how Emek's test generator engine generates its memory access instructions based on simulation state information (interpreted by the Office Action as Aharon's trace vector).
Still further, the Office Action provides no motivation to use Aharon's trace vector during instruction generation.
These arguments are moot in light of the new ground of rejection herein.
Claim Rejections - 35 USC § 112 – Enablement
Claims 1, 5, and 11 have been amended to clarify “the simulation state information comprising register state information, virtual memory state information, or a combination thereof.” This narrows the scope of the claims regarding the simulation state information to that which is enabled by the instant application. Accordingly, Examiner withdraws the §112 rejection of claims 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-6, 8, 11, and 13-15, 19, and 20
Claims 1, 4-6, 8, 11, and 13-15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US patent 7,395,196 B2 Emek [herein “Emek”] in view of US patent 6,006,028 Aharon, et al. [herein “Patent ‘028”].
Claim 1 recites “1. A method for generating a memory access instruction by a network device.” Emek column 6 lines 52-53 disclose “Transaction examples are a processor accessing a certain memory location.” Emek column 5 lines 4-15 disclose:
A "system" as used herein, is a set of components connected using some form of interconnect, which is capable of performing a set of transactions. Components may include processors and other processing elements, caches, various types of memories, bridges, interrupt controllers, DMA engines, etc. The interconnect between these components may comprise, for example, several buses and the bus-bridges connecting them. In many cases, a system contains multiple instances of a certain type of component: for example, a system with symmetric multiprocessing would contain several processors. Examples of transactions include memory mapped I/O (MMIO) and direct memory access (DMA).
The transactions accessing memory locations corresponds with generated memory access instructions. The interconnect of the system is a network. The processor(s) are network devices of the respective interconnect where they are connected.
Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions.
Claim 1 further recites “the method comprising: obtaining constraints on a memory access instruction, the constraints comprising a target address range and a specification of valid address locations.” Emek column 6 lines 65-66 disclose “choice from a set of available resources.” Available resources correspond generally with valid address locations.
Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of test program generators, Patent ‘028 column 7 lines 1-3 and 7-12 teach:
Memory is characterized by the address ranges allowed for instructions and data, and by the selected memory allocation policy ….
Answering the memory allocation requests made by the generator, several characteristics of the desired memory segment must be taken into consideration: the length required, type of memory, intended use, ie source or target, an alignment requirement and complex restrictions in particular a request for a range relative to a given base address.
Allowed memory address ranges correspond with a specification of valid address locations. A complex restriction including a request for a range corresponds with a constraint comprising a target address range.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 1 further recites “obtaining simulation state information relating to a current state of a central processing unit (CPU) design simulation, the simulation state information comprising register state information, virtual memory state information, or a combination thereof.” From the above list of alternatives Examiner is selecting “register state information.”
Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of random test generation, Patent ‘028column 9 lines 56-64 teach “Memory and register resources are described by an ISPS memory declaration. …. They include the memory name, the size of memory cells, and the range of addresses. Several memory resources are possible.” Patent ‘028 column 6 lines 43-48 teach:
Resource manager and allocator 130 is responsible for keeping track of the state of resources and their allocation. It comprises three main components as shown in FIG. 3-register modelling R, memory modelling M and attribute mechanism A The address and length constraint solvers 100 and 110 communicate with the resource manager 130.
Keeping track of state of resources in the architecture simulator is simulation state information. The register modeling in particular corresponds with register state information.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use a resource manager into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 1 further recites “and generating the memory access instruction based on the target address range, the specification of valid address locations, and the simulation state information.” Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions. See further Emek column 6 lines 52-53 (“Transaction examples are a processor accessing a certain memory location.”).
Emek column 6 lines 65-66 disclose “choice from a set of available resources.” The available resources correspond to those satisfying respective constraints.
Regarding memory access locations and transactions of Emek being based on the simulation state information, see further Patent ‘028 column 6 lines 63-66 (“Both static and dynamic information is used by the register allocator to put into effect the desired policy when replying to requests for register allocation”) and Patent ‘028 column 7 lines 7-12.
Claim 4 further recites “4. The method of claim 1, wherein the step of generating comprises: obtaining previous instruction information relating to a history of instructions previously simulated by the CPU design simulation; and generating the memory access instruction further based on the previous instruction information.” Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions.
Emek column 6 lines 65-66 disclose “choice from a set of available resources.” The available resources correspond to those satisfying respective constraints.
Emek does not explicitly disclose history of previously simulated instructions; however, in analogous art of test program generators, Patent ‘028 column 6 lines 60-64 teach “The dynamic information kept for registers is a set of attributes representing the usage of the register, eg initialized, target in-last-instruction, result. Both static and dynamic information is used by the register allocator.” The usage of the register and “target in-last-instruction” correspond with previous instruction information relating to a history of previous instructions. The register allocator using this dynamic information corresponds with generating the memory access instruction further based on the previous instruction information. See further Patent ‘028 lines 1-12.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 5 recites “5. A method for generating a memory access instruction by a network device.” Emek column 6 lines 52-53 disclose “Transaction examples are a processor accessing a certain memory location.” Emek column 5 lines 4-15 disclose:
A "system" as used herein, is a set of components connected using some form of interconnect, which is capable of performing a set of transactions. Components may include processors and other processing elements, caches, various types of memories, bridges, interrupt controllers, DMA engines, etc. The interconnect between these components may comprise, for example, several buses and the bus-bridges connecting them. In many cases, a system contains multiple instances of a certain type of component: for example, a system with symmetric multiprocessing would contain several processors. Examples of transactions include memory mapped I/O (MMIO) and direct memory access (DMA).
The transactions accessing memory locations corresponds with generated memory access instructions. The interconnect of the system is a network. The processor(s) are network devices of the respective interconnect where they are connected.
Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions.
Claim 5 further recites “the method comprising: obtaining constraints on a memory access instruction, the constraints comprising a target address range and a specification of valid address locations.” Emek column 6 lines 65-66 disclose “choice from a set of available resources.” Available resources correspond generally with valid address locations.
Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of test program generators, Patent ‘028 column 7 lines 1-3 and 7-12 teach:
Memory is characterized by the address ranges allowed for instructions and data, and by the selected memory allocation policy ….
Answering the memory allocation requests made by the generator, several characteristics of the desired memory segment must be taken into consideration: the length required, type of memory, intended use, ie source or target, an alignment requirement and complex restrictions in particular a request for a range relative to a given base address.
Allowed memory address ranges correspond with a specification of valid address locations. A complex restriction including a request for a range corresponds with a constraint comprising a target address range.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 5 further recites “obtaining simulation state information relating to a current state of a central processing unit (CPU) design simulation the simulation state information comprising register state information, virtual memory state information, or a combination thereof.” From the above list of alternatives Examiner is selecting “register state information.”
Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of random test generation, Patent ‘028column 9 lines 56-64 teach “Memory and register resources are described by an ISPS memory declaration. …. They include the memory name, the size of memory cells, and the range of addresses. Several memory resources are possible.” Patent ‘028 column 6 lines 43-48 teach:
Resource manager and allocator 130 is responsible for keeping track of the state of resources and their allocation. It comprises three main components as shown in FIG. 3-register modelling R, memory modelling M and attribute mechanism A The address and length constraint solvers 100 and 110 communicate with the resource manager 130.
Keeping track of state of resources in the architecture simulator is simulation state information. The register modeling in particular corresponds with register state information.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use a resource manager into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 5 further recites “generating a plurality of possible target addresses based on the target address range, the specification of valid address locations, and the simulation state information; selecting one of the possible target addresses for the memory access instruction; and generating the memory access instruction based on the selected one of the possible target addresses.” Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions. See further Emek column 6 lines 52-53 (“Transaction examples are a processor accessing a certain memory location.”).
Emek column 6 lines 65-66 disclose “choice from a set of available resources.” The available resources correspond to those satisfying respective constraints.
Regarding memory access locations and transactions of Emek being based on the simulation state information, see further Patent ‘028 column 6 lines 63-66 (“Both static and dynamic information is used by the register allocator to put into effect the desired policy when replying to requests for register allocation”) and Patent ‘028 column 7 lines 7-12.
Claim 6 further recites “6. The method of claim 5 wherein the step of selecting includes randomly selecting the one of possible target address.” Emek column 5 lines 47-51 disclose “The verification system 10 enables the creation of tests that have various degrees of randomness. The ability of the verification system 10 to introduce random unspecified values is fundamental, since design flaws in practice are usually unpredictable.”
Emek column 6 lines 52-53 disclose “Transaction examples are a processor accessing a certain memory location.” Emek column 6 lines 65-66 disclose “choice from a set of available resources. Emek column 7 lines 23-26 discloses “If a test case generator were to generate a transaction of type T, and the type T requires an instance of a resource A and an instance of a resource B, it would randomly choose a pair (a,b) from a Cartesian product.” Randomly choosing a selection for generating a transaction, i.e. of a processor accessing a certain memory location, corresponds to a random selecting of respective possible addresses.
Claim 8 further recites “8. The method of claim 5, wherein the step of generating the plurality of possible target addresses comprises: determining an instruction addressing mode of the memory access instruction.” Emek does not explicitly disclose an addressing mode; however, in analogous art of test program generators, Patent '028 column 10 lines 22-23 teach “automatic test generation of Complex Instructions Sets Computers (CISC).”
Patent ‘028 column 10 line 36 teaches “A 'format' is a finite set of field names.” Patent ‘028 column 12 line 23 provides an example “Format: AW-OPCODE W1, D2, B2.” The format and/or opcode correspond with an addressing model of the instruction.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 8 further recites “determining whether the instruction addressing mode permits combinations of fixed-value operands; determining whether the instruction addressing mode permits combinations of flexible-value operands.” The claim language “fixed-value operands” and “flexible-value operands” are interpreted in light of Specification paragraphs 44-45.
Patent '028 column 10 lines 22-23 teach “automatic test generation of Complex Instructions Sets Computers (CISC).”
Patent '028 column 10 lines 25-40 teach:
A data-type describes such a set of data strings by their length, either fixed or variable under limits, and structure.
….
Definition: A 'sub-operand' over a format F is a triplet holding a length expression over F , an address expression over F and a data expression.
An 'operand' over format Fis a finite set of sub-operands over F. A semantic procedure is a procedure which manipulates the architecture resources and represents the operation performed by the instruction. An 'instruction tree' is a triplet holding a format F, a semantic procedure, and a finite set of operands over F.
Sub-operands plural is a combination of operands. Fixed length data string data types are fixed value. Variable length data string data types are flexible value.
Claim 8 further recites “and for each combination of permitted fixed-value operands and/or flexible-value operands, combining the specification of valid address locations, the target address range, and the combination of permitted fixed-value operands and/or flexible-value operands to generate one possible target address of the plurality of possible target addresses.” Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions. See further Emek column 6 lines 52-53 (“Transaction examples are a processor accessing a certain memory location.”). Emek column 6 lines 65-66 disclose “choice from a set of available resources.”
Emek does not explicitly disclose an addressing mode; however, in analogous art of test program generators, Patent '028 column 10 lines 22-23 teach “automatic test generation of Complex Instructions Sets Computers (CISC).”
Patent ‘028 column 10 lines 56-57 teach “The semantic domain of address expressions consists of addresses as defined above.” The addresses are address locations. Thus, the instruction format outlined here for CISC is a combination of address location along with the range and operands.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 11 recites “11. A network device, comprising: a memory configured to store instructions; and a processor coupled to the memory and configured to execute the instructions stored in the memory.” Emek column 3 lines 47-51 disclose “The invention provides a computer software product, including a computer-readable medium in which computer program instructions are stored, which instructions, when read by a computer, cause the computer to perform a method of verifying a system design.” A computer includes processor and memory.
Claim 11 further recites “to cause the network device to: obtain constraints on a memory access instruction, the constraints comprising a target address range and a specification of valid address locations.” Emek column 6 lines 65-66 disclose “choice from a set of available resources.” Available resources correspond generally with valid address locations.
Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of test program generators, Patent ‘028 column 7 lines 1-3 and 7-12 teach:
Memory is characterized by the address ranges allowed for instructions and data, and by the selected memory allocation policy ….
Answering the memory allocation requests made by the generator, several characteristics of the desired memory segment must be taken into consideration: the length required, type of memory, intended use, ie source or target, an alignment requirement and complex restrictions in particular a request for a range relative to a given base address.
Allowed memory address ranges correspond with a specification of valid address locations. A complex restriction including a request for a range corresponds with a constraint comprising a target address range.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 11 further recites “obtain simulation state information relating to a current state of a central processing unit (CPU) design simulation the simulation state information comprising register state information, virtual memory state information, or a combination thereof.” From the above list of alternatives Examiner is selecting “register state information.”
Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of random test generation, Patent ‘028column 9 lines 56-64 teach “Memory and register resources are described by an ISPS memory declaration. …. They include the memory name, the size of memory cells, and the range of addresses. Several memory resources are possible.” Patent ‘028 column 6 lines 43-48 teach:
Resource manager and allocator 130 is responsible for keeping track of the state of resources and their allocation. It comprises three main components as shown in FIG. 3-register modelling R, memory modelling M and attribute mechanism A The address and length constraint solvers 100 and 110 communicate with the resource manager 130.
Keeping track of state of resources in the architecture simulator is simulation state information. The register modeling in particular corresponds with register state information.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use a resource manager into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 11 further recites “and generate the memory access instruction based on the target address range, the specification of valid address locations, and the simulation state information.” Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions. See further Emek column 6 lines 52-53 (“Transaction examples are a processor accessing a certain memory location.”).
Emek column 6 lines 65-66 disclose “choice from a set of available resources.” The available resources correspond to those satisfying respective constraints.
Regarding memory access locations and transactions of Emek being based on the simulation state information, see further Patent ‘028 column 6 lines 63-66 (“Both static and dynamic information is used by the register allocator to put into effect the desired policy when replying to requests for register allocation”) and Patent ‘028 column 7 lines 7-12.
Claim 13 further recites “13. The network device of claim 11, wherein executing the instructions further causes the network device to: obtain previous instruction information relating to a history of instructions previously simulated by the CPU design simulation; and generate the memory access instruction further based on the previous instruction information.” Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions.
Emek column 6 lines 65-66 disclose “choice from a set of available resources.” The available resources correspond to those satisfying respective constraints.
Emek does not explicitly disclose history of previously simulated instructions; however, in analogous art of test program generators, Patent ‘028 column 6 lines 60-64 teach “The dynamic information kept for registers is a set of attributes representing the usage of the register, eg initialized, target in-last-instruction, result. Both static and dynamic information is used by the register allocator.” The usage of the register and “target in-last-instruction” correspond with previous instruction information relating to a history of previous instructions. The register allocator using this dynamic information corresponds with generating the memory access instruction further based on the previous instruction information. See further Patent ‘028 lines 1-12.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 14 further recites “14. The network device of claim 11, wherein executing the instructions further causes the network device to: generate a plurality of possible target addresses.” Emek column 6 lines 65-66 disclose “choice from a set of available resources.” Available resources correspond generally with valid address locations.
Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of test program generators, Patent ‘028 column 7 lines 1-3 and 7-12 teach:
Memory is characterized by the address ranges allowed for instructions and data, and by the selected memory allocation policy ….
Answering the memory allocation requests made by the generator, several characteristics of the desired memory segment must be taken into consideration: the length required, type of memory, intended use, ie source or target, an alignment requirement and complex restrictions in particular a request for a range relative to a given base address.
Allowed memory address ranges correspond with a specification of valid address locations.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 14 further recites “and randomly select one of the possible target addresses for the memory access instruction.” Emek column 5 lines 47-51 disclose “The verification system 10 enables the creation of tests that have various degrees of randomness. The ability of the verification system 10 to introduce random unspecified values is fundamental, since design flaws in practice are usually unpredictable.”
Emek column 6 lines 52-53 disclose “Transaction examples are a processor accessing a certain memory location.” Emek column 6 lines 65-66 disclose “choice from a set of available resources. Emek column 7 lines 23-26 discloses “If a test case generator were to generate a transaction of type T, and the type T requires an instance of a resource A and an instance of a resource B, it would randomly choose a pair (a,b) from a Cartesian product.” Randomly choosing a selection for generating a transaction, i.e. of a processor accessing a certain memory location, corresponds to a random selecting of respective possible addresses.
Claim 15 further recites “15. The network device of claim 14, wherein executing the instructions further causes the network device to: determine an instruction addressing mode of the memory access instruction.” Emek does not explicitly disclose an addressing mode; however, in analogous art of test program generators, Patent '028 column 10 lines 22-23 teach “automatic test generation of Complex Instructions Sets Computers (CISC).”
Patent ‘028 column 10 line 36 teaches “A 'format' is a finite set of field names.” Patent ‘028 column 12 line 23 provides an example “Format: AW-OPCODE W1, D2, B2.” The format and/or opcode correspond with an addressing model of the instruction.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 15 further recites “determine whether the instruction addressing mode permits combinations of fixed-value operands; determine whether the instruction addressing mode permits combinations of flexible-value operands.” The claim language “fixed-value operands” and “flexible-value operands” are interpreted in light of Specification paragraphs 44-45.
Patent '028 column 10 lines 22-23 teach “automatic test generation of Complex Instructions Sets Computers (CISC).”
Patent '028 column 10 lines 25-40 teach:
A data-type describes such a set of data strings by their length, either fixed or variable under limits, and structure.
….
Definition: A 'sub-operand' over a format F is a triplet holding a length expression over F , an address expression over F and a data expression.
An 'operand' over format Fis a finite set of sub-operands over F. A semantic procedure is a procedure which manipulates the architecture resources and represents the operation performed by the instruction. An 'instruction tree' is a triplet holding a format F, a semantic procedure, and a finite set of operands over F.
Sub-operands plural is a combination of operands. Fixed length data string data types are fixed value. Variable length data string data types are flexible value.
Claim 15 further recites “and for each combination of permitted fixed-value operands and/or flexible-value operands, combine the specification of valid address locations, the target address range, and the combination of permitted fixed-value operands and/or flexible-value operands to generate one possible target address of the plurality of possible target addresses.” Emek column 6 lines 3-6 disclose “The test generator engine 22 may also receive some generic knowledge of the system specification, and can exploit this knowledge to generate sequences of transactions to form the test cases 30.” Generating sequences of transactions corresponds with generating the memory access instructions. See further Emek column 6 lines 52-53 (“Transaction examples are a processor accessing a certain memory location.”). Emek column 6 lines 65-66 disclose “choice from a set of available resources.”
Emek does not explicitly disclose an addressing mode; however, in analogous art of test program generators, Patent '028 column 10 lines 22-23 teach “automatic test generation of Complex Instructions Sets Computers (CISC).”
Patent ‘028 column 10 lines 56-57 teach “The semantic domain of address expressions consists of addresses as defined above.” The addresses are address locations. Thus, the instruction format outlined here for CISC is a combination of address location along with the range and operands.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek and Patent ‘028. One having ordinary skill in the art would have found motivation to use CISC instruction sets into the system of test case generation for functional verification for the advantageous purpose of “developing generators for non-traditional processors such as graphic engines and I/O controllers.” See Patent ‘028 column 4 lines 39-40.
Claim 19 further recites “19. The network device of claim 11, wherein the instructions comprise an instruction stream generator.” The claim language “instruction stream generator” is interpreted in light of Specification paragraph 36.
Emek abstract discloses “Generation of test cases for functional verification of a complex system-under-test is achieved by the use of a probability matrix.” Generating test cases for functional verification corresponds with being an instruction stream generator.
Claim 20 further recites “20. The network device of claim 11, wherein executing the instructions further causes the network device to: send to the CPU design simulation, an executable test case including the memory access instruction.” Emek column 6 lines 6-7 disclose “The test cases 30 are executed by an execution engine 12 on an implementation of the system under test.”
Emek column 6 lines 52-53 disclose “Transaction examples are a processor accessing a certain memory location.” Accessing a memory location corresponds with memory access instructions.
Dependent Claims 2, 3, 7, and 12
Claims 2, 3, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Emek and Patent ‘028 as applied to claims 1, 5, and 11 above, and further in view of US patent 6,353,829 B1 Koblenz, et al. [herein “Koblenz”].
Claim 2 further recites “2. The method of claim 1, wherein the step of generating comprises: storing a value in a previously unused memory location of the CPU design simulation.” Emek column 6 line 59 disclose “executing a store or a load assembly instruction.”
But neither Emek nor Patent ‘028 explicitly disclose storing in previously unused memory; however, in analogous art of computer memory operation, Koblenz column 5 lines 23-33 teach:
Conventional computer systems provide memory allocation techniques that allow programs to allocate and de-allocate (i.e., free) memory dynamically. To allocate a block of memory, a program invokes a memory allocation routine (e.g., "malloc") passing the size of the requested block of memory. The memory allocation routine locates a free block of memory, which is usually stored in a "heap," marks the block as being allocated, and returns to the program a pointer to the allocated block of memory. The program can then use the pointer to store data in the block of memory.
Locating free blocks of memory is selecting memory from a previously unused memory location.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek, Patent ‘028, and Koblenz. One having ordinary skill in the art would have found motivation to use conventional memory allocation into the system of test case generation for functional verification because tracking free memory in a heap for allocation/free routines is art recognized method suitable for the purpose of memory allocation. See Koblenz column 5 lines 23-37.
Claim 2 further recites “and generating the memory access instruction further based on an address of the previously unused memory location.” Koblenz column 5 lines 23-33 teach “returns to the program a pointer to the allocated block of memory. The program can then use the pointer to store data in the block of memory.” Returning a pointer to the block of memory is generating memory access according to the address of the particular unused and now allocated memory location. A pointer includes an address.
Claim 3 further recites “3. The method of claim 2, wherein the step of storing is performed according to information stored in an executable test case.” Emek column 6 lines 6-7 disclose “The test cases 30 are executed by an execution engine 12 on an implementation of the system under test.”
Claim 7 further recites “7. The method of claim 5 wherein the step of selecting includes selecting a previously unused memory location of the CPU design simulation.” Emek column 6 line 59 disclose “executing a store or a load assembly instruction.”
But neither Emek nor Patent ‘028 explicitly disclose storing in previously unused memory; however, in analogous art of computer memory operation, Koblenz column 5 lines 23-33 teach:
Conventional computer systems provide memory allocation techniques that allow programs to allocate and de-allocate (i.e., free) memory dynamically. To allocate a block of memory, a program invokes a memory allocation routine (e.g., "malloc") passing the size of the requested block of memory. The memory allocation routine locates a free block of memory, which is usually stored in a "heap," marks the block as being allocated, and returns to the program a pointer to the allocated block of memory. The program can then use the pointer to store data in the block of memory.
Locating free blocks of memory is selecting memory from a previously unused memory location.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek, Patent ‘028, and Koblenz. One having ordinary skill in the art would have found motivation to use conventional memory allocation into the system of test case generation for functional verification because tracking free memory in a heap for allocation/free routines is art recognized method suitable for the purpose of memory allocation. See Koblenz column 5 lines 23-37.
Claim 12 further recites “12. The network device of claim 11, wherein executing the instructions further causes the network device to: store a value in a previously unused memory location of the CPU design simulation.” Emek column 6 line 59 disclose “executing a store or a load assembly instruction.”
But neither Emek nor Patent ‘028 explicitly disclose storing in previously unused memory; however, in analogous art of computer memory operation, Koblenz column 5 lines 23-33 teach:
Conventional computer systems provide memory allocation techniques that allow programs to allocate and de-allocate (i.e., free) memory dynamically. To allocate a block of memory, a program invokes a memory allocation routine (e.g., "malloc") passing the size of the requested block of memory. The memory allocation routine locates a free block of memory, which is usually stored in a "heap," marks the block as being allocated, and returns to the program a pointer to the allocated block of memory. The program can then use the pointer to store data in the block of memory.
Locating free blocks of memory is selecting memory from a previously unused memory location.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek, Patent ‘028, and Koblenz. One having ordinary skill in the art would have found motivation to use conventional memory allocation into the system of test case generation for functional verification because tracking free memory in a heap for allocation/free routines is art recognized method suitable for the purpose of memory allocation. See Koblenz column 5 lines 23-37.
Claim 12 further recites “and generate the memory access instruction further based on an address of the previously unused memory location.” Koblenz column 5 lines 23-33 teach “returns to the program a pointer to the allocated block of memory. The program can then use the pointer to store data in the block of memory.” Returning a pointer to the block of memory is generating memory access according to the address of the particular unused and now allocated memory location. A pointer includes an address.
Dependent Claims 9, 10, and 16-18
Claims 9, 10, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Emek and Patent ‘028 as applied to claim 5 above, and further in view of Aharon, A., et al. “Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generator” IBM Sys. J., vol. 30, no. 4 (1991) [herein “Aharon”].
Claim 9 further recites “9. The method of claim 5, further comprising, removing one or more possible target addresses from the plurality of possible target addresses based on a filter criterion prior to selecting one possible target address of the plurality of possible target addresses.” Emek column 6 lines 65-66 disclose “choice from a set of available resources.” Available resources correspond generally with valid address locations.
Patent ‘028 column 7 lines 1-3 and 7-12 teach “Memory is characterized by the address ranges allowed for instructions.”
But neither Emek nor Patent ‘028 explicitly disclose a filter criterion removing possible target addresses; however, in analogous art of random test generation Aharon page 532 left column sixth bullet item teaches “Protect the required areas of memory and certain registers from being used by the generated test.” Protecting areas of memory from use by the generated tests corresponds with removing possible target addresses before selecting possible target addresses. The areas of memory being required corresponds with a filter criterion.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek, Patent ‘028, and Aharon. One having ordinary skill in the art would have found motivation to use restrictions on memory addresses into the system of test case generation for functional verification for the advantageous purpose of “to automatically produce a vast number of test programs for the comprehensive verification of the design.” See Aharon page 527 last line to page 528 line 2.
Claim 10 further recites “10. The method of claim 9, wherein the filter criterion is based on one of the simulation state information and previous instruction information relating to a history of instructions previously simulated by the CPU design simulation.” From the above list of alternatives the Examiner is selecting “simulation state information.”
Neither Emek nor Patent ‘028 explicitly disclose a filter criterion removing possible target addresses; however, in analogous art of random test generation, Aharon page 529 left column first paragraph teaches “The generated test programs are relatively simple, and again, must obey many restrictions.” The restrictions which must be obeyed correspond to one or more constraints.
Aharon page 529 left column first bullet item teaches “initialization of base registers to get the allowed memory addresses.” The allowed memory addresses are a specification of valid address locations. Memory addresses outside the allowed memory addresses are addresses which have been removed from possible target addresses. The initialization of registers is simulation state information.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek, Patent ‘028, and Aharon. One having ordinary skill in the art would have found motivation to use restrictions on memory addresses into the system of test case generation for functional verification for the advantageous purpose of “to automatically produce a vast number of test programs for the comprehensive verification of the design.” See Aharon page 527 last line to page 528 line 2.
Claim 16 further recites “16. The network device of claim 14, wherein executing the instructions further causes the network device to: remove one or more possible target addresses from the plurality of possible target addresses.” Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of random test generation Aharon page 532 left column sixth bullet item teaches “Protect the required areas of memory and certain registers from being used by the generated test.” Protecting areas of memory from use by the generated tests corresponds with removing possible target addresses before selecting possible target addresses. The areas of memory being required corresponds with a filter criterion.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek, Patent ‘028, and Aharon. One having ordinary skill in the art would have found motivation to use restrictions on memory addresses into the system of test case generation for functional verification for the advantageous purpose of “to automatically produce a vast number of test programs for the comprehensive verification of the design.” See Aharon page 527 last line to page 528 line 2.
Claim 16 further recites “based on a filter criterion prior to randomly selecting one possible target address of the plurality of possible target addresses.” Emek column 5 lines 47-51 disclose “The verification system 10 enables the creation of tests that have various degrees of randomness. The ability of the verification system 10 to introduce random unspecified values is fundamental, since design flaws in practice are usually unpredictable.”
Emek column 6 lines 52-53 disclose “Transaction examples are a processor accessing a certain memory location.” Emek column 6 lines 65-66 disclose “choice from a set of available resources. Emek column 7 lines 23-26 discloses “If a test case generator were to generate a transaction of type T, and the type T requires an instance of a resource A and an instance of a resource B, it would randomly choose a pair (a,b) from a Cartesian product.” Randomly choosing a selection for generating a transaction, i.e. of a processor accessing a certain memory location, corresponds to a random selecting of respective possible addresses.
Claim 17 further recites “17. The network device of claim 16, wherein executing the instructions further causes the network device to: obtain previous instruction information relating to a history of instructions previously simulated by the CPU design simulation, wherein the filter criterion is based on the previous instruction information.” Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of random test generation, Aharon page 533 left column second paragraph “Coverage evaluation helps to detect and remove ‘holes’ in the biasing. The final set of strategies ensures that there is a generation process with a reasonable probability of covering every architectural feature and every design block.”
Aharon page 535 right column third paragraph teaches:
One of the simplest coverage techniques is ensuring that each line of the code has been executed at least once. A special function analyzes the character representation of an APL function and splits each labeled line into two lines. The first one contains the label and an assignment statement that sets the corresponding bit in a trace vector associated with this function. …. A bucket of test programs is then executed (using the Run mode) on the "trace-modified" RTPG. Zero values in the trace vector indicate blocks that were not reached.
The trace vector indicating which blocks were not reached is previous instruction information.
Aharon page 535 last paragraph to page 536 first line disclose “The information from the previous step (line coverage) is used to select only those test programs that pass through the skipped line.” Using coverage information to select only those test programs which pass through a skipped line corresponds with a filter criteria based on previous instruction information.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek, Patent ‘028, and Aharon. One having ordinary skill in the art would have found motivation to use restrictions on memory addresses into the system of test case generation for functional verification for the advantageous purpose of “to automatically produce a vast number of test programs for the comprehensive verification of the design.” See Aharon page 527 last line to page 528 line 2.
Claim 18 further recites “18. The network device of claim 16, wherein the filter criterion is based on the simulation state information.” Emek does not explicitly disclose a target address range and a specification of valid address locations; however, in analogous art of random test generation, Aharon page 529 left column first paragraph teaches “The generated test programs are relatively simple, and again, must obey many restrictions.” The restrictions which must be obeyed correspond to one or more constraints.
Aharon page 529 left column first bullet item teaches “initialization of base registers to get the allowed memory addresses.” The allowed memory addresses are a specification of valid address locations. Memory addresses outside the allowed memory addresses are addresses which have been removed from possible target addresses. The initialization of registers is simulation state information.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Emek, Patent ‘028, and Aharon. One having ordinary skill in the art would have found motivation to use restrictions on memory addresses into the system of test case generation for functional verification for the advantageous purpose of “to automatically produce a vast number of test programs for the comprehensive verification of the design.” See Aharon page 527 last line to page 528 line 2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jay B Hann whose telephone number is (571)272-3330. The examiner can normally be reached M-F 10am-7pm EDT.
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/Jay Hann/Primary Examiner, Art Unit 2186 20 August 2026
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