DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 02/03/2026 has been entered. The 2nd claim 3 and claim 7 are canceled. Claims 1-6 and 8-18 remain pending in the application.
Claim Objections
Claims 1, 8, 11, 14, 17 and 18 are objected to because of the following informalities:
Claim 1 recites ‘the Sum vertex’; however, it should recite ‘the child Sum vertex’.
Claim 8 recites ‘… in one or more of in claim 1’; however, it should recite ‘…
Claim 11 recites ‘… in one or more of in claim 10’; however, it should recite ‘…
Claim 14 recites ‘… in one or more of in claim 13’; however, it should recite ‘…
Claim 17 recites ‘… in one or more of in claim 16’; however, it should recite ‘… in claim 16’.
Claim 18 recites ‘… in any one or more of claim 16’; however, it should recite ‘… in .
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Le et al. (hereinafter Le), US 20180357546 A1, in view of RAVISHANKAR et al. (hereinafter RAVISHANKAR), US 20180203673 A1, further in view of Golovashkin US 20170046614 A1.
Regarding independent claim 1, Le teaches an apparatus (Fig. 2, 100; [0026]) comprising:
memory (Fig. 2, 140; [0026]); and
logic circuitry coupled with the memory to (Fig. 2, 120; [0026]):
convert input values for an input layer of a neural network into function data structures ([0021] As shown in FIG. 1, the convolutional neural networks 10 includes convolutional layers 11 and a fully connected layer (FCL) 12; [0022] Each convolutional layer 11 performs convolutional operation on input data to extract feature vectors regarding the input data. The fully connected layer 12 classifies the input data based on the feature vectors extracted by the convolutional layers 11; [0026] As shown in FIG. 2, the information processing system 100 includes an input unit 110 that receives the input data to be processed, a processer 120 processing the input data, an output unit 130 outputting a processing result, and a storage 140 storing parameters, such as weights and bias parameters).
for each layer of the neural network after the input layer, proceeding from the layer closest to the input layer to the desired output node ([0021] As shown in FIG. 1, the convolutional neural networks 10 includes convolutional layers 11 and a fully connected layer (FCL) 12; [0022] Each convolutional layer 11 performs convolutional operation on input data to extract feature vectors regarding the input data. The fully connected layer 12 classifies the input data based on the feature vectors extracted by the convolutional layers 11; [0023] This exemplary embodiment assumes a model of the convolutional neural networks 10 which consists of an input layer, intermediate layer(s) (hidden layer(s)), and an output layer):
for each node in the layer:
if the layer is an output layer, and a current node is not going to be used as a constraint or objective function (or solved for, in the case of limit analysis), continue to a next node without doing further work ([0037] FIGS. 4A and 4B depict structures of the trees including the same subtree 225, 230; [0038] In a process of analyzing multiple trees, i.e. in a calculation of respective feature vectors of each node included in the trees, the subtree included in at least two of the trees in common is repeatedly processed; [0042] The present exemplary embodiment optimizes the TBCNN by a node-sharing of the node(s) included in the common subtree. Note that the optimization of the TBCNN is conducted as a pre-process on the trees before the tree-based convolutional layer processor 121 executes a process corresponding to the process performed by the convolutional layers 11 of FIG. 1. The node-sharing refers to combining multiple trees to generate one tree, i.e. a combined tree in such a way that subtrees of the combined tree share a node(s) that exists in common in at least two of the multiple trees before combining. Note that such a node existing in common in the multiple trees may be referred to as a common node);
otherwise,
construct a new graph, consisting of an activation function vertex, and a child Sum vertex, a sum being an argument for the activation function vertex ([0034] The TBCNN shown in FIG. 3 includes the first layer 205, the second layer 210, the third layer 215 and the fourth layer 220. The first layer 205 in the shown example corresponds to the input layer in the above mentioned model. The second layer 210 and the third layer 215 respectively correspond to the TBC layers. In other words, the TBCNN of FIG. 3 includes two TBC layers. The fourth layer 220 corresponds to the fully connected layer. Note that each node of the second layer 210 includes two features and each node of the third layer 215 includes four features; [0035] In the TBCNN, information on each node of the trees is embedded into respective feature vectors. Further, in the TBC layers which are consecutively arranged, feature vectors in the next TBC layer are calculated from feature vectors of the corresponding node and its descendant nodes in the previous TBC layer);
for each connection between a current node and nodes in a prior layer, add a child to the child Sum vertex that is a Multiply vertex, whose children in turn are a constant containing a weight of a connection to a prior node, and a graph representing a value of the prior node ([0036] For example, feature vectors of a node 1 of the third layer 215 are calculated from feature vectors of the nodes of the second layer 210 and the weights and bias parameters assigned to the nodes. More specifically, the feature vectors of the node 1 of the third layer 215 are calculated from the feature vectors of a node 1, a node 2 and a node 5 of the second layer. For example, the feature vectors of the node 1 of the third layer 215 is obtained by multiplying the node 1, the node 2 and the node 5 of the second layer 210 by the respective weights and adding the respective biases to the node 1, the node 2 and the node 5. Note that the node 1 of the second layer 210 corresponds to a node of the previous TBC layer in the above explanation. The nodes 2 and 5 correspond to descendants, i.e. child nodes of the node 1); and
add another child to the Sum vertex comprising a constant containing a bias value ([0036] For example, feature vectors of a node 1 of the third layer 215 are calculated from feature vectors of the nodes of the second layer 210 and the weights and bias parameters assigned to the nodes).
Le doesn’t explicitly teach function data structures representing constants and formulas with variables;
retrieve directed acyclic graphs used as values from desired output nodes;
for each output node to be used as a constraint, or to be solved for limit analysis, construct a comparison vertex against a “passing” value, using the output node's graph and passing value as children; and pass a graph corresponding to the output node to an optimizer that optimizes an objective while satisfying one or more constraints;
and/or for each output node to be used as an objective function, pass the graph corresponding to the output node to the optimizer.
However, in the same field of endeavor, RAVISHANKAR teaches
function data structures representing constants and formulas with variables ([0030] TABLE 1; [0031] FIG. 3 is a computation graph 300 of the example program listing shown in Table 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of a computation graph used to recognize instances where inter-stage optimizations can be performed as suggested in RAVISHANKAR into Le’s system because both of these systems are addressing optimization on directed acyclic graphs. This modification would have been motivated by the desire of an efficient programming infrastructure that supports performing optimizations across operations (RAVISHANKAR, [0004]-[0006]).
The combination of Le and RAVISHANKAR does not explicitly teach
retrieve directed acyclic graphs used as values from desired output nodes;
for each output node to be used as a constraint, or to be solved for limit analysis, construct a comparison vertex against a “passing” value, using the output node's graph and passing value as children; and pass a graph corresponding to the output node to an optimizer that optimizes an objective while satisfying one or more constraints;
and/or for each output node to be used as an objective function, pass the graph corresponding to the output node to the optimizer.
However, in the same field of endeavor, Golovashkin teaches
retrieve directed acyclic graphs used as values from desired output nodes ([0062] FIG. 1 is a block diagram that depicts an example computer 100, in an embodiment. Computer 100 performs nonlinear unconstrained optimization for accelerated training of an artificial neural network. Computer 100 includes neural network 110, objective function 150, and sparse Hessian matrix 140. These are stored within the, perhaps distributed, memory of computer 100; [0063] Neural network 110 is an artificial neural network that includes many interconnected neurons, such as vertices 121-124. Vertices 121-124 are representative of many, perhaps hundreds of billions, of neurons in neural network 110. The neurons of neural network 110 are interconnected by many synapses, such as edges 131-134. Edges 131-134 are representative of many, perhaps hundreds of trillions, of synapses in neural network 110; [0064] The edges of neural network 110 are directed. An edge originates at a vertex and terminates at another vertex. Together the edges and vertices of neural network 110 form a directed graph. Neural network 110 has additional topological constraints. Because neural network 110 is feedforward, the graph of neural network 110 is a directed acyclic graph);
for each output node to be used as a constraint, or to be solved for limit analysis, construct a comparison vertex against a “passing” value, using the output node's graph and passing value as children ([0070] Training entails adjustment of edge weights to alter the mathematical functionality of neural network 110, thereby improving the overall behavior of neural network 110. If neural network 110 is used for pattern recognition, such as optical character recognition, then the overall behavior of neural network 110 is improved when the accuracy of recognition improves. During training, the accuracy of neural network 110 is quantified according to objective function 150. Objective function 150 compares an actual behavior of neural network 110 with an expected behavior); and pass a graph corresponding to the output node to an optimizer that optimizes an objective while satisfying one or more constraints; and/or for each output node to be used as an objective function, pass the graph corresponding to the output node to the optimizer ([0071] As edge weights are intelligently adjusted, the value yielded by objective function 150 approaches some constant limit that represents perfect accuracy. However, this approaching occurs gradually, for which computer 100 may calculate a gradient of objective function 150. Gradual approaching occurs because training entails repetition by iteration. Each iteration has three phases. The first phase is sparsification; [0072] The second phase is a forward-backward pass over the graph. During the forward-backward pass, computer 100 calculates a value of and a gradient of the objective function on the full graph, and calculates the Hessian matrix 140 on the sparsified or reduced graph. The elements of sparse Hessian matrix 140 are coefficients calculated as partial second derivatives of edge weights. Calculation of sparse Hessian matrix 140 during an iteration is based on sparse Hessian matrix 140 of the previous iteration. As sparsification removes edges from the graph, the graph becomes sparser. This makes the Hessian matrix 140 sparser, such that more coefficients of sparse Hessian matrix 140 become zero, with zero representing a removed edge. Computer 100 may store sparse Hessian matrix 140 in a format optimized for a sparse matrix; [0073] The third phase of each iteration entails solving a quasi-Newton method of optimization based on sparse Hessian matrix 140 and the value of and the gradient of objective function 150. This solving calculates adjustments to edge weights, which improves the accuracy of neural network 110. Quasi-Newton methods boost efficiency by avoiding fully calculating a Hessian matrix every iteration. Instead, quasi-Newton methods incrementally update a reusable Hessian matrix based on calculated gradients; Fig. 9; [0121] Second phase 904 refines the results of first phase 902 to improve the connectivity of each node. Second phase 904 emphases precision. Second phase 904 iterates over all nodes. At each node, the five sequential steps are performed; [0122] First phase 902 may have removed too many or too few input edges or output edges of the current node. An implementation may define an ideal input count and a minimum output count as constants to constrain fan-in and fan-out of edges at a node. Likewise, an implementation may define an ideal input weight to compare against the current input weight of a node. Upon each node of the graph, the steps shown in the flowchart of FIG. 12 are performed to accomplish second phase 904).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of quantifying the accuracy of neural network according to objective function as suggested in Golovashkin into Le and RAVISHANKAR’s system because both of these systems are addressing optimization on directed acyclic graphs. This modification would have been motivated by the desire for improving the accuracy of neural network (Golovashkin, [0073]).
Regarding dependent claim 2, the combination of Le, RAVISHANKAR and Golovashkin teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. Le further teaches wherein the function data structures comprise a tree-based or graph-based data structure ([0029] In the present exemplary embodiment, the processor 120 uses tree-based convolutional neural networks (TBCNN). The TBCNN processes the input data having a tree structure. The TBCNN maps the feature vectors on each convolutional layer, i.e. tree-based convolutional (TBC) layer, without changing the form of the tree structure. In other words, the respective TBC layers generate feature maps having the same tree structure as the input data).
Regarding dependent claim 3, the combination of Le, RAVISHANKAR and Golovashkin teaches all the limitations as set forth in the rejection of claim 2 that is incorporated. Le further teaches wherein the function data structures comprise a directed acyclic graph (DAG) ([0037] FIGS. 4A and 4B depict structures of the trees including the same subtree 225, 230; [0058] FIG. 8 depicts a structure of a tree 800 generated by combining the trees of FIGS. 4A and 4B; [0074] Here, the above tree is a sort of a directed acyclic graph (DAG). Further, as mentioned above, the tree shown in FIG. 8 generated by combing multiple trees may not have an exact tree structure. The tree shown in FIG. 8 is a DAG itself. It is therefore the above mentioned exemplary embodiment is applicable to not only the information processing system 100 for analyzing data having the tree structure but also an information processing system for analyzing DAGs.).
Regarding dependent claim 4, the combination of Le, RAVISHANKAR and Golovashkin teaches all the limitations as set forth in the rejection of claim 3 that is incorporated. RAVISHANKAR further teaches wherein vertex types of the DAG comprise two or more vertex types in a group of vertex types comprising sum operation, arithmetic operation, variables, constant values, activation function, comparison operations, division operations, and subtraction operations ([0031] FIG. 3 is a computation graph 300 of the example program listing shown in Table 1; [0034] FIG. 4 illustrates an optimized computation graph 400 for the example program listed in Table 2; [0037] In phase 1 of FIG. 4, a matrix vector product (“gnp.dot(W, x)” in line 5 of Table 2) is computed. The matrix vector product could use, for example, MKL (Math Kernel Library) or CuBLAS (CUDA® Basic Linear Algebra Subprograms); [0038] In phase 2, fused execution of the computation that represents the activation function is applied to the result of phase 1 (“gnp.exp” and “+” in line 5 of Table 2), followed by a reduction (“gnp.sum” in line 6 of Table 2) to compute the normalization factor. This can be executed as a map-reduce computation. Note that this phase has two outputs: the value of the exponentiation (“exp” in FIG. 4), and the result of reducing this array (“sum_reduce” in FIG. 4) to get the normalization factor; [0039] In phase 3, the exponentiation from phase 2 is divided by (“div” in FIG. 4) the computed normalization (line 7 of Table 2)).
Regarding dependent claim 5, the combination of Le, RAVISHANKAR and Golovashkin teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. RAVISHANKAR further teaches the activation function vertex having a single child that is an argument to an activation function ([0038] In phase 2, fused execution of the computation that represents the activation function is applied to the result of phase 1 (“gnp.exp” and “+” in line 5 of Table 2), followed by a reduction (“gnp.sum” in line 6 of Table 2) to compute the normalization factor).
Regarding dependent claim 6, the combination of Le, RAVISHANKAR and Golovashkin teaches all the limitations as set forth in the rejection of claim 5 that is incorporated. RAVISHANKAR further teaches the activation function being a DAG of mathematical operations, with a single child to be used as an argument utilized as a child at one or more places in the graph ([0038] In phase 2, fused execution of the computation that represents the activation function is applied to the result of phase 1 (“gnp.exp” and “+” in line 5 of Table 2), followed by a reduction (“gnp.sum” in line 6 of Table 2) to compute the normalization factor. This can be executed as a map-reduce computation. Note that this phase has two outputs: the value of the exponentiation (“exp” in FIG. 4), and the result of reducing this array (“sum_reduce” in FIG. 4) to get the normalization factor).
Regarding independent claim 8, it is a system claim that described in one or more of in claim 1. Therefore, it is rejected for the same reason as claim 1 above. Le further teaches wherein the logic circuitry comprises processing circuitry, memory coupled with the processing circuitry, a communications interface coupled with the processing circuitry, and data storage coupled with the processing circuitry (Fig. 2; [0026] As shown in FIG. 2, the information processing system 100 includes an input unit 110 that receives the input data to be processed, a processer 120 processing the input data, an output unit 130 outputting a processing result, and a storage 140 storing parameters; [0070] Referring to FIG. 9, there is shown an example of a hardware configuration of the information processing system 100. As shown in the figure, the information processing system 100 may include a central processing unit (CPU) 91, a main memory 92 connected to the CPU 91 via a motherboard (M/B) chip set 93, and a display driver 94 connected to the CPU 91 via the same M/B chip set 93. A network interface 96, a magnetic disk device 97, an audio driver 98, and a keyboard/mouse 99 are also connected to the M/B chip set 93 via a bridge circuit 95), wherein the processing circuitry comprises one or more processors residing in one or more servers ([0027] The processor 120 may include a tree-based convolutional (TBC) layer processor 121 and a fully connected layer (FCL) processor 122; [0073] Note that the information processing system 100 may be configured by a single computer. Alternatively, the information processing system 100 may be distributed in multiple computers. Further, a part of the function of the information processing system 100 may be performed by servers on the network, such as a cloud server), wherein the memory comprises memory in the one or more servers, and the data storage comprises data storage residing in or coupled with the server, wherein the data storage further comprises data storage elements residing in other servers coupled with the one or more servers ([0076] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire; [0077] Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device), wherein the memory comprises code executable by the processing circuitry, wherein the code is distributed in whole or in part between memory in one or more of the one or more servers and/or residing in the data storage ([0078] Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention).
Regarding independent claim 9, it is a medium claim that perform operations, the operations to perform the functionality described in claim 1. Therefore, it is rejected for the same reason as claim 1 above. Le further teaches a non-transitory storage medium containing instructions, which when executed by a processor, cause the processor to perform operations ([0027] The processor 120 may include a tree-based convolutional (TBC) layer processor 121 and a fully connected layer (FCL) processor 122; [0076] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device; [0080] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks).
Regarding independent claim 10, Le teaches an apparatus (Fig. 2, 100; [0026]) comprising:
memory (Fig. 2, 140; [0026]); and
logic circuitry coupled with the memory to (Fig. 2, 120; [0026])
convert input values for an input layer of a neural network to function data structures ([0021] As shown in FIG. 1, the convolutional neural networks 10 includes convolutional layers 11 and a fully connected layer (FCL) 12; [0022] Each convolutional layer 11 performs convolutional operation on input data to extract feature vectors regarding the input data. The fully connected layer 12 classifies the input data based on the feature vectors extracted by the convolutional layers 11; [0026] As shown in FIG. 2, the information processing system 100 includes an input unit 110 that receives the input data to be processed, a processer 120 processing the input data, an output unit 130 outputting a processing result, and a storage 140 storing parameters, such as weights and bias parameters).
Le doesn’t explicitly teach
each input value associated with a different input node, each input node to representing a constant or a formula with one or more variables;
create a new neural network type of vertex, the new neural network type of vertex comprising:
a child vertex per input node;
a three dimensional array of weights comprising a first dimension to represent a current layer, a second dimension to represent a current node in the current layer, and a third dimension to represent a current weight between the current node and a prior node; and
an index of an output node to be evaluated in an output layer;
wherein a value of each node is represented by a function data structure;
wherein each vertex in the function data structure has a method solve that evaluates the vertex;
pass a graph of the function data structure corresponding to the output node to an optimizer that optimizes an objective while satisfying one or more constraints.
However, in the same field of endeavor, RAVISHANKAR teaches
each input value associated with a different input node, each input node to representing a constant or a formula with one or more variables ([0030] TABLE 1; [0031] FIG. 3 is a computation graph 300 of the example program listing shown in Table 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of a computation graph used to recognize instances where inter-stage optimizations can be performed as suggested in RAVISHANKAR into Le’s system because both of these systems are addressing optimization on directed acyclic graphs. This modification would have been motivated by the desire of an efficient programming infrastructure that supports performing optimizations across operations (RAVISHANKAR, [0004]-[0006]).
The combination of Le and RAVISHANKAR does not explicitly teach
create a new neural network type of vertex, the new neural network type of vertex comprising:
a child vertex per input node;
a three dimensional array of weights comprising a first dimension to represent a current layer, a second dimension to represent a current node in the current layer, and a third dimension to represent a current weight between the current node and a prior node; and
an index of an output node to be evaluated in an output layer;
wherein a value of each node is represented by a function data structure;
wherein each vertex in the function data structure has a method solve that evaluates the vertex;
pass a graph of the function data structure corresponding to the output node to an optimizer that optimizes an objective while satisfying one or more constraints.
However, in the same field of endeavor, Golovashkin teaches
create a new neural network type of vertex, the new neural network type of vertex comprising:
a child vertex per input node ([0086] FIG. 6 depicts tabular data structures for encoding a directed acyclic graph. In the lower right of FIG. 6. is the graph. The graph has nodes 1-4, which are vertices. The graph also has edges 1-7. In the lower left of FIG. 6 is the node table. Each row of the node table encodes a node. The # column of the node table is an implied column of node indexes. In the upper left of FIG. 6 is the edge table. Each row of the edge table encodes an edge. The # column of the edge table is an implied column of edge indexes);
a three dimensional array of weights comprising a first dimension to represent a current layer, a second dimension to represent a current node in the current layer, and a third dimension to represent a current weight between the current node and a prior node ([0087] the edge table and the node table also encode two indirect circular linked lists for each node. One list contains edges that originate at a node. The other list contains edges that terminate at the node. Each link of these lists comprises a row index, of either the edge table or the node table, that designates an edge or node. Each list is sorted by edge weight, either ascending or descending; [0088] Each node is the head of two lists, which are linked into by the edge-in and edge-out columns of the node table. The edge-in column has an edge index of an edge, with the least value of weight, that terminates at the node; [0093] In step 802, edges of a directed acyclic graph are stored in an edge array having a row for each edge. Each edge originates at a vertex of the graph and terminates at another vertex. Each edge has a weight, a next input index, and a next output index); and
an index of an output node to be evaluated in an output layer ([0089] The values of the next-in column of the edge table are a mixture of edge indices into the edge table and node indices into the node table. To distinguish indices of the two tables, a link that is based on a node index may be encoded as the additive inverse of the node index. Thus although FIG. 6 shows node:4 as the value of the next-in column of the edge table for edge 3, the value may be encoded as −4. An embodiment may instead use a different means of distinguishing edge indices from node indices, such as reserving one range of nonnegative indices for edges and another nonnegative range for nodes. An embodiment may instead distinguish indices according to a special bit encoding or by addition of a Boolean column or other flag);
wherein a value of each node is represented by a function data structure ([0086] FIG. 6 depicts tabular data structures for encoding a directed acyclic graph. In the lower right of FIG. 6. is the graph. The graph has nodes 1-4, which are vertices. The graph also has edges 1-7. In the lower left of FIG. 6 is the node table. Each row of the node table encodes a node. The # column of the node table is an implied column of node indexes. In the upper left of FIG. 6 is the edge table. Each row of the edge table encodes an edge. The # column of the edge table is an implied column of edge indexes);
wherein each vertex in the function data structure has a method solve that evaluates the vertex ([0066] Each edge has a signed numeric weight. FIG. 1 depicts edge thickness according to edge weight. For example, edge 132 is shown thicker than edge 131 because edge 132 has more weight. During training a stimulus, such as a test pattern, is applied to a first layer of neural network 110, such that each vertex of the first layer receives a signed numeric value. The value of the vertex is emitted along each edge that originates at the vertex. Each edge scales this value according to the weight of the edge and then transmits the result to a vertex in the next layer. Many edges may terminate at a vertex. That vertex sums the values delivered by those edges, applies an activation function, and then transmits the result to edges that it originates);
pass a graph of the function data structure corresponding to the output node to an optimizer that optimizes an objective while satisfying one or more constraints ([0071] As edge weights are intelligently adjusted, the value yielded by objective function 150 approaches some constant limit that represents perfect accuracy. However, this approaching occurs gradually, for which computer 100 may calculate a gradient of objective function 150. Gradual approaching occurs because training entails repetition by iteration. Each iteration has three phases. The first phase is sparsification; [0072] The second phase is a forward-backward pass over the graph. During the forward-backward pass, computer 100 calculates a value of and a gradient of the objective function on the full graph, and calculates the Hessian matrix 140 on the sparsified or reduced graph. The elements of sparse Hessian matrix 140 are coefficients calculated as partial second derivatives of edge weights. Calculation of sparse Hessian matrix 140 during an iteration is based on sparse Hessian matrix 140 of the previous iteration. As sparsification removes edges from the graph, the graph becomes sparser. This makes the Hessian matrix 140 sparser, such that more coefficients of sparse Hessian matrix 140 become zero, with zero representing a removed edge. Computer 100 may store sparse Hessian matrix 140 in a format optimized for a sparse matrix; [0073] The third phase of each iteration entails solving a quasi-Newton method of optimization based on sparse Hessian matrix 140 and the value of and the gradient of objective function 150. This solving calculates adjustments to edge weights, which improves the accuracy of neural network 110. Quasi-Newton methods boost efficiency by avoiding fully calculating a Hessian matrix every iteration. Instead, quasi-Newton methods incrementally update a reusable Hessian matrix based on calculated gradients; Fig. 9; [0121] Second phase 904 refines the results of first phase 902 to improve the connectivity of each node. Second phase 904 emphases precision. Second phase 904 iterates over all nodes. At each node, the five sequential steps are performed; [0122] First phase 902 may have removed too many or too few input edges or output edges of the current node. An implementation may define an ideal input count and a minimum output count as constants to constrain fan-in and fan-out of edges at a node. Likewise, an implementation may define an ideal input weight to compare against the current input weight of a node. Upon each node of the graph, the steps shown in the flowchart of FIG. 12 are performed to accomplish second phase 904).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of tabular data structures for encoding a directed acyclic graph as suggested in Golovashkin into Le and RAVISHANKAR’s system because both of these systems are addressing optimization on directed acyclic graphs. This modification would have been motivated by the desire for improving the accuracy of neural network (Golovashkin, [0073]).
Regarding independent claim 11, it is a system claim that described in one or more of in claim 10. Therefore, it is rejected for the same reason as claim 10 above. Le further teaches wherein the logic circuitry comprises processing circuitry, memory coupled with the processing circuitry, a communications interface coupled with the processing circuitry, and data storage coupled with the processing circuitry (Fig. 2; [0026] As shown in FIG. 2, the information processing system 100 includes an input unit 110 that receives the input data to be processed, a processer 120 processing the input data, an output unit 130 outputting a processing result, and a storage 140 storing parameters; [0070] Referring to FIG. 9, there is shown an example of a hardware configuration of the information processing system 100. As shown in the figure, the information processing system 100 may include a central processing unit (CPU) 91, a main memory 92 connected to the CPU 91 via a motherboard (M/B) chip set 93, and a display driver 94 connected to the CPU 91 via the same M/B chip set 93. A network interface 96, a magnetic disk device 97, an audio driver 98, and a keyboard/mouse 99 are also connected to the M/B chip set 93 via a bridge circuit 95), wherein the processing circuitry comprises one or more processors residing in one or more servers ([0027] The processor 120 may include a tree-based convolutional (TBC) layer processor 121 and a fully connected layer (FCL) processor 122; [0073] Note that the information processing system 100 may be configured by a single computer. Alternatively, the information processing system 100 may be distributed in multiple computers. Further, a part of the function of the information processing system 100 may be performed by servers on the network, such as a cloud server), wherein the memory comprises memory in the one or more servers, and the data storage comprises data storage residing in or coupled with the server, wherein the data storage further comprises data storage elements residing in other servers coupled with the one or more servers ([0076] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire; [0077] Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device), wherein the memory comprises code executable by the processing circuitry, wherein the code is distributed in whole or in part between memory in one or more of the one or more servers and/or residing in the data storage ([0078] Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention).
Regarding independent claim 12, it is a medium claim that perform operations, the operations to perform the functionality described in claim 10. Therefore, it is rejected for the same reason as claim 10 above. Le further teaches a non-transitory storage medium containing instructions, which when executed by a processor, cause the processor to perform operations ([0027] The processor 120 may include a tree-based convolutional (TBC) layer processor 121 and a fully connected layer (FCL) processor 122; [0076] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device; [0080] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks).
Claims 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sawada et al. (hereinafter Sawada), US 20210312305 A1, in view of Golovashkin US 20170046614 A1.
Regarding independent claim 13, Sawada teaches an apparatus (Fig. 18, 12; [0090]) comprising:
memory (Fig. 18, 28; [0090]); and
logic circuitry coupled with the memory to (Fig. 18, 16; [0090])
accept as arguments to a function evaluateNode a specified layer i (with input layer being I=0 and output layer being I=# of layers−1) and a node within that layer j ([0025] A neural network is a collection of one or more neurons. A neural network is often divided into groups of neurons called layers. A layer is a collection of one or more neurons that all receive input from the same layers and all send output to the same layers, and typically perform a similar function. An input layer is a layer that receives input from a source outside the neural network. An output layer is a layer that sends output to a target outside the neural network. All other layers are intermediate processing layers)
for nodes in the input layer, call solve to evaluate the nodes on a graph corresponding to specified input node j and return result as the current node's value ([0027] Each neural network layer is associated with a parameter tensor V, weight tensor W, input data tensor X, output data tensor Y, and intermediate data tensor Z. The parameter tensor contains all of the parameters that control neuron activation functions a in the layer. The weight tensor contains all of the weights that connect inputs to the layer. The input data tensor contains all of the data that the layer consumes as input); and
otherwise, assign value 0 to variable sum and for each node in a prior layer (represented by numeric index k):
call evaluateNode, passing i−1 for the layer and k for the node, to determine a result of evaluation for a prior node ([0034] With reference now to FIG. 1, a neural core according to embodiments of the present disclosure is depicted. A neural core 100 is a tileable computational unit that computes one block of an output tensor. A neural core 100 has M inputs and N outputs. In various embodiments, M=N)
evaluate multiplication of a prior call to evaluateNode by a weight between a current node and a node in the prior layer, ωijk in array ω ([0034] To compute an output tensor block, a neural core multiplies an M×1 input tensor block 101 with an M×N weight tensor block 102);
assign addition of a product of the multiplication and a current value of a variable sum, to the variable sum; assign addition of the bias and the current value of the variable sum, to the variable sum ([0034] accumulates the products into weighted sums that are stored in a 1×N intermediate tensor block 103));
evaluate an activation function on variable sum, as required by an optimizer that optimizes an objective while satisfying one or more constraints (or limit analysis), either by calling solve to evaluate nodes on a graph equivalent to the activation function, or embedding the corresponding logic within a Neural Network vertex itself; and return a value of evaluation of the activation function as current node's value ([0034] A O×N parameter tensor block contains the O parameters that specify each of the N neuron activation functions that are applied to the intermediate tensor block 103 to produce a 1×N output tensor block 105).
Sawada does not explicitly teach
have a solve method of the Neural Network vertex call evaluateNode, passing the output layer (i=# of layers−1), and the particular output node to evaluate (j); and
pass the Neural Network vertex to the optimizer, if it is to be used as an objective function; or pass a comparison vertex with children being the Neural Network vertex and a graph representing a passing value, if it is to be used as a constraint to the optimizer, or if it is to be passed to a limit analyzer.
However, in the same field of endeavor, Golovashkin teaches
have a solve method of the Neural Network vertex call evaluateNode, passing the output layer (i=# of layers−1), and a particular output node to evaluate (j) ([0071] As edge weights are intelligently adjusted, the value yielded by objective function 150 approaches some constant limit that represents perfect accuracy. However, this approaching occurs gradually, for which computer 100 may calculate a gradient of objective function 150. Gradual approaching occurs because training entails repetition by iteration); and
pass the Neural Network vertex to the optimizer, if it is to be used as an objective function; or pass a comparison vertex with children being the Neural Network vertex and a graph representing a passing value, if it is to be used as a constraint to the optimizer, or if it is to be passed to a limit analyzer ([0071] Each iteration has three phases. The first phase is sparsification; [0072] The second phase is a forward-backward pass over the graph. During the forward-backward pass, computer 100 calculates a value of and a gradient of the objective function on the full graph, and calculates the Hessian matrix 140 on the sparsified or reduced graph. The elements of sparse Hessian matrix 140 are coefficients calculated as partial second derivatives of edge weights. Calculation of sparse Hessian matrix 140 during an iteration is based on sparse Hessian matrix 140 of the previous iteration. As sparsification removes edges from the graph, the graph becomes sparser. This makes the Hessian matrix 140 sparser, such that more coefficients of sparse Hessian matrix 140 become zero, with zero representing a removed edge. Computer 100 may store sparse Hessian matrix 140 in a format optimized for a sparse matrix; [0073] The third phase of each iteration entails solving a quasi-Newton method of optimization based on sparse Hessian matrix 140 and the value of and the gradient of objective function 150. This solving calculates adjustments to edge weights, which improves the accuracy of neural network 110. Quasi-Newton methods boost efficiency by avoiding fully calculating a Hessian matrix every iteration. Instead, quasi-Newton methods incrementally update a reusable Hessian matrix based on calculated gradients).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of quantifying the accuracy of neural network according to objective function as suggested in Golovashkin into Sawada’s system because both of these systems are addressing optimization on directed acyclic graphs. This modification would have been motivated by the desire for improving the accuracy of neural network (Golovashkin, [0073]).
Regarding independent claim 14, it is a system claim that described in one or more of in claim 13. Therefore, it is rejected for the same reason as claim 13 above. Golovashkin further teaches wherein the logic circuitry comprises processing circuitry, memory coupled with the processing circuitry, a communications interface coupled with the processing circuitry, and data storage coupled with the processing circuitry, wherein the processing circuitry comprises one or more processors residing in one or more servers, ([0090] As shown in FIG. 18, computer system/server 12 in computing node 10 is shown in the form of a general-purpose computing device. The components of computer system/server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including system memory 28 to processor 16) wherein the memory comprises memory in the one or more servers, and the data storage comprises data storage residing in or coupled with the server, wherein the data storage further comprises data storage elements residing in other servers coupled with the one or more servers ([0094] System memory 28 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and/or cache memory 32. Computer system/server 12 may further include other removable/non-removable, volatile/non-volatile computer system storage media), wherein the memory comprises code executable by the processing circuitry, wherein the code is distributed in whole or in part between memory in one or more of the one or more servers and/or residing in the data storage ([0097] The present disclosure may be embodied as a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure; [0098] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device; [0102] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks).
Regarding independent claim 15, it is a medium claim that perform operations, the operations to perform the functionality described in claim 13. Therefore, it is rejected for the same reason as claim 13 above. Golovashkin further teaches a non-transitory storage medium containing instructions, which when executed by a processor, cause the processor to perform operations ([0097] The present disclosure may be embodied as a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure; [0098] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device; [0102] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks).
Regarding independent claim 16, Sawada teaches an apparatus (Fig. 18, 12; [0090]) comprising:
memory (Fig. 18, 28; [0090]); and
logic circuitry coupled with the memory to (Fig. 18, 16; [0090])
prepare two arrays of intermediate results, with lengths equal to a maximum number of nodes in a layer, referred to as currResults and priorResults (Fig. 1, 105, 103); and
for each layer in a neural network (represented by numeric index i, with an input layer being layer i=0 and the output layer being i=# of layers−1) ([0025] A neural network is a collection of one or more neurons. A neural network is often divided into groups of neurons called layers. A layer is a collection of one or more neurons that all receive input from the same layers and all send output to the same layers, and typically perform a similar function. An input layer is a layer that receives input from a source outside the neural network. An output layer is a layer that sends output to a target outside the neural network. All other layers are intermediate processing layers);
for each node in that layer (represented by numeric index j):
if the layer is the input layer (when i=0); then
call solve on a graph corresponding to a current input node j to evaluate nodes of the graph; and
store a result in currResultsj ([0027] Each neural network layer is associated with a parameter tensor V, weight tensor W, input data tensor X, output data tensor Y, and intermediate data tensor Z. The parameter tensor contains all of the parameters that control neuron activation functions a in the layer. The weight tensor contains all of the weights that connect inputs to the layer. The input data tensor contains all of the data that the layer consumes as input);
if the layer is the output layer and j is not equal to an index of a desired output node being evaluated continue to a next node without doing any work ([0025] An output layer is a layer that sends output to a target outside the neural network);
otherwise assign value 0 to variable sum;
for each node in a prior layer (represented by numeric index k), perform a multiplication of priorResultsk by weight ωijk and add a product to variable sum ([0034] With reference now to FIG. 1, a neural core according to embodiments of the present disclosure is depicted. A neural core 100 is a tileable computational unit that computes one block of an output tensor. A neural core 100 has M inputs and N outputs. In various embodiments, M=N. To compute an output tensor block, a neural core multiplies an M×1 input tensor block 101 with an M×N weight tensor block 102 and accumulates the products into weighted sums that are stored in a 1×N intermediate tensor block 103);
add a bias to variable sum ([0032] the weighed sum of inputs is adjusted by a bias b);
evaluate an activation function on variable sum, as required by an optimizer that optimizes ab objective while satisfying one or more constraints (or limit analysis), either by calling solve on a graph to evaluate nodes of the graph equivalent to the activation function, or embedding the corresponding logic within the NeuralNetwork vertex itself; store a result of that evaluation of the activation function in currResultsj ([0034] A O×N parameter tensor block contains the O parameters that specify each of the N neuron activation functions that are applied to the intermediate tensor block 103 to produce a 1×N output tensor block 105);
swap currResults and priorResults with each other; return the result stored in priorResults at an index of the desired output node ([0038] Referring to FIG. 2, an exemplary Inference Processing Unit (IPU) is illustrated according to embodiments of the present disclosure. IPU 200 includes a memory 201 for the neural network model. As described above, the neural network model may include the synapse weights for a neural network to be computed. IPU 200 includes an activation memory 202, which may be transient. Activation memory 202 may be divided into input and output regions, and stores neuron activations for processing. IPU 200 includes a neural computation unit 203, which is loaded with a neural network model from model memory 201. Input activations are provided from activation memory 202 in advance of each computation step. Outputs from neural computation unit 203 are written back to activation memory 202 for processing on the same or another neural computation unit).
Sawada does not explicitly teach
pass the graph corresponding to the output node to the optimizer as an objective function;
or use the graph corresponding to the output node as a child vertex of a comparison vertex, with the other vertex of a comparison graph corresponding to a “passing” value, and pass the comparison graph to the optimizer as a constraint, or to a limit analyzer for solving.
However, in the same field of endeavor, Golovashkin teaches
pass the graph corresponding to the output node to the optimizer as an objective function; or use the graph corresponding to the output node as a child vertex of a comparison vertex, with the other vertex of a comparison graph corresponding to a “passing” value, and pass the comparison graph to the optimizer as a constraint, or to a limit analyzer for solving ([0071] As edge weights are intelligently adjusted, the value yielded by objective function 150 approaches some constant limit that represents perfect accuracy. However, this approaching occurs gradually, for which computer 100 may calculate a gradient of objective function 150. Gradual approaching occurs because training entails repetition by iteration. Each iteration has three phases. The first phase is sparsification; [0072] The second phase is a forward-backward pass over the graph. During the forward-backward pass, computer 100 calculates a value of and a gradient of the objective function on the full graph, and calculates the Hessian matrix 140 on the sparsified or reduced graph. The elements of sparse Hessian matrix 140 are coefficients calculated as partial second derivatives of edge weights. Calculation of sparse Hessian matrix 140 during an iteration is based on sparse Hessian matrix 140 of the previous iteration. As sparsification removes edges from the graph, the graph becomes sparser. This makes the Hessian matrix 140 sparser, such that more coefficients of sparse Hessian matrix 140 become zero, with zero representing a removed edge. Computer 100 may store sparse Hessian matrix 140 in a format optimized for a sparse matrix; [0073] The third phase of each iteration entails solving a quasi-Newton method of optimization based on sparse Hessian matrix 140 and the value of and the gradient of objective function 150. This solving calculates adjustments to edge weights, which improves the accuracy of neural network 110. Quasi-Newton methods boost efficiency by avoiding fully calculating a Hessian matrix every iteration. Instead, quasi-Newton methods incrementally update a reusable Hessian matrix based on calculated gradients).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of quantifying the accuracy of neural network according to objective function as suggested in Golovashkin into Sawada’s system because both of these systems are addressing optimization on directed acyclic graphs. This modification would have been motivated by the desire for improving the accuracy of neural network (Golovashkin, [0073]).
Regarding independent claim 17, it is a system claim that described in one or more of in claim 16. Therefore, it is rejected for the same reason as claim 16 above. Golovashkin further teaches wherein the logic circuitry comprises processing circuitry, memory coupled with the processing circuitry, a communications interface coupled with the processing circuitry, and data storage coupled with the processing circuitry, wherein the processing circuitry comprises one or more processors residing in one or more servers ([0090] As shown in FIG. 18, computer system/server 12 in computing node 10 is shown in the form of a general-purpose computing device. The components of computer system/server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including system memory 28 to processor 16) wherein the memory comprises memory in the one or more servers, and the data storage comprises data storage residing in or coupled with the server, wherein the data storage further comprises data storage elements residing in other servers coupled with the one or more servers ([0094] System memory 28 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and/or cache memory 32. Computer system/server 12 may further include other removable/non-removable, volatile/non-volatile computer system storage media), wherein the memory comprises code executable by the processing circuitry, wherein the code is distributed in whole or in part between memory in one or more of the one or more servers and/or residing in the data storage ([0097] The present disclosure may be embodied as a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure; [0098] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device; [0102] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks).
Regarding independent claim 18, it is a medium claim that perform operations, the operations to perform the functionality described in claim 16. Therefore, it is rejected for the same reason as claim 16 above. Golovashkin further teaches a non-transitory storage medium containing instructions, which when executed by a processor, cause the processor to perform operations ([0097] The present disclosure may be embodied as a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure; [0098] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device; [0102] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks).
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered. Each of applicant’s remarks is set forth, followed by examiner’s response.
(1) Regarding 35 U.S.C. 101 rejections, Applicant’s amendments to the claims have overcome the rejections. Rejections under 35 U.S.C 101 to claims 1-6 and 8-18 are withdrawn.
(2) Applicant’s amendments to the claims have overcome the objection and the 112(b) rejections previously set forth in the previous Office Action.
(3) Regarding 103 rejections on claims 1-12, Applicant argues Claim 1 recites "for each output node to be used as a constraint, or to be solved for limit analysis, construct a comparison vertex against a "passing" value, using the output node's graph and the passing value as the children; and pass a graph corresponding to the output node to an optimizer that optimizes an objective while satisfying one or more constraints; and/or for each output node to be used as an objective function, pass a graph corresponding to the output node to an optimizer." Le, Ravishankar, and Golovashkin fail to teach or suggest these claim features. The Examiner acknowledges that le and Ravishankar do not teach or suggest these claim features. The Examiner relies on Golovashkin for teaching these features (see Office Action, page 27). However, Golovashkin describes comparing actual versus expected behavior for training error and using gradients and Hessians for training optimization. Golovashkin does not teach or suggest constructing a solver constraint node that compares a neural network output to a fixed "passing" threshold for a separate optimizer or limit analyzer.
As to point (3), Examiner respectfully disagrees. Examiner notes that the claims place no limitations on what a comparison vertex and a "passing" value are and how to construct a comparison vertex against a "passing" value. Thus, Golovashkin’s teaching of comparing actual versus expected behavior for training error and using gradients and Hessians for training optimization ([0070]-[0073]) in combination with is considered within the broadest reasonable interpretation of the claim.
(4) Regarding 103 rejections on claim 10, Applicant argues Claim 10 requires creating a new neural network type of vertex having (i) a child vertex per input node, (ii) a three-dimensional array of weights indexed by layer/node/prior-node weight, (iii) an output-node index to evaluate, (iv) each node value represented by a function data structure, and (v) each vertex having a solve method that evaluates the vertex, then passing the resulting graph for the output node to the optimizer. Golovashkin's edge and node tables are designed for efficient sparse training and sparsification bookkeeping (arrays of edges/vertices, linked lists sorted by weight). The edge and node tables are not designed for a "new neural network vertex" abstraction that encapsulates layered evaluation via a 3D weight tensor/array and exposes a per-vertex solve method to an external optimizer as a plug-in function node, as claimed. The claimed neural network type of vertex" is a compositional data structure that encapsulates an entire trained neural network as a single evaluable node within a larger optimization problem's function graph. This allows the optimizer to treat the neural network as a black-box function with defined inputs (child vertices) and outputs (evaluated via the solve method). This is not taught or suggested by Golovashkin.
As to point (4), Examiner respectfully disagrees. Golovashkin depicts the graph in Fig. 6 as a new neural network type of vertex. The graph has nodes, which are vertices. The graph also has edges. Each row of the node table encodes a node. Each row of the edge table encodes an edge. The edge table and the node table also encode two indirect circular linked lists for each node. One list contains edges that originate at a node. The other list contains edges that terminate at the node. Each link of these lists comprises a row index, of either the edge table or the node table, that designates an edge or node. Each list is sorted by edge weight, either ascending or descending. Each node is the head of two lists, which are linked into by the edge-in and edge-out columns of the node table. The edge-in column has an edge index of an edge, with the least value of weight, that terminates at the node. Edges of a directed acyclic graph are stored in an edge array having a row for each edge. Each edge originates at a vertex of the graph and terminates at another vertex. Each edge has a weight, a next input index, and a next output index ([0086]-[0088]). Thus Golovashkin is considered to teach "for each output node to be used as a constraint, or to be solved for limit analysis, construct a comparison vertex against a "passing" value, using the output node's graph and the passing value as the children; and pass a graph corresponding to the output node to an optimizer that optimizes an objective while satisfying one or more constraints; and/or for each output node to be used as an objective function, pass a graph corresponding to the output node to an optimizer."
(5) Regarding 103 rejections on claims 13-18, Applicant alleges The Examiner acknowledges that Sawada does not teach or suggest "have a solve method of the Neural Network vertex call evaluateNode, passing the output layer (i = # of layers - 1), and a particular output node to evaluate (j)," or "pass the Neural Network vertex to the optimizer, if it is to be used as an objective function; or pass a comparison
vertex with children being the Neural Network vertex and a graph representing the passing value, if it is to be used as a constraint to an optimizer, or if it is to be passed to a limit analyzer," as recited in claim 13. Golovashkin also does not teach or suggest these claim limitations. Golovashkin's optimizer is for training weights internal to the neural network, not an optimizer consuming the neural network output as a constraint or objective as required by claim 13.
As to point (5), Examiner respectfully disagrees. Golovashkin teaches training entails repetition by iteration where edge weights are intelligently adjusted. Each iteration has three phases. The first phase is sparsification. The second phase is a forward-backward pass over the graph and the third phase of each iteration entails solving a quasi-Newton method of optimization based on sparse Hessian matrix and the value of and the gradient of objective function ([0070]-[0072]). Thus, Golovashkin is considered to teach "have a solve method of the Neural Network vertex call evaluateNode, passing the output layer (i = # of layers - 1), and a particular output node to evaluate (j)," or "pass the Neural Network vertex to the optimizer, if it is to be used as an objective function; or pass a comparison
vertex with children being the Neural Network vertex and a graph representing the passing value, if it is to be used as a constraint to an optimizer, or if it is to be passed to a limit analyzer," as recited in claim 13.
(6) Regarding 103 rejections on claim 16, Applicant alleges Golovashkin and Sawada do not teach or suggest constructing a neural network vertex object with a solve method and passing that vertex (or a comparison vertex containing it) to an external optimizer as claim 16 requires. Golovashkin's optimizer is optimizing the weights of the neural network itself through training and is consuming the neural network's output as a constraint or objective in a separate optimization problem.
As to point (6), Examiner notes that claim 16 does not recite constructing a neural network vertex object with a solve method and passing that vertex (or a comparison vertex containing it) to an external optimizer. Golovashkin teaches training entails repetition by iteration where edge weights are intelligently adjusted. Each iteration has three phases. The first phase is sparsification. The second phase is a forward-backward pass over the graph and the third phase of each iteration entails solving a quasi-Newton method of optimization based on sparse Hessian matrix and the value of and the gradient of objective function ([0070]-[0072]). Thus, Golovashkin is considered to teach “pass the graph corresponding to the output node to the optimizer as an objective function; or use the graph corresponding to the output node as a child vertex of a comparison vertex, with the other vertex of the comparison graph corresponding to a “passing” value, and pass the comparison graph to the optimizer as a constraint, or to a limit analyzer for solving”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Xiao et al. (US 20080154816 A1) discloses designing a neural network involves specifying the number and arrangement of nodes, and the weights that characterize the interconnection between nodes.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY P HOANG whose telephone number is (469)295-9134. The examiner can normally be reached M-TH 8:30-5:00PM.
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/AMY P HOANG/ Examiner, Art Unit 2143
/JENNIFER N WELCH/ Supervisory Patent Examiner, Art Unit 2143
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