DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 02 December 2022.
Claims 1-20 are pending and have been presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7, 8, 10, 11, 13, 15, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over PRATHER (U.S. Patent Application Publication #2025/0348238) in view of PATRIARCA (U.S. Patent Application Publication #2022/0308796).
1. PRATHER discloses A semiconductor apparatus comprising a plurality of integrated circuitry (IC) components, including: a host input/output (I/O) interface coupled to a host-side I/O port (see [0032]: memory buffer IC includes a logic buffer connected to the host through the host bus); a power management component (see [0028]: memory buffer IC includes a PMIC to manage power); memory, comprising at least non-volatile memory in which firmware instructions are stored; at least one processing element on which the firmware instructions are configured to be executed (see PATRIARCA below); and a device-side I/O interface and router coupled to a plurality of device-side I/O ports (see [0025]: memory buffer IC distributes signals over the memory bus), wherein the semiconductor apparatus is configured to be mounted on a memory module having a plurality of Dynamic Random Access Memory (DRAM) devices that are coupled to the device-side ports (see [0027]: the memory devices include an array of DRAM’s that are coupled to the memory buffer IC; figure 3: elements 220, 240 and 250: the integrated circuit 240 is located on the memory module 220 and is coupled with the memory devices 250) and wherein execution of the firmware instructions on the at least one processing element enables the semiconductor apparatus to facilitate communication between a host in which the memory module is installed and the plurality of DRAM devices using sideband communication (see PATRIARCA below).
PATRIARCA discloses the following limitations that are not disclosed by PRATHER: memory, comprising at least non-volatile memory in which firmware instructions are stored (see [0055]: flash NOR to store firmware for the management unit); at least one processing element on which the firmware instructions are configured to be executed (see [0061]-[0062]: memory controller implemented with processing logic that includes hardware – equivalent to the claimed processing element – and microcode – equivalent to the claimed firmware instructions; the microcode storage in the processing logic would be the non-volatile memory); and wherein execution of the firmware instructions on the at least one processing element enables the semiconductor apparatus to facilitate communication between a host in which the memory module is installed and the plurality of DRAM devices using sideband communication (see [0054]: memory controller includes a management unit to recognize and manage sideband communications; [0018]: management of sideband communications between the host and the memory by the controller). PATRIARCA discloses a similar controller arrangement as PRATHER. The memory controller of PATRIARCA includes a front end interface to communicate with a host (see [0040]), a central controller portion to implement the functionality of the controller (see [0042]-[0043], and a backend interface to communicate with DRAM memory (see [0030]). A combination of PRATHER and PATRIARCA would result in the memory controller functionality of PATRIARCA being integrated into the memory buffer IC of PRATHER. Adding the functionality of PATRIARCA to PRATHER would allow the controller to manage sideband communications between the host and the memory devices to better protect the data (see PATRIARCA [0018]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to include a processing unit with firmware to enable sideband communications, as disclosed by PATRIARCA. One of ordinary skill in the art would have been motivated to make such a modification to better protect data sent by a host to a memory device, as taught by PATRIARCA. PRATHER and PATRIARCA are analogous/in the same field of endeavor as both references are directed to controllers that manage DRAM devices.
2. The semiconductor apparatus of claim 1, wherein the power management component is configured to receive power from power input lines on the memory module and manage power supplied to circuitry and components on the semiconductor apparatus and circuitry and components on the memory module (see PRATHER [0019]: power supply terminals; [0033]-[0034]: PMIC includes configuration registers to allow the PMIC module to provide the appropriate power signals to the arrays of memory devices).
3. The semiconductor apparatus of claim 1, wherein the memory module includes a plurality of data buffers (DBs) that are coupled to one or more of the device-side I/O ports when the semiconductor apparatus is mounted to the memory module (see PRATHER [0032]: buffer IC implements FIFO or LIFO buffering for data between the host and the memory devices), and wherein execution of the firmware instructions on the at least one processing element enables the semiconductor apparatus to facilitate communication between the host and the plurality of DBs using sideband communication (see PATRIARCA [0018]: sideband communication between host and controller, which includes the data buffers).
4. The semiconductor apparatus of claim 1, further comprising at least one control register (see PRATHER [0033]: registers to configure the PMIC).
5. The semiconductor apparatus of claim 1, wherein the sideband communication employs I2C or I3C buses (see PATRIARCA [0055]: I2C protocol).
7. The semiconductor apparatus of claim 1, wherein a portion of the memory is configured to implement at least one of a scratchpad and a mailbox (see PATRIARCA [0042]: portion of the memory can be a cache memory, the cache would correlate with a scratchpad since data in cache can be temporary).
8. The semiconductor apparatus of claim 1, wherein a portion of the memory includes volatile memory (see PRATHER [0027]: volatile memory such as DRAM).
10. The semiconductor apparatus of claim 1, wherein the device-side I/O interface and router comprises a proxy controller and router employing an I2C or I3C interface configured to route sideband signal over I2C or I3C bus lines coupling the DRAM devices to the device- side ports (see PATRIARCA [0055]: I2C protocol, I2C allows for communication between devices, the management unit implements the I2C protocol and therefore the management would be considered the proxy controller).
11. PRATHER discloses A memory module, comprising: a printed circuit board (PCB) on which a plurality of components and circuitry are mounted and having wiring interconnecting the plurality of components and circuitry (see [0027]: printed circuit board package with memory buffer IC and memory devices); a plurality of Dynamic Random Access Memory (DRAM) devices (see [0027]: DRAM memory devices); a plurality of Data Buffers (DBs), coupled to the plurality of DRAM devices (see [0032]: FIFO or LIFO buffering implemented by the memory buffer IC to manage data transmission between the host and the DRAM devices); a memory module management device, having a power management component configured to manage power provided to components on the memory module (see [0033]: memory buffer IC includes a PMIC, the PMIC includes a configuration register to cause the PMIC to provide the appropriate power signals to the device), having an input/output (I/O) interface coupled to host side port (see [0032]: memory buffer IC includes a logic buffer connected to the host through the host bus) connected to host sideband signal lines on the memory module (see PATRIARCA below), and having an I/O interface and router coupled to a plurality of device-side ports to which the plurality of DRAM devices and DBs are coupled via the wiring in the PCB (see [0027]: the memory devices include an array of DRAM’s that are coupled to the memory buffer IC; figure 3: elements 220, 240 and 250: the integrated circuit 240 is located on the memory module 220 and is coupled with the memory devices 250), wherein the memory module management device further comprises embedded logic configured to facilitate communication between a host in which the memory module is installed, the plurality of DRAM devices, and the plurality of DBs using sideband communication.
PATRIARCA discloses the following limitations that are not disclosed by PRATHER: host sideband signal lines on the memory module (see [0061]: I/O bus to manage out-of-band data, out-of-band data would be equivalent to sideband) and wherein the memory module management device further comprises embedded logic configured to facilitate communication between a host in which the memory module is installed, the plurality of DRAM devices, and the plurality of DBs using sideband communication (see [0061]-[0062]: memory controller implemented with processing logic that includes hardware – equivalent to the claimed embedded logic – and microcode – equivalent to the claimed firmware instructions; [0054]: memory controller includes a management unit to recognize and manage sideband communications; [0018]: management of sideband communications between the host and the memory by the controller). PATRIARCA discloses a similar controller arrangement as PRATHER. The memory controller of PATRIARCA includes a front end interface to communicate with a host (see [0040]), a central controller portion to implement the functionality of the controller (see [0042]-[0043], and a backend interface to communicate with DRAM memory (see [0030]). A combination of PRATHER and PATRIARCA would result in the memory controller functionality of PATRIARCA being integrated into the memory buffer IC of PRATHER. Adding the functionality of PATRIARCA to PRATHER would allow the controller to manage sideband communications between the host and the memory devices to better protect the data (see PATRIARCA [0018]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to include a processing unit with firmware to enable sideband communications, as disclosed by PATRIARCA. One of ordinary skill in the art would have been motivated to make such a modification to better protect data sent by a host to a memory device, as taught by PATRIARCA. PRATHER and PATRIARCA are analogous/in the same field of endeavor as both references are directed to controllers that manage DRAM devices.
13. The memory module of claim 11, wherein the embedded logic comprises a microcontroller on which firmware instructions are executed (see PATRIARCA [0055]: firmware executing on management unit; [0062]: hardware such as a processing device, circuity, dedicated logic, programmable logic, etc. – these elements would be equivalent to the claimed microcontroller).
15. The memory module of claim 11, further comprising one or more temperature sensors that are coupled to one or more device-side ports on the memory management module, wherein the memory module management device is further configured to read the temperature sensors and provide corresponding temperature data to the host (see PRATHER [0036]: temp sensors provided near the end of each memory bank, temp data is output to the host).
16. PRATHER discloses A method implemented by a memory module management device on a memory module installed in a host having a plurality of Dynamic Random Access Memory (DRAM) devices (see [0027]: memory buffer IC on a printed circuit board with DRAM devices), the memory module management device having a power management component configured to manage power provided to components on the memory module (see [0028]: memory buffer IC includes a PMIC to manage power), having an input/output I/O) interface coupled to host side port (see [0032]: memory buffer IC includes a logic buffer connected to the host through the host bus) connected to host sideband signal lines on the memory module (see PATRIARCA below), and having an I/O interface and router coupled to a plurality of device-side ports to which the plurality of DRAM devices are coupled via the wiring in the memory module (see [0027]: the memory devices include an array of DRAM’s that are coupled to the memory buffer IC; figure 3: elements 220, 240 and 250: the integrated circuit 240 is located on the memory module 220 and is coupled with the memory devices 250), the method comprising: managing power provided to components and circuitry on the memory module including the DRAM devices via the power management component (see [0019]: power supply terminals; [0033]-[0034]: PMIC includes configuration registers to allow the PMIC module to provide the appropriate power signals to the arrays of memory devices); and facilitating communication between the host and the plurality of DRAM devices using the memory module management device (see [0032]: communication between the host and the DRAM is facilitated by the memory buffer IC).
PATRIARCA discloses the following limitations that are not disclosed by PRATHER: a host side port connected to host sideband signal lines on the memory module (see [0061]: I/O bus to manage out-of-band data, out-of-band data would be equivalent to sideband; [0054]: memory controller includes a management unit to recognize and manage sideband communications; [0018]: management of sideband communications between the host and the memory by the controller). PATRIARCA discloses a similar controller arrangement as PRATHER. The memory controller of PATRIARCA includes a front end interface to communicate with a host (see [0040]), a central controller portion to implement the functionality of the controller (see [0042]-[0043], and a backend interface to communicate with DRAM memory (see [0030]). A combination of PRATHER and PATRIARCA would result in the memory controller functionality of PATRIARCA being integrated into the memory buffer IC of PRATHER. Adding the functionality of PATRIARCA to PRATHER would allow the controller to manage sideband communications between the host and the memory devices to better protect the data (see PATRIARCA [0018]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to include a processing unit with firmware to enable sideband communications, as disclosed by PATRIARCA. One of ordinary skill in the art would have been motivated to make such a modification to better protect data sent by a host to a memory device, as taught by PATRIARCA. PRATHER and PATRIARCA are analogous/in the same field of endeavor as both references are directed to controllers that manage DRAM devices.
18. The method of claim 16, wherein the memory module includes a plurality of data buffers (DBs) that are coupled to one or more of the device-side I/O ports via wiring in the memory module (see PRATHER [0032]: buffer IC implements FIFO or LIFO buffering for data between the host and the memory devices), further comprising facilitating communication between the host and the plurality of DBs using the memory module management device (see PRATHER [0032]: memory buffer IC facilitate communication between the host and memory device).
Claim(s) 6 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over PRATHER (U.S. Patent Application Publication #2025/0348238) and PATRIARCA (U.S. Patent Application Publication #2022/0308796) as applied to claims 1-5, 7, 8, 10, 11, 13, 15, 16 and 18 above, and further in view of ERICKSON (U.S. Patent Application Publication #2023/0161599).
6. The semiconductor apparatus of claim 1 (see PRATHER above), wherein the sideband communications employ the Management Component Transport Protocol (MCTP) (see ERICKSON below).
ERICKSON discloses the following limitations that are not disclosed by PRATHER: the sideband communications employ the Management Component Transport Protocol (MCTP) (see [0032]: message sent from host to memory interface controller over a sideband link, message is secured with MCTP encapsulation). The use of MCPT allows for secure access to the memory device by the host (see [0033]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to have sideband communication employ MCTP, as disclosed by ERICKSON. One of ordinary skill in the art would have been motivated to make such a modification to allow secure access to the memory system, as taught by ERICKSON. PRATHER and ERICKSON are analogous/in the same field of endeavor as both references are directed to communications with a memory system.
20. The method of claim 16, wherein communication between the host and the plurality of DRAM devices comprises routing sideband signals over I2C or I3C buses (see PATRIARCA [0055]: I2C) using the Management Component Transport Protocol (MCTP) (see ERICKSON below).
ERICKSON discloses the following limitations that are not disclosed by PRATHER: the sideband communications employ the Management Component Transport Protocol (MCTP) (see [0032]: message sent from host to memory interface controller over a sideband link, message is secured with MCTP encapsulation). The use of MCPT allows for secure access to the memory device by the host (see [0033]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to have sideband communication employ MCTP, as disclosed by ERICKSON. One of ordinary skill in the art would have been motivated to make such a modification to allow secure access to the memory system, as taught by ERICKSON. PRATHER and ERICKSON are analogous/in the same field of endeavor as both references are directed to communications with a memory system.
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over PRATHER (U.S. Patent Application Publication #2025/0348238) and PATRIARCA (U.S. Patent Application Publication #2022/0308796) as applied to claims 1-5, 7, 8, 10, 11, 13, 15, 16 and 18 above, and further in view of YOUNG (U.S. Patent Application Publication #2023/0239165).
9. The semiconductor apparatus of claim 1 (see PRATHER above), further comprising an SPDM (Security Protocol and Data Model) Authentication block configured to implement SPDM to authenticate at least a portion of the firmware instructions (see YOUNG below).
YOUNG discloses the following limitations that are not disclosed by PRATHER: an SPDM (Security Protocol and Data Model) Authentication block configured to implement SPDM to authenticate at least a portion of the firmware instructions (see [0051]: SPDM to authenticate a configuration of a device, including firmware). This protocol provides assurances regarding the integrity of instructions used by a device (see [0051]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to use SPDM to authenticate firmware instructions, as disclosed by YOUNG. One of ordinary skill in the art would have been motivated to make such a modification to provide assurances regarding the integrity of instructions used by the device, as taught by YOUNG. PRATHER and YOUNG are analogous/in the same field of endeavor as both references are directed to memory systems.
19. The method of claim 16, wherein the memory module management device includes one of more processing elements on which firmware instructions are executed (see PATRIARCA [0055]: firmware executing on management unit; [0062]: hardware such as a processing device, circuity, dedicated logic, programmable logic, ect. – these elements would be equivalent to the claimed microcontroller), further comprising: employing SPDM (Security Protocol and Data Model) authentication using logic in the memory module management device to authenticate at least a portion of the firmware instructions (see YOUNG below).
YOUNG discloses the following limitations that are not disclosed by PRATHER: an SPDM (Security Protocol and Data Model) Authentication block configured to implement SPDM to authenticate at least a portion of the firmware instructions (see [0051]: SPDM to authenticate a configuration of a device, including firmware). This protocol provides assurances regarding the integrity of instructions used by a device (see [0051]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to use SPDM to authenticate firmware instructions, as disclosed by YOUNG. One of ordinary skill in the art would have been motivated to make such a modification to provide assurances regarding the integrity of instructions used by the device, as taught by YOUNG. PRATHER and YOUNG are analogous/in the same field of endeavor as both references are directed to memory systems.
Claim(s) 12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over PRATHER (U.S. Patent Application Publication #2025/0348238) and PATRIARCA (U.S. Patent Application Publication #2022/0308796) as applied to claims 1-5, 7, 8, 10, 11, 13, 15, 16 and 18 above, and further in view of LESLIE (U.S. Patent Application Publication #2022/0076721).
12. The memory module of claim 11 (see PRATHER above), wherein the DRAM devices are Double Data Rate 6th generation (DDR6) DRAMs (see LESLIE below).
LESLIE discloses the following limitations that are not disclosed by PRATHER: wherein the DRAM devices are Double Data Rate 6th generation (DDR6) DRAMs (see [0103]: DDR6 protocol). The number of memory devices needed depends on the channel width associated with the DIMM. The use of DDR6 provides a full channel width of 80 bits (see [0103]). The use of DDR6 would be a matter of design choice based on the needs to the system. For systems that need a channel width of 80 bits, DDR6 would be appropriate, as taught by LESLIE.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to use DDR6, as disclosed by LESLIE. One of ordinary skill in the art would have been motivated to make such a modification to provide a channel width of 80 bits, as taught by LESLIE. PRATHER and LESLIE are analogous/in the same field of endeavor as both references are directed to DRAM memory systems.
17. The method of claim 16 (see PRATHER above), wherein the DRAM devices Double Data Rate 6th generation (DDR6) DRAMs (see LESLIE below).
LESLIE discloses the following limitations that are not disclosed by PRATHER: wherein the DRAM devices are Double Data Rate 6th generation (DDR6) DRAMs (see [0103]: DDR6 protocol). The number of memory devices needed depends on the channel width associated with the DIMM. The use of DDR6 provides a full channel width of 80 bits (see [0103]). The use of DDR6 would be a matter of design choice based on the needs to the system. For systems that need a channel width of 80 bits, DDR6 would be appropriate, as taught by LESLIE.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to use DDR6, as disclosed by LESLIE. One of ordinary skill in the art would have been motivated to make such a modification to provide a channel width of 80 bits, as taught by LESLIE. PRATHER and LESLIE are analogous/in the same field of endeavor as both references are directed to DRAM memory systems.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over PRATHER (U.S. Patent Application Publication #2025/0348238) and PATRIARCA (U.S. Patent Application Publication #2022/0308796) as applied to claims 1-5, 7, 8, 10, 11, 13, 15, 16 and 18 above, and further in view of HINKLE (U.S. Patent Application Publication #2024/0111454).
14. The memory module of claim 11 (see PRATHER above), further comprising a registered clock device (RCD) that is coupled to a device-side port on the memory management module, wherein the memory module management device further facilitates communication between the host and the RCD (see HINKLE below).
HINKLE discloses the following limitations that are not disclosed by PRATHER above: a registered clock device (RCD) that is coupled to a device-side port on the memory management module (see [0015]: an RCD is a buffer to redrives command and address signals to a DRAM device, therefore, this would be coupled to the device side port), wherein the memory module management device further facilitates communication between the host and the RCD (see [0015]-[0016]: RCD receives signals from the host, therefore there is communication between the host and the RCD). The RCD provides functionality between the host and the DRAM to convert signals and access addresses to direct host accesses to the appropriate memory module (see [0015]-[0016]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify PRATHER to include an RCD, as disclosed by HINKLE. One of ordinary skill in the art would have been motivated to make such a modification to redrive signals to the DRAM and direct accesses to the appropriate DRAM, as taught by HINKLE. PRATHER and HINKLE are analogous/in the same field of endeavor as both references are directed to DRAM memory systems.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached at 571-272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2136