DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 9,300,265), in view of Chung (US 7,030,717).
In regard to Claim 1:
Lee discloses, in Figure 2, a transmitter circuit having an input port (Vi1, Vi2), a first transmission node (B5), a second transmission node (B14), a third transmission node (B40), and a fourth transmission node (B38) and comprising:
a first operational amplifier (234);
a first output stage (202(1-11)) coupled to the first operational amplifier (234);
a first network (232) coupled to the first output stage (202(1-11)) and the first operational amplifier (234);
a first switch group (220) coupled between the first network (232) and the input port (Vi1);
a first impedance matching circuit (230) coupled to the first output stage (220(1-11)), the first transmission node (B5), and the second transmission node (B14);
a second operational amplifier (244);
a second output stage (208(1-4)) coupled to the second operational amplifier (244);
a second network (242) coupled to the second output stage (208(1-4)) and the second operational amplifier (244);
a second switch group (222) coupled between the second network (242) and the input port (Vi2); and
a second impedance matching circuit (240) coupled to the second output stage (208(1-4)), the third transmission node (B40), and the fourth transmission node (B38).
Lee does not disclose a first resistor-capacitor network and a second resistor-capacitor network.
Chung discloses, in Figure 2, a first (232 of Lee above) resistor-capacitor network (3) and a second (242 of Lee above) resistor-capacitor network (3).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the details of the impedance matching circuit taught by Chung with the first and second resistor-capacitor networks taught by Lee, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In regard to Claim 2:
Chung further discloses, in Figure 2, the transmitter circuit of claim 1, wherein the first resistor-capacitor network (232 of Lee) comprises a first resistor-capacitor circuit (upper 31 and 32) and a second resistor-capacitor circuit (lower 31 and 32), and the second resistor-capacitor network (242 of Lee) comprises a third resistor-capacitor circuit (upper 31 and 32) and a fourth resistor-capacitor circuit (lower 31 and 32).
In regard to Claim 5:
Chung further discloses, in Figure 2, the transmitter circuit of claim 1, wherein the first impedance matching circuit (230 of Lee) comprises a first resistor (upper 31) and a second resistor (lower 31), and the second impedance matching circuit (240) comprises a third resistor (upper 31) and a fourth resistor (lower 31).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the details of the impedance matching circuit taught by Chung with the first and second impedance matching circuits taught by Lee, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In regard to Claim 8:
Chung further discloses, in Figure 2, the transmitter circuit of claim 1, wherein the first impedance matching circuit (230 of Lee) and the second impedance matching circuit (240 of Lee) do not comprise any switch (the impedance matching circuit 3 of Chung does not comprise any switch).
Allowable Subject Matter
Claims 3-4 and 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 3:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the first switch group comprises a first switch and a second switch, and the second switch group comprises a third switch and a fourth switch.
In regard to Claim 4:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the input port comprises a first input node and a second input node, and the first switch is coupled between the first input node and the first resistor-capacitor circuit, the second switch is coupled between the second input node and the second resistor-capacitor circuit, the third switch is coupled between the first input node and the third resistor-capacitor circuit, and the fourth switch is coupled between the second input node and the fourth resistor-capacitor circuit.
In regard to Claim 6:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the first resistor is coupled between the first output stage and the first transmission node, the second resistor is coupled between the first output stage and the second transmission node, the third resistor is coupled between the second output stage and the third transmission node, and the fourth resistor is coupled between the second output stage and the fourth transmission node.
In regard to Claim 7:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the transmitter circuit operates in a first mode or a second mode; in the first mode, the first switch group is turned on and the second switch group is turned off; in the second mode, the first switch group is turned off and the second switch group is turned on.
Claims 9-17 are allowed.
In regard to Claim 9:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a common mode feedback (CMFB) circuit; a first switch coupled between the CMFB circuit and the first output stage; and a second switch coupled between the CMFB circuit and the second output stage.
However, Lee et al. (US 9,300,265) discloses, in Figure 2, a transmitter circuit having an input port (Vi1, Vi2), a first transmission node (B5), a second transmission node (B14), a third transmission node (B40), and a fourth transmission node (B38) and comprising: a first operational amplifier (234); a first output stage (202(1-11)) coupled to the first operational amplifier (234); a first network (232) coupled to the first output stage (202(1-11)) and the first operational amplifier (234); a first switch group (220) coupled between the first network (232) and the input port (Vi1); a first impedance matching circuit (230) coupled to the first output stage (220(1-11)), the first transmission node (B5), and the second transmission node (B14); a second operational amplifier (244); a second output stage (208(1-4)) coupled to the second operational amplifier (244); a second network (242) coupled to the second output stage (208(1-4)) and the second operational amplifier (244); a second switch group (222) coupled between the second network (242) and the input port (Vi2); and a second impedance matching circuit (240) coupled to the second output stage (208(1-4)), the third transmission node (B40), and the fourth transmission node (B38).
Chung (US 7,030,717) discloses, in Figure 2, a first (232 of Lee above) resistor-capacitor network (3) and a second (242 of Lee above) resistor-capacitor network (3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gaynor et al. (US 2015/0091776) discloses an antenna switch can connect an antenna to either transmit circuitry or receive circuitry, depending on control signals applied to the antenna switch while presenting different impedances to a connected circuitry.
Kemmochi et al. (US 2010/0091752) discloses an inventive high frequency circuit includes a switch circuit (SPDT1), connected to an antenna terminal (Anti), using a field-effect transistor for switching between a connection with first to third transmitting terminals (Tx1-1, Tx2-1, Tx3-1) and a connection with first to third receiving terminals (Rx1-1, Rx2-1, Rx3-1); a transmitting-side triplexer (Trip1) for branching a transmitting path connected to the switch circuit into transmitting paths of first to third frequency bands; and a receiving-side triplexer (Trip2) for branching a receiving path connected to the switch circuit into receiving paths of the first to third frequency bands.
Tsutsui et al. (US 9,647,775) discloses a power amplification module includes a first input terminal arranged to receive a first transmission signal in a first frequency band, a second input terminal arranged to receive a second transmission signal in a second frequency band higher than the first frequency band, a first amplification circuit that amplifies the first transmission signal, a second amplification circuit that amplifies the second transmission signal, a first filter circuit located between the first input terminal and the first amplification circuit, and a second filter circuit located between the second input terminal and the second amplification circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
