Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Varghese et al. (US 20080139141 A1) in view of Darabi et al. (US 7233772 B1), hereinafter Darabi.
Regarding Independent Claim 1, Varghese discloses,
A transmitter circuit (Fig. 2, 123a) having an input port (Fig. 2, port at 224), a first transmission node (Fig. 2, first node at the output of 232a), a second transmission node (Fig. 2, second node at the output of 232a), a third transmission node (Fig. 2, first node at the output of 232b), and a fourth transmission node (Fig. 2, second node at the output of 232b) and comprising:
A first operational amplifier (Fig. 2, 228a);
a first output stage (Fig. 2, 232a) coupled to the first operational amplifier (Fig. 2, 228a);
a first resistor-capacitor network coupled to the first output stage and the first operational amplifier;
a first switch group (Fig. 2, 234a) coupled between the first resistor-capacitor network (Fig. 2, 230a) and the input port (Fig. 2, port at 224);
a first impedance matching circuit (Fig. 2, 230a) coupled to the first output stage (Fig. 2, 232a), the first transmission node (Fig. 2, first node at the output of 232a), and the second transmission node (Fig. 2, second node at the output of 232a);
a second operational amplifier (Fig. 2, 228b);
a second output stage (Fig. 2, 232b) coupled to the second operational amplifier (Fig. 2, 228b);
a second resistor-capacitor network coupled to the second output stage and the second operational amplifier;
a second switch group (Fig. 2, 234b) coupled between the second resistor-capacitor network (Fig. 2, 230b) and the input port (Fig. 2, port at 224); and
a second impedance matching circuit (Fig. 2, 230b) coupled to the second output stage (Fig. 2, 232b), the third transmission node (Fig. 2, first node at the output of 232b), and the fourth transmission node (Fig. 2, second node at the output of 232b).
Varghese is silent regarding;
a first resistor-capacitor network coupled to the first output stage and the first operational amplifier;
a second resistor-capacitor network coupled to the second output stage and the second operational amplifier;
Darabi discloses:
a first resistor-capacitor network (Fig. 6, 98, 106, 100, and 108) coupled to the first output stage (Fig. 6, VOQP and VOIN) and the first operational amplifier (Fig. 6, 94);
a second resistor-capacitor network (Fig. 6, 104, 112, 102, and 110) coupled to the second output stage (Fig. 6, VOQP and VOQN) and the second operational amplifier (Fig. 6, 96);
Varghese and Darabi are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a resistor-capacitor network coupled to the amplifiers in Varghese‘s design in order to ensure stability and suppress unwanted high-frequency parasitic oscillations in accordance with Darabi‘s design.
Regarding claim 2, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 1, wherein the first resistor-capacitor network comprises a first resistor-capacitor circuit and a second resistor-capacitor circuit, and the second resistor-capacitor network comprises a third resistor-capacitor circuit and a fourth resistor-capacitor circuit.
Varghese is silent regarding;
wherein the first resistor-capacitor network comprises a first resistor-capacitor circuit and a second resistor-capacitor circuit, and the second resistor-capacitor network comprises a third resistor-capacitor circuit and a fourth resistor-capacitor circuit.
Darabi discloses:
wherein the first resistor-capacitor network (Fig. 6, 98, 106, 100, and 108) comprises a first resistor-capacitor circuit (Fig. 6, 98 and 106) and a second resistor-capacitor circuit (Fig. 6, 100 and 108), and the second resistor-capacitor network (Fig. 6, 104, 112, 102, and 110) comprises a third resistor-capacitor circuit (Fig. 6, 104 and 112) and a fourth resistor-capacitor circuit (Fig. 6, 102 and 110).
Varghese and Darabi are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a resistor-capacitor network coupled to the amplifiers in Varghese‘s design in order to ensure stability and suppress unwanted high-frequency parasitic oscillations in accordance with Darabi‘s design.
Regarding claim 3, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 2, wherein the first switch group (Fig. 2, 234a) comprises a first switch and a second switch (Fig. 2, 234a is comprised of two switches), and the second switch group (Fig. 2, 234b) comprises a third switch and a fourth switch (Fig. 2, 234b is comprised of two switches).
Regarding claim 4, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 3, wherein the input port (Fig. 2, port at 224) comprises a first input node and a second input node (Fig. 2, the port at 224 is comprised of two nodes), and the first switch is coupled between the first input node and the first resistor-capacitor circuit (Fig. 2, the first switch of 234a is coupled to the first node at the port of 224), the second switch is coupled between the second input node and the second resistor-capacitor circuit (Fig. 2, the second switch of 234a is coupled to the second node at the port of 224), the third switch is coupled between the first input node and the third resistor-capacitor circuit (Fig. 2, the first switch of 234b is coupled to the first node at the port of 224), and the fourth switch is coupled between the second input node and the fourth resistor-capacitor circuit (Fig. 2, the second switch of 234b is coupled to the second node at the port of 224).
Regarding claim 5, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 1, wherein the first impedance matching circuit (Fig. 2, 230a) comprises a first resistor and a second resistor (Fig. 2, 230a is a low pass filter and low pass filters are known for having resistors), and the second impedance matching circuit (Fig. 2, 230b) comprises a third resistor and a fourth resistor (Fig. 2, 230b is a low pass filter and low pass filters are known for having resistors).
Regarding claim 6, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 5, wherein the first resistor is coupled between the first output stage and the first transmission node (Fig. 2, the first resistor in 230a is coupled to the first node at the output of 232a), the second resistor is coupled between the first output stage and the second transmission node (Fig. 2, the second resistor in 230a is coupled to the second node at the output of 232a), the third resistor is coupled between the second output stage and the third transmission node (Fig. 2, the first resistor in 230b is coupled to the first node at the output of 232b), and the fourth resistor is coupled between the second output stage and the fourth transmission node (Fig. 2, the second resistor in 230b is coupled to the second node at the output of 232b).
Regarding claim 7, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 1, wherein the transmitter circuit operates in a first mode or a second mode [See paragraph [0055], “The I path selector switch 234a may comprise suitable logic, circuitry, and/or code that may enable an input signal to be selectively coupled to one of a plurality of output points. In an exemplary embodiment of the invention, the I path selector switch 234a may select from two pairs of differential input signals, and couple the selected differential input signal to a differential output.”];
in the first mode, the first switch group is turned on and the second switch group is turned off [See paragraph [0055], “The I path selector switch 234a may comprise suitable logic, circuitry, and/or code that may enable an input signal to be selectively coupled to one of a plurality of output points.”];
in the second mode, the first switch group is turned off and the second switch group is turned on [See paragraph [0055], “The I path selector switch 234a may comprise suitable logic, circuitry, and/or code that may enable an input signal to be selectively coupled to one of a plurality of output points.”].
Regarding claim 8, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 1, wherein the first impedance matching circuit (Fig. 6, 230a) and the second impedance matching circuit (Fig. 6, 230b) do not comprise any switch (Fig. 6, 230a and 230b do not comprise a switch).
Regarding independent claim 9, Varghese discloses,
A transmitter circuit (Fig. 2, 123a) having a first transmission node (Fig. 2, first node at the output of 232a), a second transmission node (Fig. 2, second node at the output of 232a), a third transmission node (Fig. 2, first node at the output of 232b), and a fourth transmission node (Fig. 2, second node at the output of 232b) and comprising:
an operational amplifier (Fig. 2, 228a and 228b):
a first output stage (Fig. 2, 232a) coupled to the operational amplifier (Fig. 2, 228a):
a first resistor-capacitor network coupled to the first output stage:
a first switch group (Fig. 2, 234a) coupled between the first resistor-capacitor network (Fig. 2, 230a) and the input port (Fig. 2, port at 224);
a first impedance matching circuit (Fig. 2, 230a) coupled to the first output stage (Fig. 2, 232a), the first transmission node (Fig. 2, first node at the output of 232a), and the second transmission node (Fig. 2, second node at the output of 232a);
a second output stage (Fig. 2, 232b) coupled to the second operational amplifier (Fig. 2, 228b);
a second resistor-capacitor network coupled to the second output stage;
a second switch group (Fig. 2, 234b) coupled between the second resistor-capacitor network (Fig. 2, 230b) and the input port (Fig. 2, port at 224); and
a second impedance matching circuit (Fig. 2, 230b) coupled to the second output stage (Fig. 2, 232b), the third transmission node (Fig. 2, first node at the output of 232b), and the fourth transmission node (Fig. 2, second node at the output of 232b);
a common mode feedback (CMFB) circuit (Fig. 2, 240);
a first switch (Fig. 2, 240 is a baseband processor, which comprises switches) coupled between the CMFB circuit (Fig. 2, 240) and the first output stage (Fig. 2, 232a); and
a second switch (Fig. 2, 240 is a baseband processor, which comprises switches) coupled between the CMFB circuit (Fig. 2, 240) and the second output stage (Fig. 2, 232a).
Varghese is silent regarding;
a first resistor-capacitor network coupled to the first output stage:
a second resistor-capacitor network coupled to the second output stage;
Darabi discloses:
a first resistor-capacitor network (Fig. 6, 98, 106, 100, and 108) coupled to the first output stage (Fig. 6, VOQP and VOIN);
a second resistor-capacitor network (Fig. 6, 104, 112, 102, and 110) coupled to the second output stage (Fig. 6, VOQP and VOQN);
Varghese and Darabi are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a resistor-capacitor network coupled to the amplifiers in Varghese‘s design in order to ensure stability and suppress unwanted high-frequency parasitic oscillations in accordance with Darabi‘s design.
Regarding claim 10, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 9, wherein the first resistor-capacitor network comprises a first resistor-capacitor circuit and a second resistor-capacitor circuit, and the second resistor-capacitor network comprises a third resistor-capacitor circuit and a fourth resistor-capacitor circuit.
Varghese is silent regarding;
wherein the first resistor-capacitor network comprises a first resistor-capacitor circuit and a second resistor-capacitor circuit, and the second resistor-capacitor network comprises a third resistor-capacitor circuit and a fourth resistor-capacitor circuit.
Darabi discloses:
wherein the first resistor-capacitor network (Fig. 6, 98, 106, 100, and 108) comprises a first resistor-capacitor circuit (Fig. 6, 98 and 106) and a second resistor-capacitor circuit (Fig. 6, 100 and 108), and the second resistor-capacitor network (Fig. 6, 104, 112, 102, and 110) comprises a third resistor-capacitor circuit (Fig. 6, 104 and 112) and a fourth resistor-capacitor circuit (Fig. 6, 102 and 110).
Varghese and Darabi are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a resistor-capacitor network coupled to the amplifiers in Varghese‘s design in order to ensure stability and suppress unwanted high-frequency parasitic oscillations in accordance with Darabi‘s design.
Regarding claim 11, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 10, wherein the first switch group (Fig. 2, 234a) comprises a third switch and a fourth switch (Fig. 2, 234a is comprised of two switches), and the second switch group (Fig. 2, 234b) comprises a fifth switch and a sixth switch (Fig. 2, 234b is comprised of two switches).
Regarding claim 12, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 11, wherein the operational amplifier (Fig. 2, 228a and 228b) has a first input terminal and a second input terminal (Fig. 2, 228a has two input terminals), and the third switch is coupled between the first input terminal of the operational amplifier and the first resistor-capacitor circuit (Fig. 2, the first switch of 234a is coupled to the first node of 228a), the fourth switch is coupled between the second input terminal of the operational amplifier and the second resistor-capacitor circuit (Fig. 2, the second switch of 234a is coupled to the second node of 228a), the fifth switch is coupled between the first input terminal of the operational amplifier and the third resistor-capacitor circuit (Fig. 2, the first switch of 234b is coupled to the first node of 228b), and the sixth switch is coupled between the second input terminal of the operational amplifier and the fourth resistor-capacitor circuit (Fig. 2, the second switch of 234b is coupled to the second node of 228b).
Regarding claim 13, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 9, wherein the first impedance matching circuit (Fig. 2, 230a) comprises a first resistor and a second resistor (Fig. 2, 230a is a low pass filter and low pass filters are known for having resistors), and the second impedance matching circuit (Fig. 2, 230b) comprises a third resistor and a fourth resistor (Fig. 2, 230b is a low pass filter and low pass filters are known for having resistors).
Regarding claim 14, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 5, wherein the first resistor is coupled between the first output stage and the first transmission node (Fig. 2, the first resistor in 230a is coupled to the first node at the output of 232a), the second resistor is coupled between the first output stage and the second transmission node (Fig. 2, the second resistor in 230a is coupled to the second node at the output of 232a), the third resistor is coupled between the second output stage and the third transmission node (Fig. 2, the first resistor in 230b is coupled to the first node at the output of 232b), and the fourth resistor is coupled between the second output stage and the fourth transmission node (Fig. 2, the second resistor in 230b is coupled to the second node at the output of 232b).
Regarding claim 15, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 9, wherein the transmitter circuit operates in a first mode or a second mode [See paragraph [0055], “The I path selector switch 234a may comprise suitable logic, circuitry, and/or code that may enable an input signal to be selectively coupled to one of a plurality of output points. In an exemplary embodiment of the invention, the I path selector switch 234a may select from two pairs of differential input signals, and couple the selected differential input signal to a differential output.”]:
in the first mode, the first switch group and the first switch are turned on, and the second switch group and the second switch are turned off [See paragraph [0055], “The I path selector switch 234a may comprise suitable logic, circuitry, and/or code that may enable an input signal to be selectively coupled to one of a plurality of output points.”];
in the second mode, the first switch group and the first switch are turned off, and the second switch group and the second switch are turned on [See paragraph [0055], “The I path selector switch 234a may comprise suitable logic, circuitry, and/or code that may enable an input signal to be selectively coupled to one of a plurality of output points.”].
Regarding claim 16, Varghese discloses,
The transmitter circuit (Fig. 2, 123a) of claim 9, wherein the first impedance matching circuit (Fig. 6, 230a) and the second impedance matching circuit (Fig. 6, 230b) do not comprise any switch (Fig. 6, 230a and 230b do not comprise a switch).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE E PINERO whose telephone number is (703)756-4746. The examiner can normally be reached M-F 8:00 AM - 5:00 PM (ET).
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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