Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over US20220366211A1 to Ma et al, AutoFreeze: Automatically Freezing Model Blocks to Accelerate Fine-tuning by Liu et al and US20210382693A1 to Song.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US20220366211A1 to Ma et al, AutoFreeze: Automatically Freezing Model Blocks to Accelerate Fine-tuning by Liu et al, US20210382693A1 to Song and A Survey on Multi-Task Learning by Zhang et al
Ma teaches claim 1. A semiconductor device comprising:
a first non-volatile memory (NVM) configured to store weights of a first set of layers of a machine learning model, wherein weights of the first set of layers and (Ma para 116 “a non-volatile memory device includes: a first array of non-volatile memory cells each storing a weight value of a first layer of a neural network…” Ma para 116 “non-volatile memory device includes: a first array of non-volatile memory cells each storing a weight value of a first layer of a neural network; a second array of non-volatile memory cells each comprising a programmable resistive element connected in series with a threshold switching selector, the programmable resistive element storing a weight value of a second layer of the neural network and the threshold switching selector configured to become conductive in response to application of a voltage level exceeding a threshold voltage…”)
a second NVM configured to store weights of a second set of layers of the machine learning model, wherein weights of the second set of layers are adjustable, the second NVM is different from the first NVM, and the second NVM comprises a(Ma para 116 “a non-volatile memory device includes:… a second array of non-volatile memory cells each comprising a programmable resistive element connected in series with a threshold switching selector, the programmable resistive element storing a weight value of a second layer of the neural network…” Ma para 112 “the weights can be adjusted by reprogramming one or more memory cells…” Ma para 116 “non-volatile memory device includes: a first array of non-volatile memory cells each storing a weight value of a first layer of a neural network; a second array of non-volatile memory cells each comprising a programmable resistive element connected in series with a threshold switching selector, the programmable resistive element storing a weight value of a second layer of the neural network and the threshold switching selector configured to become conductive in response to application of a voltage level exceeding a threshold voltage…”) Ma doesn’t teach fixing weights.
However, Liu teaches that weights of the first set of layers are fixed. (Liu fig. 1 p. 2 “We present a high level design of AutoFreeze. During fine-tuning, AutoFreeze adaptively determines layers which can be frozen. Once layers are frozen, the backward computation for those layers can be avoided. At later epochs, intermediate outputs are also cached leading to further gains.” See fig. 1 below.)
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Liu, Ma and the claims all train neural networks. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to “to choose which layers are trained and… this can accelerate model fine-tuning while preserving accuracy.” Liu abs.
Ma doesn’t teach a dedicated MAC for each NVM bank.
However, Song teaches the first NVM comprises a first multiply-accumulate unit… the second NVM comprises a second multiply-accumulate unit. (Song fig. 2 shows several memory banks “BK0” “BK2” with their own dedicated MACs “MAC0” “MAC1”.)
Song, Ma and the claims all teach Processing in memory. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to dedicate a MAC to each layer so that “a data processing speed in the neural network may be improved.” Song para 3.
Ma teaches claim 2. The semiconductor device of claim 1, wherein the first NVM is at least one of:
an analog NVM; and (Ma para 95 “Depending on the embodiment, the weights and input values can be analog values…”)
a multi-level-cell (MLC) NVM. (Ma para 72 “ the memory cells can be binary valued, having either a low resistance state or a high resistance state, or multi-level cells (MLCs…”)
Ma teaches claim 3. The semiconductor device of claim 2, wherein the first NVM is a monolithic three-dimensional (3D) NVM. (Ma fig. 7d see below. Ma para 41 “memory structure 502 comprises a three dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. “)
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Ma fig. 7d
Ma teaches claim 4. The semiconductor device of claim 1, wherein at least one of the NVMs is configured to perform compute-in-memory. (Ma para 26 “The following presents techniques for performing dropout when implementing a neural network through in-memory computation using a memory array in which the memory cells include a threshold switching selector in series with a programmable resistance element.”)
Ma teaches claim 5. The semiconductor device of claim 1, wherein the second NVM is an analog NVM with bi-directional device conductance tunability. (Ma abs “storing weight values as conductance values in memory cells formed of a series combination of a threshold switching selector, such as an ovonic threshold switch, and a programmable resistive element, such as a ReRAM element.” ReRam is a bi-directional device with conductance tunability. Ma para 95 “Depending on the embodiment, the weights and input values can be analog values…”)
Ma teaches claim 6. The semiconductor device of claim 1, wherein the first NVM and the second NVM constitute at least a portion of a neural network. (Ma para 116 “non-volatile memory device includes: a first array of non-volatile memory cells each storing a weight value of a first layer of a neural network; a second array of non-volatile memory cells each comprising a programmable resistive element connected in series with a threshold switching selector, the programmable resistive element storing a weight value of a second layer of the neural network and the threshold switching selector configured to become conductive in response to application of a voltage level exceeding a threshold voltage…”)
Ma teaches claim 7. The semiconductor device of claim 1, wherein the first NVM and the second NVM are integrated on a same package. (Ma fig. 7d see below. Ma para 71 “FIG. 7D depicts an embodiment of a portion of a two level memory array that forms a cross-point architecture in an oblique view.”)
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Ma fig. 7d
Ma teaches claim 8. The semiconductor device of claim 1, wherein the second NVM and at least one additional copy of the second NVM are connected to the first NVM to implement (Ma fig. 7d top four rows of memory cells 701 are the first and second copy of the second NVM, see below. Learning is taught in Ma para 79 “training a neural network to generate a set of weights.”)
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Ma fig. 7d, Examiner added pointers.
Ma doesn’t teach multi-task learning.
However, Zhang teaches multi-task learning. (Zhang title “A Survey on Multi-Task Learning” Zhang abs “Multi-Task Learning (MTL) is a learning paradigm in machine learning and its aim is to leverage useful information contained in multiple related tasks to help improve the generalization performance of all the tasks.”)
Ma, Zhang and the claims are all neural networks. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to do multi-task learning in Ma “to boost their performance…” Zhang abs.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AUSTIN HICKS/Primary Examiner, Art Unit 2142
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