DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 6-9, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over TADA; Akira US PGPUB 20210243046 A1 in view of Smart; David C. et al. US PGPUB 20190104085 A1, further in view of Modi; Geet Govind et al. US Patent 11695539 B1
Regarding claim 1. Tada teaches A non-transitory computer-readable storage medium, the computer-readable storage medium including instructions that when executed by a processor, (Fig. 2, CPU/Flash/Ram 51/52/53) cause the processor to:
determine, by a driver of an Ethernet controller based on an interrupt received from a PHY circuit coupled to the Ethernet controller, that a connection between the PHY circuit and a remote device was established using auto-negotiation over a physical communication medium; ([0043] The PHY 3 operates according to the operation setting registered in the register 32. An item (in other words, parameter) that makes up the operation setting of the PHY 3 is, for example, communication standard applied to the PHY 3, a serial transmission method, communication speed, a role as a result of auto-negotiation (master or slave), an interrupt condition, an operation mode, or the like.)
Tada does not teach
determine, by the driver, a speed of the connection; and based on a determination that the speed of the connection is not a first predetermined speed,
enable, by the driver, auto-negotiation between the PHY circuit and the Ethernet controller to establish a link at a second speed that is different than the first predetermined speed using a power management controller (PMC) interface.
However, Smart teaches
determine, by the driver, a speed of the connection; and based on a determination that the speed of the connection is not a first predetermined speed, ([0007] When the first PHY auto-negotiates with the first subnetwork to communicate at the faster speed and the second PHY auto-negotiates with the second subnetwork to communicate at the slower speed, the controller forces the first PHY to communicate at the slower speed which causes communication between the first and second PHYs at the slower speed and causes the first PHY to renegotiate with the first subnetwork to communicate at the slower speed.)
enable, by the driver, auto-negotiation between the PHY circuit and the Ethernet controller to establish a link at a second speed ([0007] When the first PHY auto-negotiates with the first subnetwork to communicate at the slower speed and the second PHY auto-negotiates with the second subnetwork to communicate at the faster speed, the controller forces the second PHY to communicate at the slower speed which causes communication between the first and second PHYs at the slower speed and causes the second PHY to renegotiate with the second subnetwork to communicate at the slower speed.) ) that is different than the first predetermined speed. ([0007] Each of the first and second PHYs can auto-negotiate to communicate at a slower speed and a faster speed, where the faster speed is faster than the slower speed.)
in order to reduce congestion by setting interfaces into compatible communication speed ([0005])
Tada and Smart are analogous art in the same field of endeavor of packet network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of compatible speed negotiation in Smart in order to reduce congestion.
Tada and Smart do not teach using a power management controller (PMC) interface.
However, Modi teaches using a power management controller (PMC) interface. (col 7 line 55-60. Management and control circuitry 220 may further include power management circuitry for receiving one or more power supply voltages, one example of which is the VDD power supply voltage received at terminal VDD shown in FIG. 2, and for generating bias and reference voltages from those power supply voltages for distribution throughout PHY 106. Other functions not shown in FIG. 2 may also be provided in PHY 106, such functions including a “wake on LAN” circuit function, an auto-negotiation circuit function, and the like.)
in order to improve recovery from malfunctions (col 18, line 10)
Tada and Modi are analogous art in the same field of endeavor of network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of integrated PHY circuits in order to improve recovery from malfunctions.
Regarding claim 2. Tada and Smart and Modi teach The computer-readable storage medium of claim 1, but Tada does not teach wherein the instructions further cause the processor to: store, by the driver, an indication of the second speed in a media access control (MAC) circuit of the Ethernet controller.
However, Smart teaches
wherein the instructions further cause the processor to: store, by the driver, an indication of the second speed in a media access control (MAC) circuit of the Ethernet controller. ([0030] Where a traditional repeater is configured for a single speed of communication, and without the ability to adapt if a device attached to MDI 212 is not communicating at the same speed as a device attached to MDI 222, the adaptive network repeater 200 adds a microcontroller unit (MCU) 230, which can monitor and control data communication link status of both PHY 210 and PHY 220 through a bidirectional interface to the MDIO port of each of PHY 210 and PHY 220. The microcontroller 230 can be a small, inexpensive micro-controller, for example an 8-bit microcontroller.)
in order to reduce congestion by setting interfaces into compatible communication speed ([0005])
Tada and Smart are analogous art in the same field of endeavor of packet network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of compatible speed negotiation in Smart in order to reduce congestion.
Regarding claim 7. Tada and Smart and Modi teach The computer-readable storage medium of claim 1, Tada teaches wherein the Ethernet controller is to comprise a time-sensitive networking (TSN) Ethernet controller, ([0050] Each of the MACs 42 may be configured to provide the functions specified by IEEE 802.3. Each of the MACs 42 correspond to a MAC unit.)
Tada does not teach
wherein the instructions further cause the processor to: based on a determination that the second speed does not exceed the first predetermined speed, perform the auto-negotiation between the PHY circuit and the TSN Ethernet controller.
However, Smart teaches
wherein the instructions further cause the processor to: based on a determination that the second speed does not exceed the first predetermined speed, perform the auto-negotiation between the PHY circuit and the TSN Ethernet controller. ([0007] hen the first PHY auto-negotiates with the first subnetwork to communicate at the faster speed and the second PHY auto-negotiates with the second subnetwork to communicate at the slower speed, the controller forces the first PHY to communicate at the slower speed which causes communication between the first and second PHYs at the slower speed and causes the first PHY to renegotiate with the first subnetwork to communicate at the slower speed.)
in order to reduce congestion by setting interfaces into compatible communication speed ([0005])
Tada and Smart are analogous art in the same field of endeavor of packet network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of compatible speed negotiation in Smart in order to reduce congestion.
Regarding claim 8 and 9. Tada and Smart and Modi teach An apparatus, comprising: an Ethernet controller; a processor; and a memory storing instructions that, when executed by the processor, cause the processor (Tada Fig. 2, Microcomputer 5 containing CPU/Flash/RAM) to perform the method recited in claim 1 and 2.
Regarding claim 14. Tada and Smart and Modi teach The apparatus of claim 8, and Tada teaches wherein the driver reads a register of the PHY circuit to determine the speed of the connection via a medium independent I/O (MDIO) bus, ([0018] Further, the relay device includes a PHY manager that controls an operation of the PHY module. The PHY manager is connected to the PHY module via a signal line (hereinafter, MDIO line) for inputting and outputting management data, which is data for managing the PHY module. The PHY manager rewrites a value of a register of the PHY module in order to change an operation setting of the PHY module and reads out the register value of the PHY module via the MDIO line.)
wherein the Ethernet controller is a time-sensitive networking (TSN) Ethernet controller compatible with standards of the Institute of Electrical and Electronics Engineers (IEEE) 802.3 working group and the IEEE 802.1 working group. ([0050] Each of the MACs 42 may be configured to provide the functions specified by IEEE 802.3. Each of the MACs 42 correspond to a MAC unit.)
Regarding claim 15. Tada teaches A method, comprising: determining, by a driver of an Ethernet controller of a system on a chip (SoC) ([0017] The PHY module provides a physical layer and is packaged as a PHY chip with, for example, one or two ports.) based on an interrupt received from a PHY circuit coupled to the Ethernet controller, that a connection between the PHY circuit and a remote device was established using auto-negotiation over a physical communication medium; ([0043] The PHY 3 operates according to the operation setting registered in the register 32. An item (in other words, parameter) that makes up the operation setting of the PHY 3 is, for example, communication standard applied to the PHY 3, a serial transmission method, communication speed, a role as a result of auto-negotiation (master or slave), an interrupt condition, an operation mode, or the like.)
Tada does not teach determining, by the driver, a speed of the connection; and based on a determination that the speed of the connection is not a first predetermined speed, enabling, by the driver, auto-negotiation between the PHY circuit and the Ethernet controller to establish a link at a second speed that is different than the first predetermined speed using a power management controller (PMC).
However, Smart teaches
determine, by the driver, a speed of the connection; and based on a determination that the speed of the connection is not a first predetermined speed, ([0007] When the first PHY auto-negotiates with the first subnetwork to communicate at the faster speed and the second PHY auto-negotiates with the second subnetwork to communicate at the slower speed, the controller forces the first PHY to communicate at the slower speed which causes communication between the first and second PHYs at the slower speed and causes the first PHY to renegotiate with the first subnetwork to communicate at the slower speed.)
enable, by the driver, auto-negotiation between the PHY circuit and the Ethernet controller to establish a link at a second speed ([0007] When the first PHY auto-negotiates with the first subnetwork to communicate at the slower speed and the second PHY auto-negotiates with the second subnetwork to communicate at the faster speed, the controller forces the second PHY to communicate at the slower speed which causes communication between the first and second PHYs at the slower speed and causes the second PHY to renegotiate with the second subnetwork to communicate at the slower speed.) ) that is different than the first predetermined speed. ([0007] Each of the first and second PHYs can auto-negotiate to communicate at a slower speed and a faster speed, where the faster speed is faster than the slower speed.)
in order to reduce congestion by setting interfaces into compatible communication speed ([0005])
Tada and Smart are analogous art in the same field of endeavor of packet network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of compatible speed negotiation in Smart in order to reduce congestion.
Tada and Smart do not teach using a power management controller (PMC) interface.
However, Modi teaches using a power management controller (PMC) interface. (col 7 line 55-60. Management and control circuitry 220 may further include power management circuitry for receiving one or more power supply voltages, one example of which is the VDD power supply voltage received at terminal VDD shown in FIG. 2, and for generating bias and reference voltages from those power supply voltages for distribution throughout PHY 106. Other functions not shown in FIG. 2 may also be provided in PHY 106, such functions including a “wake on LAN” circuit function, an auto-negotiation circuit function, and the like.)
in order to improve recovery from malfunctions (col 18, line 10)
Tada and Modi are analogous art in the same field of endeavor of network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of integrated PHY circuits in order to improve recovery from malfunctions.
Regarding claim 16. Tada and Smart and Modi teach The method of claim 15, Tada teaches wherein the Ethernet controller is a time-sensitive networking (TSN) Ethernet controller compatible with standards of the Institute of Electrical and Electronics Engineers (IEEE) 802.3 working group and the IEEE 802.1 working group, ([0050] Each of the MACs 42 may be configured to provide the functions specified by IEEE 802.3. Each of the MACs 42 correspond to a MAC unit.)
They don’t teach the method further comprising: storing, by the driver, an indication of the second speed in a media access control (MAC) circuit of the TSN Ethernet controller.
However, Smart teaches
storing, by the driver, an indication of the second speed in a media access control (MAC) circuit of the Ethernet controller. ([0030] Where a traditional repeater is configured for a single speed of communication, and without the ability to adapt if a device attached to MDI 212 is not communicating at the same speed as a device attached to MDI 222, the adaptive network repeater 200 adds a microcontroller unit (MCU) 230, which can monitor and control data communication link status of both PHY 210 and PHY 220 through a bidirectional interface to the MDIO port of each of PHY 210 and PHY 220. The microcontroller 230 can be a small, inexpensive micro-controller, for example an 8-bit microcontroller.)
in order to reduce congestion by setting interfaces into compatible communication speed ([0005])
Tada and Smart are analogous art in the same field of endeavor of packet network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of compatible speed negotiation in Smart in order to reduce congestion.
Claims 3, 5, 6, 10, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tada and Smart as applied to claim 1, 8 and 15 above, and further in view of Ghosh; Shubhadeep et al. US Patent 9480097 B1.
Regarding claim 3, Tada and Smart and Modi teach The computer-readable storage medium of claim 1, but they don’t teach wherein the instructions further cause the processor to, prior to the determination that the connection was established: disable, by the driver, an auto-negotiation bit of the PHY circuit; and receive the interrupt.
However, Ghosh teaches
wherein the instructions further cause the processor to, prior to the determination that the connection was established: disable, by the driver, an auto-negotiation bit of the PHY circuit; and receive the interrupt. (col 10, line 10, “an auto-negotiation configuration bit of the MII control register of local network device 210 may be used to enable or disable auto-negotiation (e.g., bit 4, which specifies a value for “an_config”). Local network device 210 may determine whether auto-negotiation is enabled based on the value of the auto-negotiation configuration bit.”)
in order to improve network performance by increasing the likelihood of establishing a communication link (col 10 line 55)
Tada and Ghosh are analogous art in the same field of endeavor of wireless communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of disabling an auto-negotiation in order to improve network performance.
Regarding claim 5. Tada and Smart and Modi teach The computer-readable storage medium of claim 1, Tada does not teach wherein the instructions further cause the processor to:
based on a determination that the speed of the connection exceeds the first predetermined speed: disable, by the driver, auto-negotiation between the PHY circuit and the Ethernet controller; and
store, by the driver, an indication of the speed of the connection in a physical coding sublayer (PCS) circuit of the Ethernet controller.
However, Smart teaches
store, by the driver, an indication of the speed of the connection in a physical coding sublayer (PCS) circuit of the Ethernet controller. ([0030] Where a traditional repeater is configured for a single speed of communication, and without the ability to adapt if a device attached to MDI 212 is not communicating at the same speed as a device attached to MDI 222, the adaptive network repeater 200 adds a microcontroller unit (MCU) 230, which can monitor and control data communication link status of both PHY 210 and PHY 220 through a bidirectional interface to the MDIO port of each of PHY 210 and PHY 220. The microcontroller 230 can be a small, inexpensive micro-controller, for example an 8-bit microcontroller.)
in order to reduce congestion by setting interfaces into compatible communication speed ([0005])
Tada and Smart are analogous art in the same field of endeavor of packet network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of compatible speed negotiation in Smart in order to reduce congestion.
Tada and Smart do not teach
based on a determination that the speed of the connection exceeds the first predetermined speed: disable, by the driver, auto-negotiation between the PHY circuit and the Ethernet controller; and
However, Ghosh teaches
based on a determination that the speed of the connection exceeds the first predetermined speed: disable, by the driver, an auto-negotiation bit of the PHY circuit; and receive the interrupt. (col 10, line 10, “an auto-negotiation configuration bit of the MII control register of local network device 210 may be used to enable or disable auto-negotiation (e.g., bit 4, which specifies a value for “an_config”). Local network device 210 may determine whether auto-negotiation is enabled based on the value of the auto-negotiation configuration bit.”)
in order to improve network performance by increasing the likelihood of establishing a communication link (col 10 line 55)
Tada and Ghosh are analogous art in the same field of endeavor of wireless communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify
Regarding claim 6. Tada and Smart and Modi and Ghosh teach The computer-readable storage medium of claim 5, Tada does not teach wherein the instructions further cause the processor to: receive, by the driver from the PCS circuit, another interrupt; read, by the driver and in the PCS circuit, the second speed of the link; and store, by the driver in a media access control (MAC) circuit of the Ethernet controller, an indication of the second speed read from the PCS circuit.
However, Smart teaches
receive, by the driver from the PCS circuit, another interrupt; read, by the driver and in the PCS circuit, the second speed of the link; ([0039] In this case, the PHY 210 will auto-negotiate to a speed of 1000 Mb/s which is the highest speed supported by the network device 340; and the PHY 220 will auto-negotiate to a speed of 100 Mb/s which is the highest speed supported by the network device 342.) )
store, by the driver in a media access control (MAC) circuit of the Ethernet controller, an indication of the second speed read from the PCS circuit. . ([0030] Where a traditional repeater is configured for a single speed of communication, and without the ability to adapt if a device attached to MDI 212 is not communicating at the same speed as a device attached to MDI 222, the adaptive network repeater 200 adds a microcontroller unit (MCU) 230, which can monitor and control data communication link status of both PHY 210 and PHY 220 through a bidirectional interface to the MDIO port of each of PHY 210 and PHY 220. The microcontroller 230 can be a small, inexpensive micro-controller, for example an 8-bit microcontroller.)
in order to reduce congestion by setting interfaces into compatible communication speed ([0005])
Tada and Smart are analogous art in the same field of endeavor of packet network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of compatible speed negotiation in Smart in order to reduce congestion.
Regarding claim 10. Tada, Smart, Modi and Ghosh teaches The apparatus of claim 8, wherein the instructions further cause the processor to perform the method in claim 3.
Regarding claim 17. Tada and Smart teach The method of claim 15, but they don’t teach further comprising prior to determining that the connection was established: disabling, by the driver, an auto-negotiation bit of the PHY circuit; and receiving the interrupt.
However, Ghosh teaches
disable, by the driver, an auto-negotiation bit of the PHY circuit; and receive the interrupt. (col 10, line 10, “an auto-negotiation configuration bit of the MII control register of local network device 210 may be used to enable or disable auto-negotiation (e.g., bit 4, which specifies a value for “an_config”). Local network device 210 may determine whether auto-negotiation is enabled based on the value of the auto-negotiation configuration bit.”)
in order to improve network performance by increasing the likelihood of establishing a communication link (col 10 line 55)
Tada and Ghosh are analogous art in the same field of endeavor of wireless communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of disabling an auto-negotiation in order to improve network performance.
Regarding claim 20. Tada and Smart and Modi teach The method of claim 15, but Tada does not teach
further comprising based on a determination that the speed of the connection exceeds the first predetermined speed: disabling, by the driver, auto-negotiation between the PHY circuit and the Ethernet controller; and storing, by the driver, an indication of the speed of the connection in a physical coding sublayer (PCS) circuit of the Ethernet controller.
However, Smart teaches
store, by the driver, an indication of the speed of the connection in a physical coding sublayer (PCS) circuit of the Ethernet controller.([0030] Where a traditional repeater is configured for a single speed of communication, and without the ability to adapt if a device attached to MDI 212 is not communicating at the same speed as a device attached to MDI 222, the adaptive network repeater 200 adds a microcontroller unit (MCU) 230, which can monitor and control data communication link status of both PHY 210 and PHY 220 through a bidirectional interface to the MDIO port of each of PHY 210 and PHY 220. The microcontroller 230 can be a small, inexpensive micro-controller, for example an 8-bit microcontroller.)
in order to reduce congestion by setting interfaces into compatible communication speed ([0005])
Tada and Smart are analogous art in the same field of endeavor of packet network communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of compatible speed negotiation in Smart in order to reduce congestion.
Tada and Smart do not teach
based on a determination that the speed of the connection exceeds the first predetermined speed: disable, by the driver, auto-negotiation between the PHY circuit and the Ethernet controller; and
However, Ghosh teaches
based on a determination that the speed of the connection exceeds the first predetermined speed: disable, by the driver, an auto-negotiation bit of the PHY circuit; and receive the interrupt. (col 10, line 10, “an auto-negotiation configuration bit of the MII control register of local network device 210 may be used to enable or disable auto-negotiation (e.g., bit 4, which specifies a value for “an_config”). Local network device 210 may determine whether auto-negotiation is enabled based on the value of the auto-negotiation configuration bit.”)
in order to improve network performance by increasing the likelihood of establishing a communication link (col 10 line 55)
Tada and Ghosh are analogous art in the same field of endeavor of wireless communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify
Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tada and Smart and Modi as applied to claim 1, 8, and 15 above, and further in view of Wiley; George Alan US PGPUB 20150271037 A1
Regarding claim 4. Tada and Smart and Modi teach The computer-readable storage medium of claim 1, but it does not teach wherein the instructions further cause the processor to: determine, by the driver, that a set of lanes of a flexible interface adapter (FIA) coupled to the Ethernet controller are allocated to the Ethernet controller; and
program, by the driver, lane configuration registers of the FIA based on the speed of the connection.
However, Wiley teaches
wherein the instructions further cause the processor to: determine, by the driver, that a set of lanes of a flexible interface adapter (FIA) coupled to the Ethernet controller are allocated to the Ethernet controller; ([0096] One or more of the differential receiver outputs in the slave will change at each UI boundary due to the symbol encoding rules. When multiple receiver outputs change, they are often staggered in time due to slight differences in rise and fall times between the three signals of the lane and due to slight differences in the length of each of the three signals in a lane.) and
program, by the driver, lane configuration registers of the FIA based on the speed of the connection. ([0113] The Tx Lane Configuration Registers 1210 may include a set registers (e.g., 12C registers, SPI registers, etc.) to write to a block of registers that chooses the test pattern values and the debug and/or operating modes of the modified transmitter 1200.)
in order to minimize transmission jitter by providing a more reliable testing patter in the lane configuration register ([0003])
Tada and Wiley are analogous art in the same field of endeavor of wireless communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of lane configuration register in Wiley in order to minimize transmission jitter.
Regarding claim 11. Tada, Smart, Modi and Wiley teach The apparatus of claim 8, wherein the instructions further cause the processor to perform the method in claim 4.
Regarding claim 18. Tada and Smart and Modi teach The method of claim 15, but it does not teach further comprising: determining, by the driver, that a set of lanes of a flexible interface adapter (FIA) coupled to the Ethernet controller are allocated to the Ethernet controller; and programming, by the driver, lane configuration registers of the FIA based on the speed of the connection.
However, Wiley teaches
determine, by the driver, that a set of lanes of a flexible interface adapter (FIA) coupled to the Ethernet controller are allocated to the Ethernet controller; ([0096] One or more of the differential receiver outputs in the slave will change at each UI boundary due to the symbol encoding rules. When multiple receiver outputs change, they are often staggered in time due to slight differences in rise and fall times between the three signals of the lane and due to slight differences in the length of each of the three signals in a lane.) and
program, by the driver, lane configuration registers of the FIA based on the speed of the connection. ([0113] The Tx Lane Configuration Registers 1210 may include a set registers (e.g., 12C registers, SPI registers, etc.) to write to a block of registers that chooses the test pattern values and the debug and/or operating modes of the modified transmitter 1200.)
in order to minimize transmission jitter by providing a more reliable testing patter in the lane configuration register ([0003])
Tada and Wiley are analogous art in the same field of endeavor of wireless communication. It would have been obvious before the effective filing date of the claimed invention to a person with ordinary skill in the art to modify the method in Tada with the technique of lane configuration register in Wiley in order to minimize transmission jitter.
Allowable Subject Matter
Claims 12, 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHAOHUI YANG whose telephone number is (571)270-7527. The examiner can normally be reached 9 AM to 5 PM M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marcus Smith can be reached at 571 270-1096. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHAOHUI YANG/ Examiner, Art Unit 2468
/MARCUS SMITH/ Supervisory Patent Examiner, Art Unit 2468
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