Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/05/2022, 05/15/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements mentioned above are being considered by the examiner, except for the reference that has been lined through in the IDS submitted on 05/15/2024 because the applicant has not provided a translated copy of the cited references.
Specification
The abstract of the disclosure is objected to because of undue length, exceeding 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The disclosure is objected to because of the following informalities:
The applicant’s specification paragraph [0003] appears to contain a grammatical error and should be changed to: “and may use [[a]] several rows simultaneously in performing [[an]] a MAC operation”.
The applicant’s specification paragraphs [0038], [0066], [0080], [0087], [0090], and [0093] are blank.
The applicant’s specification paragraph [0115] refers to MAC[1] as the third summation charge, however, in [0095], and in [0101] MAC[1] is referred to as the first summation charge.
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(o) because figure 7 lacks suitable descriptive legends.
Furthermore, the drawings are objected to as failing to comply with 37 CFR 1.84(a)(1) because Figures 3-11, and 13-15 are blurry, difficult to read, and requires solid black lines.
Furthermore, the drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: paragraphs [0052]-[0053] of the applicant’s specification reference figures 5(a)-5(c), but the drawings do not show/label figures 5(a)-5(c).
Furthermore, the applicant’s specification paragraphs [0040], [0041], [0061], [0079], [0082], [0088], [0089], and [0122] refer to figure 2 for bank 100, however figure 2 does not include reference sign 100 for a bank.
Furthermore, the applicant’s specification paragraph [0047] references SRAM circuit SR11, however figure 3 does not include reference sign SR11.
Furthermore, the applicant’s specification paragraph [0058] references SRAM SR12 in figure 3, however figure 3 does not include reference sign SR12.
Furthermore, the applicant’s specification paragraph [0072] references SRAM SR21 as part of figure 6, however figure 6 does not include reference sign SR21.
Furthermore, the applicant’s specification paragraph [0076] references SRAM SR22 as part of figure 6 output generator 124, however figure 6 does not include reference sign SR22 in output generator 124.
Furthermore, the applicant’s specification paragraph [0072] references output generator 122 having transistor TR27, however transistor TR27, in figure 6, is not shown as being in output generator 122, instead it is a part of the multiplexor circuit 123.
Furthermore, the applicant’s specification paragraph [0076] references output generator having transistor TR27, however, transistor TR27, in figure 6, is not shown as being in output generator 124, instead it is part of the multiplexor circuit 123.
Furthermore, the applicant’s specification paragraph [0074] references output generator 122 generating sampling signal VM2, however VM2 is not shown as being produced by output generator 122, but instead generated by signal selector 121.
Furthermore, the applicant’s specification paragraph [0074] references VM2 applied to capacitor C21, however VM2, in figure 6, is shown as being output from sign selector circuit 121, and not applied to capacitor C21, which is in the output generation circuit 122.
Furthermore, the applicant’s specification paragraph [0074] references output generator 122 providing the second sampling signal VM2 to the second output generator 124, however figure 6 shows the reference sign VM2 as being provided to output generator 122 by the sign selector circuit 121.
Furthermore, the applicant’s specification paragraph [0075] references multiplexor circuit 123 generating a second sampling signal VM2, whereas [0074] states that VM2 is generated by output generator 122. Regardless, figure 6 shows the sign selection circuit 121 producing the sampling signal with reference sign VM2 instead.
Furthermore, the applicant’s specification paragraph [0102] gives an equation which is in reference to figure 10 which references Q0. Figure 10 does not contain a reference signal Q0.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 appears to contain a grammatical error and should be changed to: “the fourth summation charge and configured to generate an output voltage”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “an input controller provided with an input signal and configured to generate” in claim 1, and “output controller is configured to generate an analog voltage” in claim 9.
In review of the applicant’s specification, the structure of “input controller” is interpreted as: the input controller 10 may include a digital-to-analog converter (DAC) and a buffer as disclosed in [0031] of the applicant’s specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claim limitation of “output controller is configured to generate an analog voltage” of claim 9 invokes 35 USC 112(f) or pre- AIA 35 USC 112, sixth paragraph. However, the written description fails to provide an adequate description of the structure, material, or acts to perform the claimed functions of these limitations. See rejection under 35 USC 112(b) below for further details as to the lack of structure.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitations of: “and configured to generate a first output charge to a seventh output charge”. It is unclear if it is meant to be understood as the first output charge is generated and provided to a seventh output charge in some manner, or if it is meant to be understood as it is configured to generate a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge. For purposes of examination, the Examiner interprets the limitation to mean that it is configured to generate a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge.
Furthermore, claim 1 recites the limitations of: “an adder provided with the first output charge to the seventh output charge”. It is unclear if it is meant to be understood as the first output charge is provided to the seventh output charge, or if it is meant to be understood as an adder is provided with the first output charge, second output charge, third output charge, fourth output charge, fifth output charge, sixth output charge, and seventh output charge. For purposes of examination, the Examiner interprets the limitation to mean that an adder is provided with the first output charge, second output charge, third output charge, fourth output charge, fifth output charge, sixth output charge, and seventh output charge.
Furthermore, claim 1 recites the limitations of: “generate a first summation charge to a fourth summation charge”. It is unclear if it is meant to be understood as a first summation charge is generated and provided to a fourth summation charge in some manner, or if it is meant to be understood as the adder is configured to generate a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge. For purposes of examination, the Examiner interprets the limitation to mean that the adder is configured to generate a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge.
Furthermore, claim 1 recites the limitations of: “generate a first summation charge to a fourth summation charge based on the weight precision bit number and the first output charge to the seventh output charge”. As referenced above, the Examiner interprets “generate a first summation charge to a fourth summation charge” as meant to be understood as the adder is configured to generate a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge. It is unclear if “based on the weight precision bit number and the first output charge to the seventh output charge” is meant to be understood as it is based on the weight precision bit number and the first output charge going to the seventh output charge in some manner, or if it is meant to be understood as the first, second, third, and fourth summation charges are individually all based on the weight precision bit number and the first output charge, second output charge, third output charge, fourth output charge, fifth output charge, sixth output charge, and seventh output charge, or if it is meant to be understood as the adder generates the four summation charges, and in calculating the four summation charges, they each may be generated based on the weight precision bit number and one of, or a combination of the seven output charges (as in each summation charge individually is not necessarily determined using all seven output charges, but all seven output charges are used in the calculation of the four summation charges as a whole). For purposes of examination, the Examiner interprets “generate a first summation charge to a fourth summation charge based on the weight precision bit number and the first output charge to the seventh output charge” to mean, in part as referenced above, the adder is configured to generate a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge, and in calculating the four summation charges, they each may be generated based on the weight precision bit number and one of, or a combination of the seven output charges (as in each summation charge individually is not necessarily determined using all seven output charges, but all seven output charges are used in the calculation of the four summation charges as a whole).
Furthermore, claim 1 recites the limitations of: “configured to generate a first output charge to a seventh output charge based on the first input voltage signal, the second input voltage signal, the third input voltage signal, the first selection signal, and the second selection signal”. As referenced above, the Examiner interprets the portion of the limitations “configured to generate a first output charge to a seventh output charge” to mean it is configured to generate a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge. However, the limitations are further unclear if it is meant to be understood that each individual output charge of the seven output charges are generated based on all of the list of signals, (first input voltage signal, second input voltage signal, third input voltage signal, first selection signal, and second selection signal), or if it is meant to be understood as each output charge of the seven output charges may be generated based on one of, or a combination of the list of signals, (as in each output charge individually is not necessarily determined using all of the signals (the three input voltage signals and the two selection signals), but all of the signals (the three input voltage signals and the two selection signals) are used in the calculation of the seven output charges as a whole). For purposes of examination, the Examiner interprets the limitation to mean, in part as referenced above, “configured to generate a first output charge to a seventh output charge”, it is configured to generate a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge, and that “based on the first input voltage signal, the second input voltage signal, the third input voltage signal, the first selection signal, and the second selection signal” is meant to be understood as each output charge of the seven output charges may be generated based on one of, or a combination of the list of signals, (as in each output charge individually is not necessarily determined using all of the signals (the three input voltage signals and the two selection signals), but all of the signals (the three input voltage signals and the two selection signals) are used in the calculation of the seven output charges as a whole).
Claims 1-9 inherit the same deficiency as claim 1 based on dependence.
Regarding claim 2, claim 2 recites the limitations of: “wherein the memory array includes banks in which first memory cells are arranged in a first column and second memory cells are arranged in a second column to a fourth column”. It is unclear if the memory array comprises banks, or if “the memory array includes banks” is meant to be understood as the memory array works in cooperation with banks in some manner, or if it is meant to be understood as the memory array comprises banks. For purposes of examination, the Examiner interprets the limitation to mean that the memory array comprises banks.
Furthermore, claim 2 recites the limitations of: “second memory cells are arranged in a second column to a fourth column”. It is unclear if the limitation is meant to be understood as second memory cells are arranged in a second column and to a fourth column, or if it is meant to be understood as second memory cells are arranged in a second column, a third column, and a fourth column. For purposes of examination, the Examiner interprets the limitation to be understood as second memory cells are arranged in a second column, a third column, and a fourth column.
Furthermore, claim 2 recites the limitations of: “wherein the memory array includes banks in which first memory cells are arranged in a first column and second memory cells are arranged in a second column to a fourth column”. As referenced above, the Examiner interprets a portion of these limitations to mean that the memory array comprises banks, and that the limitation of “second memory cells are arranged in a second column to a fourth column” is interpreted by the Examiner as second memory cells are arranged in a second column, a third column, and a fourth column. However, it remains further unclear if the limitations of “banks in which first memory cells are arranged in a first column and second memory cells are arranged in a second column to a fourth column” is meant to be understood as throughout the plurality of banks as a whole there are memory cells arranged in a first column, a second column, a third column and a fourth column, or if it is meant to be understood that each individual bank of the plurality of banks comprises memory cells arranged in a first column, a second column, a third column, and a fourth column. For purposes of examination, the Examiner interprets the limitations to mean that each individual bank of the plurality of banks comprises memory cells arranged in a first column, a second column, a third column, and a fourth column.
Claim 3 inherits the same deficiency as claim 2 based on dependence.
Regarding claim 3, claim 3 recites the limitations of: “each of the first output charge to the seventh output charge”. Similarly as with claim 1, It is unclear if it is meant to be understood as the first output charge is generated and provided to a seventh output charge in some manner, or if “the first output charge to the seventh output charge” is meant to be understood as a list of a first output charge, second output charge, third output charge, fourth output charge, fifth output charge, sixth output charge, and seventh output charge. For purposes of examination, the Examiner interprets the limitation, “the first output charge to the seventh output charge”, to mean that it is as a list of a first output charge, second output charge, third output charge, fourth output charge, fifth output charge, sixth output charge, and seventh output charge.
Furthermore, claim 3 recites the limitations of: “the first operation charges to a summation of the seventh operation charges”, it is unclear if it is meant to be understood as the first operation charges are generated and provided to the seventh operation charges in some manner, or if “the first operation charges to a summation of the seventh operation charges” is meant to be understood as, the first operation charges, second operation charges, third operation charges, fourth operation charges, fifth operation charges, sixth operation charges, and seventh operation charges. For purposes of examination the Examiner interprets “the first operation charges to a summation of the seventh operation charges” to be understood as the first operation charges, second operation charges, third operation charges, fourth operation charges, fifth operation charges, sixth operation charges, and seventh operation charges.
Furthermore, claim 3 recites the limitations of: “each of the first output charge to the seventh output charge is a summation of the first operation charges to a summation of the seventh operation charges”. It is unclear if is meant to be understood as the first output charge is a summation of the first operation charges, second operation charges, third operation charges, fourth operation charges, fifth operation charges, sixth operation charges, and seventh operation charges, and similarly the second, output charge, third output charge, fourth output charge, fifth output charge, sixth output charge, and seventh output charge each individually being a summation of all seven of the operation charges, or if it is meant to be understood as the first output charge is a summation of the first operation charges, the second output charge is a summation of the second operation charges, the third output charge is a summation of the third operation charges, the fourth output charge is a summation of the fourth operation charges, the fifth output charge is a summation of the fifth operation charges, the sixth output charge is a summation of the sixth operation charges, and the seventh output charge is a summation of the seventh operation charges. For purposes of examination, the Examiner interprets the limitations of “each of the first output charge to the seventh output charge is a summation of the first operation charges to a summation of the seventh operation charges” to mean the first output charge is a summation of the first operation charges, the second output charge is a summation of the second operation charges, the third output charge is a summation of the third operation charges, the fourth output charge is a summation of the fourth operation charges, the fifth output charge is a summation of the fifth operation charges, the sixth output charge is a summation of the sixth operation charges, and the seventh output charge is a summation of the seventh operation charges.
Furthermore, claim 3 recites the limitations of: “wherein the first memory cells arranged in the first column generate first operation charges, the second memory cells arranged in the second column generate second operation charges and third operation charges, the second memory cells arranged in the third column generate fourth operation charges and fifth operation charges, and the second memory cells arranged in the fourth column generate sixth operation charges and seventh operation charges, and wherein each of the first output charge to the seventh output charge is a summation of the first operation charges to a summation of the seventh operation charges.” Claim 3 is dependent on claims 1 and 2. Claim 1 recites limitations regarding an apparatus comprising a memory array wherein the memory array is configured to “generate a first output charge to a seventh output charge”, as referenced above the examiner interprets this limitation to mean that the memory array is configured to generate a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge. Claim 1 recites the first output charge, second output charge, third output charge, fourth output charge, fifth output charge, sixth output charge, and seventh output charge as singular individual charges (a singular first output charge, singular second output charge and so on). Claim 2 recites limitations “the memory array includes banks in which first memory cells are arranged in a first column and second memory cells are arranged in a second column to a fourth column”, as referenced above, the Examiner interprets the limitations to mean that the memory array comprises banks (plural), and the banks comprise first memory cells, and second memory cells in their claimed arrangements. Claim 3 recites limitations, as interpreted by the Examiner, regarding the first memory cells arranged in the first column producing first operation charges, second memory cells in the second column producing second and third operation charges, second memory cells in the third column producing fourth and fifth operation charges, and second memory cells in the fourth column producing sixth and seventh operation charges, and where the first operation charges are summed to generate the first output charge, the second operation charges are summed to generate the first output charge, the third operation charges are summed to generate the third output charge, the fourth operation charges are summed to generate the fourth output charge, the fifth operation charges are summed to generate the fifth output charge, the sixth operation charges are summed to generate the sixth output charge and the seventh operation charges are summed to generate the seventh output charge. With claim 2 claiming a plurality of banks, “the memory array includes banks”, and as interpreted by the Examiner (as referenced above) with the structure of each bank comprising the first and second memory cells in the claimed arrangement of first, second third, and fourth columns, it is unclear if each of the plurality of banks generate the first operation charges which are part of the summation into a singular first output charge (and similarly with second, third, fourth, fifth, sixth, and seventh operation charges summed to generate a second, third, fourth, fifth, sixth, and seventh output charge respectively), or if claim 3 is meant to replace the limitations of claim 1 regarding a singular first, second, third, fourth, fifth, sixth, and seventh output charge, by meaning that each bank has the claimed structure of first and second memory cells in the claimed arrangement of a first, second, third, and fourth column, and that each of the plurality of banks, each using four columns of memory cells, generates first, second, third, fourth, fifth, sixth, and seventh operation charges, and that each of the plurality of banks produces their own seven operation charges and then sums the first operation charges into their own individual first output charge, second operation charges into a second output charge, third operation charges into a third output charge, fourth operation charges into a fourth output charge, fifth operation charges into a fifth output charge, sixth operation charges into a sixth output charge, and seventh operation charges into a seventh output charge, so that each of the plurality of banks produces a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge so that the memory array itself generates a plurality of first output charges, second output charges, third output charges, fourth output charges, fifth output charges, sixth output charges, and seventh output charges.
Regarding claim 5, claim 5 recites the limitations of: “wherein the adder generates the first summation charge and the second summation charge based on the first output charge to the fourth output charge”. It is unclear if the adder generates the first summation charge and the second summation charge based on the first output charge sent to a fourth output charge in some manner, or if it is meant to be understood as the adder generates the first summation charge and the second summation charge based on the first output charge, the second output charge, the third output charge, and the fourth output charge. For purposes of examination, the Examiner interprets the limitation to mean that the adder generates the first summation charge and the second summation charge based on the first output charge, the second output charge, the third output charge, and the fourth output charge.
Furthermore, claim 5 recites the limitations of: “wherein the adder generates the first summation charge and the second summation charge based on the first output charge to the fourth output charge”. As referenced above, the Examiner interprets the limitation to mean that the adder generates the first summation charge and the second summation charge based on the first output charge, the second output charge, the third output charge, and the fourth output charge. However, it remains unclear if it is meant to be understood as the first and the second summation charge is generated based on the first output charge and the second output charge and the third output charge and the fourth output charge in the similar manner as to claim 1 where the Examiner interpreted the generation of summation charges as a whole are generated using the seven output charges, or if the limitation of claim 5 is meant to be understood as specifically claiming that the first and second summation charges are based on the first, second, third, and fourth output charges. For purposes of examination, the Examiner interprets the limitation in a similar manner as claim 1, where the Examiner interprets the limitation to mean that the first and second summation charges are generated using a plurality of the claimed output charges.
Furthermore, claim 5 recites the limitations of: “wherein the adder generates the first summation charge and the second summation charge based on the first output charge to the fourth output charge”. Claim 5 is dependent on claims 1, and 4. Claim 1 recites the limitation of: “generate a first summation charge to a fourth summation charge based on the weight precision bit number”. Claim 4 recites the limitation of: “wherein the first summation charge is identical to the second summation charge based on the weight precision bit number being 4”. Claim 4 recites a limitation regarding the first summation charge and the second summation charge being based, at least in part, on the weight precision bit number. Claim 1 recites a limitation regarding the first, second, third, and fourth summation charges are based, in part, by the weight precision bit. With the claim 5 limitation of “wherein the adder generates the first summation charge and the second summation charge based on the first output charge to the fourth output charge”, as referenced above, the Examiner interprets as meaning the adder generates the first summation charge and the second summation charge based on the first output charge, the second output charge, the third output charge, and the fourth output charge, it is unclear how this limitation coincides with the limitation of claims 1, and 4 regarding the first and second summation charges being based, at least in part, on the weight precision bit number.
Regarding claim 7, claim 7 recites the limitations of: “wherein the adder generates the first summation charge and the fourth summation charge based on the first output charge to the seventh output charge”. It is unclear if the adder generates the first summation charge and the fourth summation charge based on the first output charge sent to a seventh output charge in some manner, or if it is meant to be understood as the adder generates the first summation charge and the fourth summation charge based on the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge. For purposes of examination, the Examiner interprets the limitation to mean that the adder generates the first summation charge and the fourth summation charge based on the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge.
Furthermore, claim 7 recites the limitations of: “wherein the adder generates the first summation charge and the fourth summation charge based on the first output charge to the seventh output charge”. Claim 7 is dependent on claim 1. Claim 1 recites the limitation of: “generate a first summation charge to a fourth summation charge based on the weight precision bit number and the first output charge to the seventh output charge”. As referenced above, the Examiner interprets the claim 7 limitation of: “wherein the adder generates the first summation charge and the fourth summation charge based on the first output charge to the seventh output charge” as the adder generates the first summation charge and the fourth summation charge based on the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge. Furthermore, as referenced above, the Examiner interprets the claim 1 limitation of: “generate a first summation charge to a fourth summation charge based on the weight precision bit number and the first output charge to the seventh output charge” to mean, the adder is configured to generate a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge, and in calculating the four summation charges, they each may be generated based on the weight precision bit number and one of, or a combination of the seven output charges (as in each summation charge individually is not necessarily determined using all seven output charges, but all seven output charges are used in the calculation of the four summation charges as a whole). Furthermore, Claim 7 is dependent on claim 6. Claim 6 recites the limitation of: “wherein the first summation charge is identical to the fourth summation charge based on the weight precision bit number being 8”. Claim 6 recites a limitation regarding the first summation charge and the fourth summation charge being based, at least in part, on the weight precision bit number. It is unclear how the limitation of claim 7 regarding the first and fourth summation charges each being based on the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge is meant to coincide with the limitations of claims 1 and 6 of the summation charges each generated based on the weight precision bit number and one of, or a combination of the seven output charges (as in each summation charge individually is not necessarily determined using all seven output charges, but all seven output charges are used in the calculation of the four summation charges as a whole).
Regarding claim 9, claim 9 recites the limitations of: “wherein the output controller is configured to generate an analog voltage based on the first summation charge and the fourth summation charge, and generate the output voltage by converting the analog voltage to a digital voltage.” It is unclear if it is meant to be understood as the output controller is generating the analog voltage solely on the first and fourth summation charges, or if the analog voltages are generated based on the first summation charge the fourth summation charge and other charges (second, and third summation charges). For purposes of examination, the Examiner interprets the limitations to mean that the output controller is configured to generate an analog voltage based in part on the first summation charge and the fourth summation charge.
Furthermore, regarding the “output controller” of claim 9, as referenced above, invokes 35 USC 112(f) or pre-AIA 35 USC 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material or acts for performing the entire claimed function. The specification refers to the “output controller” in terms of what it does, its function, versus what it is, its structure, see applicant’s specification [0030], [0036]-[0037]. Furthermore, applicant’s figure 1 reference number (Output controller 50) of the in-memory computing apparatus is merely a black box, without indicating adequate structure to perform all of the described functions of the “output controller”.
Regarding claim 10, claim 10 recites the limitations of: “generating a first output charge to a seventh output charge”. It is unclear if it is meant to be understood as generating a first output charge to go to or become a seventh output charge in some manner, or if it is meant to be understood as generating a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge and a seventh output charge. For purposes of examination, the Examiner interprets the limitation to mean generating a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge and a seventh output charge.
Furthermore, claim 10 recites the limitations of: “generating a first summation charge to a fourth summation charge”. It is unclear if it is meant to be understood as generating a first summation charge which goes to a fourth summation charge in some manner, or if it is meant to be understood as generating a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge. For purposes of examination, the Examiner interprets the limitation to mean generating a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge.
Furthermore, claim 10 recites the limitations of: “the first output charge to the seventh output charge”. It is unclear if it is meant to be understood as it the first output charge which given to the seventh output charge in some manner, or if it is meant to be understood as the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge. For purposes of examination, the Examiner interprets the limitation to mean the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge.
Furthermore claim 10 recites the limitations of: “generating a first output charge to a seventh output charge based on the first input voltage signal, the second input voltage signal, the third input voltage signal, the first selection signal, and the second selection signal”. As referenced above, the Examiner interprets the portion of the limitations “generating a first output charge to a seventh output charge” to mean generating a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge and a seventh output charge. However, the limitations are further unclear if it is meant to be understood that each individual output charge of the seven output charges are generated based on all of the list of signals, (first input voltage signal, second input voltage signal, third input voltage signal, first selection signal, and second selection signal), or if it is meant to be understood as each output charge of the seven output charges may be generated based on one of, or a combination of the list of signals, as in each output charge individually is not necessarily determined using all of the signals (the three input voltage signals and the two selection signals), but all of the signals (the three input voltage signals and the two selection signals) are used in the calculation of the seven output charges as a whole. For purposes of examination, the Examiner interprets the limitation to mean, in part as referenced above, “generating a first output charge to a seventh output charge” to mean generating a first output charge, a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge and a seventh output charge, and that “based on the first input voltage signal, the second input voltage signal, the third input voltage signal, the first selection signal, and the second selection signal” is meant to be understood as each output charge of the seven output charges may be generated based on one of, or a combination of the list of signals, as in each output charge individually is not necessarily determined using all of the signals (the three input voltage signals and the two selection signals), but all of the signals (the three input voltage signals and the two selection signals) are used in the calculation of the seven output charges as a whole.
Furthermore, claim 10 recites the limitations of: “generating a first summation charge to a fourth summation charge based on the first output charge to the seventh output charge and the weight precision bit number”. As referenced above, the Examiner interprets “generating a first summation charge to a fourth summation charge” to mean generating a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge. As referenced above, the Examiner interprets “the first output charge to the seventh output charge”, to mean the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge. However, it is unclear if “based on the weight precision bit number and the first output charge to the seventh output charge” is meant to be understood as the first, second, third, and fourth summation charges are individually all based on the weight precision bit number and the first output charge, second output charge, third output charge, fourth output charge, fifth output charge, sixth output charge, and seventh output charge, or if it is meant to be understood as generating the four summation charges, and in calculating the four summation charges, they each may be generated based on the weight precision bit number and one of, or a combination of the seven output charges as in each summation charge individually is not necessarily determined using all seven output charges, but all seven output charges are used in the calculation of the four summation charges as a whole. For purposes of examination, the Examiner interprets “generating a first summation charge to a fourth summation charge based on the first output charge to the seventh output charge and the weight precision bit number” to mean, in part as referenced above, generating a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge, and in calculating the four summation charges, they each may be generated based on the weight precision bit number and one of, or a combination of the seven output charges as in each summation charge individually is not necessarily determined using all seven output charges, but all seven output charges are used in the calculation of the four summation charges as a whole.
Claims 11-16 inherit the same deficiency as claim 10 based on dependence.
Regarding claim 12, claim 12 recites the limitations of: “generating the first summation charge and the second summation charge based on the first output charge to the fourth output charge”. It is unclear if it is meant to be understood as generating the first summation charge and the second summation charge based on the first output charge sent to a fourth output charge in some manner, or if it is meant to be understood as generating the first summation charge and the second summation charge based on the first output charge, the second output charge, the third output charge, and the fourth output charge. For purposes of examination, the Examiner interprets the limitation to mean generating the first summation charge and the second summation charge based on the first output charge, the second output charge, the third output charge, and the fourth output charge.
Furthermore, claim 12 recites the limitations of: “generating the first summation charge and the second summation charge based on the first output charge to the fourth output charge”. Claim 12 is dependent on claims 10, and 11. Claim 10 recites the limitation of: “generating a first summation charge to a fourth summation charge based on the first output charge to the seventh output charge and the weight precision bit number”. Claim 11 recites the limitation of: “the first summation charge is identical to the second summation charge based on the weight precision bit number being 4”. Claim 11 recites a limitation regarding the first summation charge and the second summation charge being based, at least in part, on the weight precision bit number. Claim 10 recites a limitation regarding the first, second, third, and fourth summation charges are based, in part, by the weight precision bit. With the claim 12 limitation of “generating the first summation charge and the second summation charge based on the first output charge to the fourth output charge”, as referenced above, the Examiner interprets as meaning the generating the first summation charge and the second summation charge based on the first output charge, the second output charge, the third output charge, and the fourth output charge, it is unclear how this limitation coincides with the limitations of claims 10, and 11 regarding the first and second summation charges being based, at least in part, on the weight precision bit number.
Regarding claim 14, claim 14 recites the limitations of: “generating the first summation charge and the fourth summation charge based on the first output charge to the seventh output charge”. It is unclear if it is meant to be understood as the first summation charge and the fourth summation charge are based on the first output charge sent to a seventh output charge in some manner, or if it is meant to be understood as generating the first summation charge and the fourth summation charge based on the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge. For purposes of examination, the Examiner interprets the limitation to mean generating the first summation charge and the fourth summation charge based on the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge.
Furthermore, claim 14 recites the limitations of: “generating the first summation charge and the fourth summation charge based on the first output charge to the seventh output charge”. Claim 14 is dependent on claim 10. Claim 10 recites the limitation of: “generating a first summation charge to a fourth summation charge based on the first output charge to the seventh output charge and the weight precision bit number”. As referenced above, the Examiner interprets the claim 14 limitation of: “generating the first summation charge and the fourth summation charge based on the first output charge to the seventh output charge” generating the first summation charge and the fourth summation charge based on the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge. Furthermore, as referenced above, the Examiner interprets the claim 10 limitation of: “generating a first summation charge to a fourth summation charge based on the first output charge to the seventh output charge and the weight precision bit number” to mean, generating a first summation charge, a second summation charge, a third summation charge, and a fourth summation charge, and in calculating the four summation charges, they each may be generated based on the weight precision bit number and one of, or a combination of the seven output charges as in each summation charge individually is not necessarily determined using all seven output charges, but all seven output charges are used in the calculation of the four summation charges as a whole. Furthermore, Claim 14 is dependent on claim 13. Claim 13 recites the limitation of: “the first summation charge is identical to the fourth summation charge based on the weight precision bit number being 8”. Claim 13 recites a limitation regarding the first summation charge and the fourth summation charge being based, at least in part, on the weight precision bit number. It is unclear how the limitation of claim 14 regarding the first and fourth summation charges each being based on the first output charge, the second output charge, the third output charge, the fourth output charge, the fifth output charge, the sixth output charge, and the seventh output charge is meant to coincide with the limitations of claims 1 and 6 of the summation charges each generated based on the weight precision bit number and one of, or a combination of the seven output charges as in each summation charge individually is not necessarily determined using all seven output charges, but all seven output charges are used in the calculation of the four summation charges as a whole.
Regarding claim 15, claim 15 recites the limitations of: “generating an output voltage based on the first summation charge and the fourth summation charge.” It is unclear if it is meant to be understood as generating the output voltage solely on the first and fourth summation charges, or if the output voltage is generated based on the first summation charge, the fourth summation charge, and other charges (second, and third summation charges). For purposes of examination, the Examiner interprets the limitations to mean generating an output voltage based in part on the first summation charge and the fourth summation charge.
Claim 16 inherits the same deficiency as claim 15 based on dependence.
Regarding claim 16, claim 16 recites the limitations of: “generating the output voltage includes: generating an analog voltage based on the first summation charge and the fourth summation charge; and converting the analog voltage to a digital voltage”. It is unclear if it is meant to be understood as generating the analog voltage solely on the first and fourth summation charges, or if the analog voltage is generated based on the first summation charge, the fourth summation charge, and other charges (second, and third summation charges). For purposes of examination, the Examiner interprets the limitations to mean generating an analog voltage based in part on the first summation charge and the fourth summation charge.
Regarding claim 17, claim 17 recites the limitations of: “second memory cells arranged in a second column to a fourth column”. It is unclear if it is meant to be understood as second memory cells are arranged in a second column and to a fourth column, or if it is meant to be understood as second memory cells are arranged in a second column, a third column and a fourth column. For purposes of examination, the Examiner interprets the limitation to mean that second memory cells are arranged in a second column, second memory cells are arranged in a third column, and second memory cells are arranged in a fourth column.
Furthermore regarding claim 17, claim 17 recites the limitations of: “generate a second output charge to a seventh output charge”. It is unclear if it is meant to be understood as it generates a second output charge provided to a seventh output charge in some manner, or if it is meant to be understood as generate a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge. For purposes of examination, the Examiner interprets the limitation to mean generate a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge.
Furthermore regarding claim 17, claim 17 recites the limitations of: “wherein the first memory cell includes a first static random access memory (SRAM) for storing a sign of a weighting value and a second SRAM”. Earlier in claim 17, the claim recites a plurality of first memory cells, “first memory cells arranged in a first column”. It is unclear if the limitation of “wherein the first memory cell includes a first static random access memory (SRAM) for storing a sign of a weighting value and a second SRAM” is meant to be understood as a particular one of the plurality of first memory cells includes a first static random access memory, and a second SRAM, or if it is meant to be understood as each first memory cell of the plurality of first memory cells includes a first static random access memory, and a second SRAM. Furthermore, It is unclear if “includes” from “wherein the first memory cell includes a first static random access memory (SRAM) for storing a sign of a weighting value and a second SRAM” is meant to be understood as the first memory cell(s) work in some manner of cooperation with SRAM or if it is meant to be understood as the first memory cell(s) comprises a first SRAM and a second SRAM. For purposes of examination, the Examiner interprets the limitation of “wherein the first memory cell includes a first static random access memory (SRAM) for storing a sign of a weighting value and a second SRAM” to mean that each first memory cell of the plurality of first memory cells comprises a first SRAM and a second SRAM.
Furthermore, claim 17 recites the limitations of: “the second memory cell includes a third SRAM for storing either one of a sign or a size of the weighting value and a fourth SRAM”. Earlier in claim 17, the claim recites a plurality of second memory cells, “second memory cells”. It is unclear if the limitation of “the second memory cell includes a third SRAM for storing either one of a sign or a size of the weighting value and a fourth SRAM” is meant to be understood as a particular one of the plurality of second memory cells includes a third SRAM, and a fourth SRAM, or if it is meant to be understood as each second memory cell of the plurality of second memory cells includes a third SRAM, and a fourth SRAM. Furthermore, it is unclear if “includes” from “the second memory cell includes a third SRAM for storing either one of a sign or a size of the weighting value and a fourth SRAM” is meant to be understood as the second memory cell(s) work in some cooperative way with SRAM or if it is meant to be understood as the second memory cell(s) comprises a third SRAM and a fourth SRAM. For purposes of examination, the Examiner interprets the limitation of “the second memory cell includes a third SRAM for storing either one of a sign or a size of the weighting value and a fourth SRAM” to mean that each second memory cell of the plurality of second memory cells comprises a third SRAM and a fourth SRAM.
Furthermore, claim 17 recites the limitations of: “second memory cells arranged in a second column to a fourth column and provided with the first input voltage signal, the second input voltage signal, the third input voltage signal, a first weighting value selection signal, and a second weighting value selection signal”. As referenced above, the Examiner interprets the portion of the limitation “second memory cells arranged in a second column to a fourth column” to mean that second memory cells are arranged in a second column, second memory cells are arranged in a third column, and second memory cells are arranged in a fourth column. However, it remains unclear if “and provided with the first input voltage signal, the second input voltage signal, the third input voltage signal, a first weighting value selection signal, and a second weighting value selection signal” is meant to be understood as each individual second memory cell is provided the three input voltage signals “the first input voltage signal, the second input voltage signal, the third input voltage signal”, and both of the selection signals, “a first weighting value selection signal, and a second weighting value selection signal”, or if it is meant to be understood that each of the two, three and four columns individually are provided the three input voltage signals and the two selection signals, or if it is meant to be understood as the second memory cells are arranged in a second, third and fourth column, and that a second column may be provided with one of, a combination of, or all of the signals (three input signals and two selection signals), and similarly the third column may be provided with one of, a combination of, or all of the signals (three input signals and two selection signals), and similarly the fourth column may be provided with one of, a combination of, or all of the signals (three input signals and two selection signals) such that every one of the signals (three input signals and two selection signals) aren’t necessarily provided to each of the columns (second, third, fourth) individually, but rather that every one of the signals (three input signals and two selection signals) are provided to the three columns (second, third, and fourth) as a whole. For purposes of examination, the Examiner interprets the limitations to mean the second memory cells are arranged in a second column, a third column and fourth column, and that a second column may be provided with one of, a combination of, or all of the signals (three input signals and two selection signals), and similarly the third column may be provided with one of, a combination of, or all of the signals (three input signals and two selection signals), and similarly the fourth column may be provided with one of, a combination of, or all of the signals (three input signals and two selection signals) such that every one of the signals (three input signals and two selection signals) aren’t necessarily provided to each of the columns (second, third, fourth) individually, but rather that every one of the signals (three input signals and two selection signals) are provided to the three columns (second, third, and fourth) as a whole.
Claims 18-22 inherit the same deficiency as claim 17 based on dependence.
Regarding claim 18, claim 18 recites the limitations of: “the first memory cells generate a sign signal”. It is unclear if the limitation is meant to be understood as the combination of first memory cells of the plurality of first memory cells generate a singular sign signal, or if it is meant to be understood as each first memory cell from the plurality of first memory cells generates a sign signal. For purposes of examination, the Examiner interprets the limitation to mean that each first memory cell of the plurality of first memory cells generate a sign signal.
Claims 19-21 inherit the same deficiency as claim 18 based on dependence.
Regarding claim 19, claim 19 recites the limitations of: “the first memory cells generate a sampling signal”. It is unclear if the limitation is meant to be understood as the combination of first memory cells of the plurality of first memory cells generate a singular sampling signal, or if it is meant to be understood as each first memory cell from the plurality of first memory cells generates a sampling signal. For purposes of examination, the Examiner interprets the limitation to mean that each first memory cell of the plurality of first memory cells generate a sampling signal.
Claims 20-21 inherit the same deficiency as claim 19 based on dependence.
Regarding claim 20, claim 20 recites the limitations of: “the first memory cells generate a first operation charge”. It is unclear if the limitation is meant to be understood as the combination of all of the first memory cells generates a singular first operation charge, or if it is meant to be understood as each of the first memory cells generate their own first operation charge. For purposes of examination, the Examiner interprets the limitation to mean that each first memory cell of the plurality of first memory cells generate a first operation charge.
Regarding claim 21, claim 21 recites the limitations of: “the second memory cells generate a first operation charge”. It is unclear if the limitation is meant to be understood as the combination of all of the second memory cells generate a singular first operation charge, or if it is meant to be understood as each of the second memory cells of the plurality of second memory cells generates a first operation charge. For purposes of examination, the Examiner interprets the limitation to mean that each second memory cell of the plurality of second memory cells generate a first operation charge.
Furthermore, claim 21 recites the limitations of: “a second threshold voltage signal is applied to the second memory cells”. It is unclear if it is meant to be understood as the second threshold voltage is applied to certain second memory cells (second memory cells of a second column, or second memory cells of a third column, or second memory cells of a fourth column), or if it is meant to be understood as the second threshold voltage signal is applied to all of the second memory cells of the memory array.
Furthermore, claim 21 recites the limitations of: “a second threshold voltage signal is applied to the second memory cells, and the second memory cells generate a first operation charge based on the second threshold voltage signal”. Claim 21 is dependent on claim 17. Claim 17 recites the limitations of “second memory cells arranged in a second column to a fourth column and provided with the first input voltage signal, the second input voltage signal, the third input voltage signal, a first weighting value selection signal, and a second weighting value selection signal to generate a second output charge to a seventh output charge”. As referenced above, the examiner interprets the claim 17 limitation of “second memory cells arranged in a second column to a fourth column” as meaning second memory cells are arranged in a second column, second memory cells are arranged in a third column, and second memory cells are arranged in a fourth column. Furthermore, as referenced above, the examiner interprets the claim 17 limitation of “generate a second output charge to a seventh output charge” to mean generate a second output charge, a third output charge, a fourth output charge, a fifth output charge, a sixth output charge, and a seventh output charge. With claim 21 dependent on claim 17, it means that there are a plurality of second memory cells, and that the second memory cells are arranged in a second column, a third column and a fourth column. As referenced above, the Examiner interprets the limitation of “the second memory cells generate a first operation charge” to mean each second memory cell of the plurality of second memory cells generate a first operation charge. This would mean that each second memory cell, second memory cells in the second column, second memory cells arranged in the third column, and second memory cells arranged in the fourth column each generate a first operation charge. However, it remains unclear if “a second threshold voltage signal is applied to the second memory cells, and the second memory cells generate a first operation charge based on the second threshold voltage signal” is meant to be understood as the second memory cells each generate the same charge, “a first operation charge”, or if different cells or columns may generate different operation charges. For purposes of examination, the Examiner interprets “a second threshold voltage signal is applied to the second memory cells, and the second memory cells generate a first operation charge based on the second threshold voltage signal” to meant that a threshold voltage signal is applied to second memory cells and that the second memory cells that it is applied to generate their own “first operation charge”.
Regarding claim 22, claim 22 recites the limitations of: “the second memory cells further include a first capacitor and a second capacitor”. It is unclear if the limitation is meant to be understood as all of the second memory cells of the plurality of second memory cells include a singular first capacitor and a second capacitor (they all share), or if it is meant to be understood as each of the second memory cells of the plurality of second memory cells include their a first capacitor and a second capacitor. Furthermore, it is unclear if “include” in the limitation is meant to be understood as the second memory cells work in some manner of cooperation with a first capacitor and a second capacitor, of if it is meant to be understood as the second memory cells comprises a first capacitor and a second capacitor. For purposes of examination, the Examiner interprets “the second memory cells further include a first capacitor and a second capacitor” to mean each of the second memory cells of the plurality of second memory cells comprises a first capacitor and a second capacitor.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, and 10-22 are rejected under 35 U.S.C. 102(a)(1), as being anticipated by Eunyoung et al. (Lee, Eunyoung, et al. "A charge-domain scalable-weight in memory computing macro with dual-SRAM architecture for precision-scalable DNN accelerators." IEEE Transactions on Circuits and Systems I: Regular Papers Volume 68. Issue 8 (2021). Pp 1-12), hereinafter, “Eunyoung”.
With regards to claim 1, Eunyoung teaches:
An in-memory computing apparatus (Fig. 1);
comprising: an input controller provided with an input signal and configured to generate a first input voltage signal, a second input voltage signal, and a third input voltage signal based on the input signal; (Fig. 1 regarding ICDAC & ICtrl, and VIN Buffer together as an input controller; Fig. 13(a) regarding the input controller (ICDAC & ICtrl, and VIN Buffer) receiving an input signal and generating a first input signal (IS), a second input signal (ISb), and a third input signal (VIN); Fig. 2 regarding inner workings of Type 1 Dual-SRAM cell, input signal IS as a first input voltage signal, input signal ISb as a second input voltage signal, and input signal VIN as a third input voltage signal; Fig. 6 regarding the detailed schematic of Type 2 Dual SRAM cell with input signal IS (as a first input signal), ISb (as a second input signal), and VIN (as a third input signal));
a weighting value controller configured to generate a first selection signal and a second selection signal based on a weight precision bit number; (Fig. 8(a) regarding a first selection signal (SE), and a second selection signal (SEb) according to a weight precision bit of 2, 4, and 8; (Page 4 column 1 paragraph 3) regarding the selection signals, (SE, and SEb), generated by the digital controller (as a weighting value controller), and that the selection signals are fixed for each precision);
a memory array provided with the first input voltage signal, the second input voltage signal, and the third input voltage signal from the input controller, (Fig. 1 regarding ICDAC & ICtrl, and VIN Buffer together as an input controller outputting a 3 bit input signal, furthermore regarding a memory array of banks and within a bank type 1 and type 2 cells; Fig. 13(a) regarding the input controller (ICDAC & ICtrl, and VIN Buffer) receiving an input signal and generating a first input signal (IS), a second input signal (ISb),and a third input signal (VIN); (Page 2 column 2 paragraph 3) regarding input signals (IS, and ISb) shared in each row within a bank; Fig. 2 regarding inside a Type 1 memory cell, where it receives the three input voltage signals, (IS, ISb, and VIN));
and provided with the first selection signal and the second selection signal from the weighting value controller, (Fig. 1 regarding selection signals (SE, SEb) input into the memory array Type 2 memory cells; (Page 4 column 1 paragraph 3) regarding the selection signals, (SE, and SEb), generated by the digital controller (as a weighting value controller));
and configured to generate a first output charge to a seventh output charge based on the first input voltage signal, the second input voltage signal, the third input voltage signal, the first selection signal, and the second selection signal; (Fig. 1 regarding ICDAC & ICtrl, and VIN Buffer together as an input controller outputting a 3 bit input signal, furthermore regarding a memory array of banks and within a bank type 1 and type 2 cells; Fig. 13(a) regarding the input controller (ICDAC & ICtrl, and VIN Buffer) receiving an input signal and generating a first input signal (IS), a second input signal (ISb),and a third input signal (VIN); (Page 2 column 2 paragraph 3) regarding input signals (IS, and ISb) shared in each row within a bank; Fig. 2 regarding inside a Type 1 memory cell, where it receives the three input voltage signals, (IS, ISb, and VIN); Fig. 1 regarding selection signals (SE, SEb) input into the memory array Type 2 memory cells; (Page 4 column 1 paragraph 3) regarding the selection signals, (SE, and SEb), generated by the digital controller (as a weighting value controller); Fig. 6 regarding the detailed schematic of the Type 2 memory cell, where it receives/uses the three input voltages, (IS, ISb, and VIN), as well as the two selection signals, (SE, SEb); (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL; Fig. 1 regarding each bank having 7 MBL bits with the Type 1 cell column producing one MBL bit and each Type 2 cell column producing two bits; Fig. 6 regarding Type 2 cell with outputs MBLT2[0], and MBLT2[1]; Fig. 11 regarding seven MBL lines, MBL[0]-MBL[6]);
and an adder provided with the first output charge to the seventh output charge from the memory array (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU; (Page 5) regarding how the SCMU adds the MBL values from the memory array);
and configured to generate a first summation charge to a fourth summation charge based on the weight precision bit number and the first output charge to the seventh output charge. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3]; (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU in accordance to the weight precision bit number).
With regards to claim 2, Eunyoung teaches the in-memory computing apparatus of claim 1, as referenced above.
Eunyoung further teaches:
wherein the memory array includes banks (Fig. 1 regarding Banks 0-7);
in which first memory cells are arranged in a first column and second memory cells are arranged in a second column to a fourth column. (Fig. 1 regarding a first column of Type 1 memory cells as first memory cells, and a second column, a third column, and a fourth column of Type 2 memory cells as second memory cells).
With regards to claim 3, Eunyoung teaches the in-memory computing apparatus of claim 2, as referenced above.
Eunyoung further teaches:
wherein the first memory cells arranged in the first column generate first operation charges, (Fig. 1 regarding a first column of Type 1 memory cells (as first memory cells) and the first output line, MBL[55]; Fig. 2 regarding the detailed schematic of a (single) Type 1 cell (as a first memory cell) with output of each individual Type 1 cell, MBLT1 (as first operation charges); (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL; Fig. 11 regarding seven MBL lines, MBL[0]-MBL[6];Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first operation charges, each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second operation charges, and "B" as third operation charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth operation charges, and "B" as fifth operation charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth operation charges, and "B" as seventh operation charges);
the second memory cells arranged in the second column generate second operation charges and third operation charges, (Fig. 1 regarding a second column made up of Type 2 memory cells (as second memory cells) and the second output line MBL[54:53] indicating two outputs; Fig. 6 regarding the detailed schematic of a (single) Type 2 cell (as a second memory cell) with output of each Type 2 cell, being outputs MBLT2[1] and MBLT2[0] (as second and third operation charges respectively); (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL; Fig. 11 regarding seven MBL lines, MBL[0]-MBL[6]; Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first operation charges, each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second operation charges, and "B" as third operation charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth operation charges, and "B" as fifth operation charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth operation charges, and "B" as seventh operation charges);
the second memory cells arranged in the third column generate fourth operation charges and fifth operation charges, (Fig. 1 regarding a third column made up of Type 2 memory cells (as second memory cells) and the third output line MBL[52:51] indicating two outputs; Fig. 6 regarding the detailed schematic of a (single) Type 2 cell (as a second memory cell) with output of each Type 2 cell, being outputs MBLT2[1] and MBLT2[0] (as fourth and fifth operation charges respectively); (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL; Fig. 11 regarding seven MBL lines, MBL[0]-MBL[6]; Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first operation charges, each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second operation charges, and "B" as third operation charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth operation charges, and "B" as fifth operation charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth operation charges, and "B" as seventh operation charges);
and the second memory cells arranged in the fourth column generate sixth operation charges and seventh operation charges, (Fig. 1 regarding a fourth column made up of Type 2 memory cells (as second memory cells) and the fourth output line MBL[50:49] indicating two outputs; Fig. 6 regarding the detailed schematic of a (single) Type 2 cell (as a second memory cell) with output of each Type 2 cell, being outputs MBLT2[1] and MBLT2[0] (as sixth and seventh operation charges respectively); (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL; Fig. 11 regarding seven MBL lines, MBL[0]-MBL[6]; Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first operation charges, each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second operation charges, and "B" as third operation charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth operation charges, and "B" as fifth operation charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth operation charges, and "B" as seventh operation charges);
and wherein each of the first output charge to the seventh output charge is a summation of the first operation charges to a summation of the seventh operation charges. (Fig. 1 regarding a first column made up of Type 1 memory cells (as first memory cells) and the first output bit line MBL[55], a second column made up of Type 2 memory cells (as second memory cells) and the second output bit line MBL[54:53], a third column made up of Type 2 memory cells (as second memory cells) and the third output bit line MBL[52:51], and the fourth column made up of Type 2 memory cells (as second memory cells) and the fourth output bit line MBL[50:19]; Fig. 2 regarding the detailed schematic of a (single) Type 1 cell (as a first memory cell) with output of each individual Type 1 cell, MBLT1 (as first operation charges); Fig. 6 regarding the detailed schematic of a (single) Type 2 cell (as a second memory cell) with output of each Type 2 cell, being outputs MBLT2[1] and MBLT2[0] (as second and third operation charges for the Type 2 memory cells in column 2 creating MBL[54:53], as fourth and fifth operation charges for the Type 2 memory cells in column 3 creating MBL[52:51], and as sixth and seventh operation charges for the Type 2 memory cells in column 4 creating MBL[50:49]);(Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL; Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first operation charges, each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second operation charges, and "B" as third operation charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth operation charges, and "B" as fifth operation charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth operation charges, and "B" as seventh operation charges).
With regards to claim 4, Eunyoung teaches the in-memory computing apparatus of claim 1, as referenced above.
Eunyoung further teaches:
wherein the first summation charge is identical to the second summation charge based on the weight precision bit number being 4. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3]; (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU in accordance to the weight precision bit number, where MAC[3] (as a first summation charge) is equal to MAC[2] (as a second summation charge) when the weight precision bit is 4).
With regards to claim 5, Eunyoung teaches the in-memory computing apparatus of claim 4, as referenced above.
Eunyoung further teaches:
wherein the adder generates the first summation charge and the second summation charge based on the first output charge to the fourth output charge. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3]; (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU in accordance to the weight precision bit number, where MAC[3] (as a first summation charge) is equal to MAC[2] (as a second summation charge) when the weight precision bit is 4,furthermore regarding MBL[6]-MBL[0] as the seven output charges, furthermore regarding the structure of the adder circuit outputting MAC[3] and MAC[2], furthermore regarding the mathematical equations to calculate the outputs of MAC[3] and MAC[4]; Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first output charges, each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second output charges, and "B" as third output charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth output charges, and "B" as fifth output charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth output charges, and "B" as seventh output charges).
With regards to claim 6, Eunyoung teaches the in-memory computing apparatus of claim 1, as referenced above.
Eunyoung further teaches:
wherein the first summation charge is identical to the fourth summation charge based on the weight precision bit number being 8. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3]; (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU in accordance to the weight precision bit number, where MAC[3] (as a first summation charge) is equal to MAC[0] (as a fourth summation charge) when the weight precision bit is 8, furthermore regarding the structure of the adder circuit outputting MAC[3] and MAC[0], furthermore regarding the mathematical equations to calculate the outputs of MAC[3] and MAC[0]).
With regards to claim 7, Eunyoung teaches the in-memory computing apparatus of claim 6, as referenced above.
Eunyoung further teaches:
wherein the adder generates the first summation charge and the fourth summation charge based on the first output charge to the seventh output charge. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3] (as summation charges); (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU).
With regards to claim 8, Eunyoung teaches the in-memory computing apparatus of claim 1, as referenced above.
Eunyoung further teaches:
further comprising an output controller provided with the first summation charge and the fourth summation charge (Fig. 1 regarding SAR ADC and SCMU; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3] (as summation charges); (Page 5 column 1 paragraph 2) regarding the final outputs of the SCMU (MAC[3]-MAC[0]) are connected to the SAR ADC);
and configure to generate an output voltage. (Fig. 1 regarding SAR ADC; (Page 11 column 2) regarding the SAR ADC generating a final output).
With regards to claim 10 Eunyoung teaches:
A method for operating an in-memory computing apparatus, (Fig. 1);
comprising: generating a first input voltage signal, a second input voltage signal, and a third input voltage signal based on an input signal; (Fig. 1 regarding ICDAC & ICtrl, and VIN Buffer together as an input controller; Fig. 13(a) regarding the input controller (ICDAC & ICtrl, and VIN Buffer) receiving an input signal and generating a first input signal (IS), a second input signal (ISb), and a third input signal (VIN); Fig. 2 regarding inner workings of Type 1 Dual-SRAM cell, input signal IS as a first input voltage signal, input signal ISb as a second input voltage signal, and input signal VIN as a third input voltage signal);
generating a first selection signal and a second selection signal based on a weight precision bit number; (Fig. 8(a) regarding a first selection signal (SE), and a second selection signal (SEb) according to a weight precision bit of 2, 4, and 8; (Page 4 column 1 paragraph 3) regarding the selection signals, (SE, and SEb), generated by the digital controller (as a weighting value controller), and that the selection signals are fixed for each precision);
generating a first output charge to a seventh output charge based on the first input voltage signal, the second input voltage signal, the third input voltage signal, the first selection signal, and the second selection signal; (Fig. 1 regarding ICDAC & ICtrl, and VIN Buffer together as an input controller outputting a 3 bit input signal, furthermore regarding a memory array of banks and within a bank type 1 and type 2 cells; Fig. 13(a) regarding the input controller (ICDAC & ICtrl, and VIN Buffer) receiving an input signal and generating a first input signal (IS), a second input signal (ISb),and a third input signal (VIN); (Page 2 column 2 paragraph 3) regarding input signals (IS, and ISb) shared in each row within a bank; Fig. 2 regarding inside a Type 1 memory cell, where it receives the three input voltage signals, (IS, ISb, and VIN); Fig. 1 regarding selection signals (SE, SEb) input into the memory array Type 2 memory cells; (Page 4 column 1 paragraph 3) regarding the selection signals, (SE, and SEb), generated by the digital controller (as a weighting value controller); Fig. 6 regarding the detailed schematic of the Type 2 memory cell, where it receives/uses the three input voltages, (IS, ISb, and VIN), as well as the two selection signals, (SE, SEb); (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL; Fig. 1 regarding each bank having 7 MBL bits with the Type 1 cell column producing one MBL bit and each Type 2 cell column producing two bits; Fig. 6 regarding Type 2 cell with outputs MBLT2[0], and MBLT2[1]; Fig. 11 regarding seven MBL lines, MBL[0]-MBL[6]);
and generating a first summation charge to a fourth summation charge based on the first output charge to the seventh output charge and the weight precision bit number. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3]; (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU in accordance to the weight precision bit number).
With regards to claim 11, Eunyoung teaches the method for operating an in-memory computing apparatus of claim 10, as referenced above.
Eunyoung further teaches:
wherein the first summation charge is identical to the second summation charge based on the weight precision bit number being 4. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3]; (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU in accordance to the weight precision bit number, where MAC[3] (as a first summation charge) is equal to MAC[2] (as a second summation charge) when the weight precision bit is 4).
With regards to claim 12, Eunyoung teaches the method for operating an in-memory computing apparatus of claim 11, as referenced above.
Eunyoung further teaches:
further comprising generating the first summation charge and the second summation charge based on the first output charge to the fourth output charge. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3]; (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU in accordance to the weight precision bit number, where MAC[3] (as a first summation charge) is equal to MAC[2] (as a second summation charge) when the weight precision bit is 4,furthermore regarding MBL[6]-MBL[0] as the seven output charges, furthermore regarding the structure of the adder circuit outputting MAC[3] and MAC[2], furthermore regarding the mathematical equations to calculate the outputs of MAC[3] and MAC[4]; Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first output charges, each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second output charges, and "B" as third output charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth output charges, and "B" as fifth output charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth output charges, and "B" as seventh output charges).
With regards to claim 13, Eunyoung teaches the method for operating an in-memory computing apparatus of claim 10, as referenced above.
Eunyoung further teaches:
wherein the first summation charge is identical to the fourth summation charge based on the weight precision bit number being 8. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3]; (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU in accordance to the weight precision bit number, where MAC[3] (as a first summation charge) is equal to MAC[0] (as a fourth summation charge) when the weight precision bit is 8, furthermore regarding the structure of the adder circuit outputting MAC[3] and MAC[0], furthermore regarding the mathematical equations to calculate the outputs of MAC[3] and MAC[0]).
With regards to claim 14, Eunyoung teaches the method for operating an in-memory computing apparatus of claim 13, as referenced above.
Eunyoung further teaches:
further comprising generating the first summation charge and the fourth summation charge based on the first output charge to the seventh output charge. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3] (as summation charges); (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU).
With regards to claim 15, Eunyoung teaches the method for operating an in-memory computing apparatus of claim 10, as referenced above.
Eunyoung further teaches:
further comprising generating an output voltage based on the first summation charge and the fourth summation charge. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3] (as summation charges); (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU; Fig. 1 regarding SAR ADC; (Page 11 column 2) regarding the SAR ADC generating a final digital output).
With regards to claim 16, Eunyoung teaches the method for operating an in-memory computing apparatus of claim 15, as referenced above.
Eunyoung further teaches:
wherein generating the output voltage includes: generating an analog voltage based on the first summation charge and the fourth summation charge; (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3] (as summation charges); (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU; Fig. 1 regarding SAR ADC; (Page 8 column 1) regarding generation of voltage VMAC; Fig. 14 regarding VMAC used in ADC operation; (Page 11 column 2) regarding the SAR ADC generating a final digital output);
and converting the analog voltage to a digital voltage. (Fig. 1 regarding the Series-coupled merge unit (SCMU) provided the data from the MBL lines, MBL lines shown to provide 7 bits of data(MBL[55], MBL[51:53], MBL[52:51], MBL[50:49]) as the output charges; Fig. 10 regarding the schematic of the SCMU, where it adds input values to generate MAC[0], MAC[1], MAC[2], MAC[3] (as summation charges); (Page 5) regarding how the SCMU adds the MBL values from the memory array, resulting in MAC[3-0]; Fig. 11 regarding operations of the SCMU; Fig. 1 regarding SAR ADC; (Page 8 column 1) regarding generation of voltage VMAC; Fig. 14 regarding VMAC used in ADC operation; (Page 11 column 2) regarding the SAR ADC generating a final digital output).
With regards to claim 17, Eunyoung teaches:
comprising: first memory cells arranged in a first column (Fig. 1 regarding a first column of Type 1 memory cells (as first memory cells));
and provided with a first input voltage signal, a second input voltage signal, and a third input voltage signal to generate a first output charge; (Fig. 1 regarding ICDAC & ICtrl, and VIN Buffer together as an input controller; Fig. 13(a) regarding the input controller (ICDAC & ICtrl, and VIN Buffer) receiving an input signal and generating a first input signal (IS), a second input signal (ISb), and a third input signal (VIN); Fig. 2 regarding inner workings of Type 1 Dual-SRAM cell, input signal IS as a first input voltage signal, input signal ISb as a second input voltage signal, and input signal VIN as a third input voltage signal; Fig. 1 regarding a first column of Type 1 memory cells (as first memory cells) and the first output line, MBL[55] (as first output charge); Fig. 11 regarding seven MBL lines, MBL[0]-MBL[6] (as containing seven output charges);Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first operation charges; Fig. 2 regarding the detailed schematic of a (single) Type 1 cell (as a first memory cell) with output of each individual Type 1 cell, MBLT1 (as first operation charges); (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL (as referenced above, MBL[55] as the combined column wise charges (making the first output charges) of each of the first operation charges shown from Fig. 10, and Fig. 2));
and second memory cells arranged in a second column to a fourth column and provided with the first input voltage signal, the second input voltage signal, the third input voltage signal, a first weighting value selection signal, and a second weighting value selection signal to generate a second output charge to a seventh output charge, (Fig. 1 regarding ICDAC & ICtrl, and VIN Buffer together as an input controller; Fig. 13(a) regarding the input controller (ICDAC & ICtrl, and VIN Buffer) receiving an input signal and generating a first input signal (IS), a second input signal (ISb), and a third input signal (VIN); Fig. 2 regarding inner workings of Type 1 Dual-SRAM cell, input signal IS as a first input voltage signal, input signal ISb as a second input voltage signal, and input signal VIN as a third input voltage signal; Fig. 1 regarding a second column made up of Type 2 memory cells (as second memory cells) and the second output bit line MBL[54:53] (as second and third output charges respectively), a third column made up of Type 2 memory cells (as second memory cells) and the third output bit line MBL[52:51] (as fourth and fifth output charges respectively), and the fourth column made up of Type 2 memory cells (as second memory cells) and the fourth output bit line MBL[50:19](as sixth and seventh output charges respectively); Fig. 11 regarding seven MBL lines, MBL[0]-MBL[6] (as containing seven output charges);Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second operation charges, and "B" as third operation charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth operation charges, and "B" as fifth operation charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth operation charges, and "B" as seventh operation charges; Fig. 6 regarding the detailed schematic of a (single) Type 2 cell (as a second memory cell) with output of each Type 2 cell, being outputs MBLT2[1] and MBLT2[0] (as second and third operation charges for the Type 2 memory cells in column 2 creating MBL[54:53], as fourth and fifth operation charges for the Type 2 memory cells in column 3 creating MBL[52:51], and as sixth and seventh operation charges for the Type 2 memory cells in column 4 creating MBL[50:49]); (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL (as referenced above, MBL[54:53] as the combined column wise charges (making the second and third output charges respectively) of each of the second and third operation charges (respectively) shown from Fig. 10, and Fig. 6), MBL[52:51] as the combined column wise charges (making the fourth and fifth output charges respectively) of each of the fourth and fifth operation charges (respectively) shown from Fig. 10, and Fig. 6), MBL[50:49] as the combined column wise charges (making the sixth and seventh output charges) of each of the sixth and seventh operation charges (respectively) shown from Fig. 10, and Fig. 6));
wherein the first memory cell includes a first static random access memory (SRAM) for storing a sign of a weighting value ((Page 2 column 2 paragraph 3) regarding the Fig. 1 architecture including a Dual-SRAM macro which includes an SRAM cell array, storing weights in sign and magnitude form; Figure 2 regarding the detailed schematic of type 1 Dual-SRAM left bit as the first SRAM (of the dual SRAM));
and a second SRAM for storing a size of the weighting value, ((Page 2 column 1 paragraph 3) regarding the Fig. 1 architecture including a Dual-SRAM macro which includes an SRAM cell array, storing weights in sign and magnitude form. Furthermore regarding there are 8 SRAM banks and each bank includes a Type 1 Dual-SRAM cells and three columns of Type 2 Dual-SRAM cells; (Page 2 column 2 paragraph 1) regarding each Dual-SRAM cell containing SRAMs; (Page 2 column 2 paragraph 2) regarding further structure of the Dual-SRAM cells, with the left bit of Type 1 cells (as first memory cells) storing a sign bit, and the right bit of Type 1 cells (as first memory cells) as storing magnitude of the weight; Figure 2 regarding the detailed schematic of type 1 Dual-SRAM right bit as the second SRAM (of the dual SRAM));
and wherein the second memory cell includes a third SRAM for storing either one of a sign or a size of the weighting value ((Page 2 column 1 paragraph 3) regarding the Fig. 1 architecture including a Dual-SRAM macro which includes an SRAM cell array, storing weights in sign and magnitude form. Furthermore regarding there are 8 SRAM banks and each bank includes a Type 1 Dual-SRAM cells and three columns of Type 2 Dual-SRAM cells (as second memory cells); (Page 2 column 2 paragraph 1) regarding each Dual-SRAM cell containing SRAMs; (Page 2 column 2 paragraph 2) regarding further structure of the Dual-SRAM cells, with the left bit of Type 2 cells (as second memory cells) storing a sign bit or a magnitude bit, and the right bit of Type 2 cells (as second memory cells) as storing magnitude of the weight; Figure 6 regarding the detailed schematic of Type 2 Dual-SRAM left bit as the third SRAM (of the dual SRAM));
and a fourth SRAM for storing a size of the weighting value. ((Page 2 column 1 paragraph 3) regarding the Fig. 1 architecture including a Dual-SRAM macro which includes an SRAM cell array, storing weights in sign and magnitude form. Furthermore regarding there are 8 SRAM banks and each bank includes a Type 1 Dual-SRAM cells and three columns of Type 2 Dual-SRAM cells (as second memory cells); (Page 2 column 2 paragraph 1) regarding each Dual-SRAM cell containing SRAMs; (Page 2 column 2 paragraph 2) regarding further structure of the Dual-SRAM cells, with the left bit of Type 2 cells (as second memory cells) storing a sign bit or a magnitude bit, and the right bit of Type 2 cells (as second memory cells) as storing magnitude of the weight; Figure 6 regarding the detailed schematic of Type 2 Dual-SRAM right bit as the fourth SRAM (of the dual SRAM)).
With regards to claim 18, Eunyoung teaches the memory array of claim 17, as referenced above.
Eunyoung further teaches:
wherein the first memory cells generate a sign signal based on the first input voltage signal and the sign of the weighting value. ((Page 2 column 2 paragraph 3 - page 3 column 1 paragraphs 1-2) regarding a signal generated that represents the multiplied sign with its transition direction determined by the product of the sign of the input and of the weight. Furthermore regarding the generated signal determined by values from the input voltage signals (IS as a first input voltage signal, and ISb as a second input voltage signal); Table I regarding generated sign signals based on the input voltage signals and sign of the weighting value).
With regards to claim 19, Eunyoung teaches the memory array of claim 18, as referenced above.
Eunyoung further teaches:
wherein, a first threshold voltage signal is applied to the first memory cells, (Fig. 2 regarding the detailed schematic of Type 1 memory cells (as first memory cells), 1/2 VDD as a first threshold voltage signal, VM as a first sampling signal from the sign; Fig. 4 regarding the voltage level generated according to the magnitude of the input and example sampling signal waveforms (VM); Table 1 regarding the relationship between VM and 1/2VDD based on input signal and weight sign; (page 3 column 2 paragraph 2) regarding 1/2VDD as a threshold voltage, with the maximum voltage transition as VC being 1/2VDD);
and the first memory cells generate a sampling signal based on the third input voltage signal and the sign signal. (Fig. 1 regarding ICDAC & ICtrl, and VIN Buffer together as an input controller; Fig. 13(a) regarding the input controller (ICDAC & ICtrl, and VIN Buffer) receiving an input signal and generating a first input signal (IS), a second input signal (ISb), and a third input signal (VIN); Fig. 2 regarding inner workings of Type 1 Dual-SRAM cell, input signal IS as a first input voltage signal, input signal ISb as a second input voltage signal, and input signal VIN as a third input voltage signal; (Page 2 column 2 paragraph 3 - page 3 column 1 paragraphs 1-2) regarding a signal (VS) generated that represents the multiplied sign with its transition direction determined by the product of the sign of the input and of the weight; Table 1 regarding the sampling signal (VM) is determined in part by the third input voltage signal (VIN), and the relationship of VM following VS (sign signal); Fig. 8 regarding the sign bit passing scheme, figure 8(a) showing a sign bit passed from A to B in the Type 1 cell, with B outputting VM (sampling signal)).
With regards to claim 20, Eunyoung teaches the memory array of claim 19, as referenced above.
Eunyoung further teaches:
wherein the first memory cells generate a first operation charge based on the sampling signal. (Fig. 1 regarding a first column of Type 1 memory cells (as first memory cells) and the first output line, MBL[55]; Fig. 2 regarding the detailed schematic of a (single) Type 1 cell (as a first memory cell) with output of each individual Type 1 cell, MBLT1 (as first operation charges), sampling signal VM in the circuit, and signal VC in the circuit to output MBLT1; (Page 3 column 2 paragraph 1) regarding each row has a different amount of charge determined by the input and weight, and charges are combined column wise on the MBL; Fig. 10 regarding the schematic of the SCMU placed in each bank, where each Type 1 cell (as a first memory cell) in a first column shows a capacitor out of a box labeled "B", as first operation charges; (Page 3 column 1 paragraph 2) regarding VM (sampling signal) delivered to signal VC; Fig. 5 as examples of outputs of MBL based on VC; (Page 3 column 2 paragraph 1) regarding VC drives one terminal of the coupling capacitor CC (which the output of CC is the operation charge MBLT1 shown in Fig. 2)).
With regards to claim 21, Eunyoung teaches the memory array of claim 19, as referenced above.
Eunyoung further teaches:
wherein, a second threshold voltage signal is applied to the second memory cells, (Fig. 6 regarding the detailed schematic of Type 2 memory cells (as second memory cells), VDD as a second threshold voltage signal);
and the second memory cells generate a first operation charge based on the second threshold voltage signal. (Fig. 1 regarding a second column made up of Type 2 memory cells (as second memory cells) and the second output line MBL[54:53] indicating two outputs; Fig. 6 regarding the detailed schematic of a (single) Type 2 cell (as a second memory cell) with output of each Type 2 cell, being outputs MBLT2[1] and MBLT2[0] (as second and third operation charges respectively), and threshold voltage VDD used in the circuitry; 10 regarding the schematic of the SCMU placed in each bank, where each Type 2 cell (as a second memory cell) in a second column shows a capacitor out of a box labeled "A", as second operation charges, and "B" as third operation charges, each Type 2 cell (as a second memory cell) in a third column shows a capacitor out of a box labeled "A", as fourth operation charges, and "B" as fifth operation charges, each Type 2 cell (as a second memory cell) in a fourth column shows a capacitor out of a box labeled "A", as sixth operation charges, and "B" as seventh operation charges).
With regards to claim 22, Eunyoung teaches the memory array of claim 17, as referenced above.
Eunyoung further teaches:
wherein the second memory cells further include a first capacitor and a second capacitor, (Fig. 6 regarding the detailed schematic of Type 2 memory cells (as second memory cells), with a first capacitor CC[1], and a second capacitor CC[0]);
and wherein a size of the first capacitor is double a size of the second capacitor. (Fig. 6 regarding the detailed schematic of Type 2 memory cells (as second memory cells), with a first capacitor CC[1], and a second capacitor CC[0] and capacitor CC[1] being 2X and CC[0] being 1X).
Deferring of Indication of Allowable Subject Matter
The Examiner is deferring decision as to prior art and/or indication of allowable subject matter over prior art regarding claim 9 due to the 35 U.S.C. 112(a), 112(b) rejections made to the claim.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s
disclosure:
Jia et al. (U.S. Patent Applicant Publication 2023/0074229 A1)
Fig. 1 shows and in memory computing array with columns made up of cells
Fig. 2B shows schematic of a cell of the memory array, receiving multiple input signals
Fig. 11 shows in-memory computing banks each having N rows and M columns, and using filter weights in calculations
[0076]-[0077] regarding accumulation of output charges from cells
Seemingly does not discuss the sign signal details of the claimed invention, nor the specifics regarding details of certain columns producing certain output charges of the claimed invention
Verma et al (U.S. Patent Application Publication 2021/0271597 A1)
Fig. 1 shows in memory computing array organized in to separate channels
Fig. 3 shows more details of in memory computing including multiple input signals provided to the memory array
Seemingly does not discuss the sign signals details of the claimed invention, nor the specifics regarding details of certain columns producing certain output charges of the claimed invention
Conclusion
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/J.A.K./ Examiner, Art Unit 2182
/EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
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