DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 8, 10, 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Arbel et al (U.S 11784149, Arbel).
As to claim 1, Arbel discloses an electronic device (fig. 1), comprising:
a field-programmable gate array (FPGA) (col 4 lns 38-45 “main chip”) configured to interface with a chiplet (“secondary dies”), the FPGA comprising an interface configurable to interface with a programmable fabric of the FPGA (fig. 1, interface structures 120) based on entering a first mode (fig. 2 “true orientation” of “different orientations”), wherein the first mode comprises configuring a bump assignment orientation in a first direction (fig 3, fig. 7) , or configurable to interface with the chiplet by entering a second mode (“rotated orientation”), wherein the second mode comprises configuring a bump assignment orientation in a second direction (fig. 4, fig. 7, col 7 ln 15-40).
As to claim 4, Arbel discloses the electronic device of claim 1, wherein the first direction comprises a horizontal direction (fig. 1A-B).
As to claim 8, Arbel discloses a system (fig. 2), comprising:
a programmable logic device (fig. die 105), comprising:
a programmable fabric core (fig. 2, circuitry 220A-B); and
a plurality of interfaces ( fig. 1A, 120A-B), each configurable to interface with a respective chiplet (secondary dies 110A-B) using one of a plurality of interface types (fig. 1A, true/rotated orientation types) based on a plurality of modes (fig. 6-7, based on true/rotated mode), wherein the plurality of interfaces comprises a first interface (fig. 1, “true orientation”) and a second interface (“rotated orientation”), wherein the first interface is configurable to communicatively couple the programmable logic device to a first chiplet (die 110A) via the first interface using a first mode of the plurality of modes (“true orientation”), wherein the first mode corresponds to a first microbump assignment configuration (fig. 6, s610-s625, fig. 7);
a second interface configurable to communicatively couple the programmable logic device to a second chiplet (die 110B) via the second interface using a second mode of the plurality of modes (“rotated orientation”), wherein the second mode corresponds to a second microbump assignment configuration (fig. 6, s610-s625, fig. 7).
As to claim 10, Arbel discloses the system of claim 8, wherein the second microbump assignment configuration comprises a plurality of microbumps oriented horizontally (fig. 1A-B).
As to claim 14, Arbel discloses an integrated circuit (fig. 2), comprising:
programmable fabric (die 105); and
mapping circuitry (circuitry 205A, 215A) configured to enable a single interface of the programmable fabric (120A) to interface with a first interface type (“true orientation” type) in a first mode (“true” mode) based on a first microbump assignment of a plurality of microbumps (fig. 6, s610-625, fig. 7) and enable the programmable fabric to interface with a second interface type (“rotated orientation” type) in a second mode (“rotated” mode) based on a second microbump assignment of the plurality of microbumps (fig. 6, s610-625, fig. 7).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Arbel in view of Tang et al (US 20200133902, Tang).
As to claim 2, Arbel discloses the electronic device of claim 1, but does not disclose wherein the first mode causes the bump assignment to be assigned according to an Advanced Interconnect Bus (AIB) standard. In the same field of art (intrasystem connection), Tang discloses various dies configured for data communication, in chiplets, may use various data communication protocols or versions of protocols (par. 7). In one embodiment, Tang discloses a device (fig. 1-2) includes an FPGA die (FPGA die 8) and an Advanced Interconnect Bus (AIB) interconnect circuitry (circuitry 13) to couple to a transceive chiplet (chiplet 10). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Tang, by using AIB standard so that the first mode causes the bump assignment to be assigned according to an Advanced Interconnect Bus (AIB) standard. The motivation is to standardize the system, to improve the flexibility of the system (par. 8).
As to claim 17, Arbel discloses the integrated circuit of claim 14, wherein the mapping circuitry maps the plurality of microbumps in a vertical direction (fig. 2. Note: The microbumps 230 are vertically oriented to the die 105 surface). Arbel does not disclose the first mode comprises an Advanced Interface Bus (AIB) mode. In the same field of art (intrasystem connection), Tang discloses various dies configured for data communication, in chiplets, may use various data communication protocols or versions of protocols (par. 7). In one embodiment, Tang discloses a device (fig. 1-2) includes an FPGA die (FPGA die 8) and an Advanced Interconnect Bus (AIB) interconnect circuitry (circuitry 13) to couple to a transceive chiplet (chiplet 10). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Tang, by comprising the first mode as an Advanced Interface Bus (AIB) mode and, in the AIB mode, the mapping circuitry maps the plurality of microbumps in a vertical direction. The motivation is to standardize the system, to improve the flexibility of the system (par. 8).
Claim 3, 7, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Arbel in view of Publication (Enabling Optical Interconnects Using the New UCIe Standard, Pub).
As to claim 3, Arbel discloses the electronic device of claim 1, but does not disclose wherein the second mode causes the bump assignment to be assigned according to a Universal Chiplet Interconnect Express (UCIe) standard. In the same field of art (intrasystem connection), Pub discloses UCIe is a new die to die inteconnect standard for high-bandwidth, power-efficient and cost-effective connectivity between chiplets (page 3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Pub, by using UCIe standard so that the second mode causes the bump assignment to be assigned according to a Universal Chiplet Interconnect Express (UCIe) standard. The motivation is to improve the performance and the power consumption of the system (page 1).
As to claim 7, Arbel discloses the electronic device of claim 1, but does not disclose the limitations in claim 7. In the same field of art (intrasystem connection), Pub discloses an optical chiplet using Advanced Interface Bus (AIB) as the interface which is compatible with UCIe standards (page 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Pub, by configuring a set of bumps to send and/or receive data according to an Advanced Interconnect Bus (AIB) standard in the first mode and to send and/or receive data according to a Universal Chiplet Interconnect Express (UCIe) standard in the second mode. The motivation is to improve the performance and the power consumption of the system (page 1).
As to claim 18, Arbel discloses the integrated circuit of claim 14, wherein the mapping circuitry maps the plurality of microbumps in a horizontal direction (fig. 2. Note: The microbumps 230 are horizontally oriented to the surface of die 120). Arbel does not disclose the second mode comprises a Universal Chiplet Interconnect Express (UCle) mode. In the same field of art (intrasystem connection), Pub discloses an optical chiplet using Advanced Interface Bus (AIB) as the interface which is compatible with UCIe standards (page 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Pub, by configuring the second mode as a Universal Chiplet Interconnect Express (UCle) mode and, in the UCIe mode, the mapping circuitry maps the plurality of microbumps in a horizontal direction. The motivation is to improve the performance and the power consumption of the system (page 1).
Claims 5, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Arbel in view of Pal et al (US 20180189232, Pal).
As to claim 5, Arbel discloses the electronic device of claim 1, but does not disclose wherein the second direction comprises a vertical direction. In the same field of art (intrasystem connection), Pal discloses a chip comprises a mesh of horizontally-oriented ring interconnect and vertically-oriented ring interconnect (fig. 2B chip 400) wherein each chip tile can correspond to an intersection of a horizontally oriented ring and a vertically oriented ring (par. 53). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Pal, by comprising the second direction as a vertical direction. The motivation is to improve the flexibility of the system.
As to claim 9, Arbel discloses the system of claim 8, but does not disclose wherein the first microbump assignment configuration comprises a plurality of microbumps oriented vertically. In the same field of art (intrasystem connection), Pal discloses a chip comprises a mesh of horizontally-oriented ring interconnect and vertically-oriented ring interconnect (fig. 2B chip 400) wherein each chip tile can correspond to an intersection of a horizontally oriented ring and a vertically oriented ring (par. 53). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Pal, by comprising the first microbump assignment configuration with a plurality of microbumps oriented vertically. The motivation is to improve the flexibility of the system.
Claims 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Arbel in view of Sardella et al (US 6924986, Sardella).
As to claim 11, Arbel discloses the system of claim 8, but does not disclose the limitations in claim 11. In the same field of art (intrasystem connection), Sardella discloses a system which includes a circuit board and a plurality of pluggable modules coupled to the circuit board (col 1 ln 49-55). In one embodiment, Sardella discloses a logic device comprises a set of pins that are configured to send and/or receive clock signals when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode (fig. 10, col 5 lns 50-62). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Sardella, by comprising a set of microbumps that are configured to send and/or receive clock signals when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode. The motivation is to improve the flexibility of the system (col 1 ln 40-43).
As to claim 20, Arbel discloses the integrated circuit of claim 14, but does not disclose the limitations in claim 20. In the same field of art (intrasystem connection), Sardella discloses a system which includes a circuit board and a plurality of pluggable modules coupled to the circuit board (col 1 ln 49-55). In one embodiment, Sardella discloses a logic device comprises a set of pins that are configured to send and/or receive clock signals when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode (fig. 10, col 5 lns 50-62). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Sardella, by configuring one or more microbumps of a plurality of microbumps to send and/or receive clock signals, receive data, receive ready signals, loading signals, or any combination thereof based on a selected mode. The motivation is to improve the flexibility of the system (col 1 ln 40-43).
Claim 12, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Arbel in view of Barot et al (US 20170329737, Barot).
As to claim 12, Arbel discloses the system of claim 8, but does not disclose the limitations in claim 12. In the same field of art (intrasystem connection), Barot discloses methods that bridge between a first full-duplex multi-wire serial interface and a second full-duplex multi-wire serial interface (par. 5). In one embodiment, Barot discloses a set of pins that are configured to send and/or receive ready signals and loading signals when a first interface is operating in the first mode and are configured to transmit or receive data when a second interface is operating in the second mode (fig. 2, par. 47). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Barot, by comprising a set of microbumps that are configured to send and/or receive ready signals and loading signals when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode. The motivation is to improve the functionality of the system (par. 4).
As to claim 19, Arbel discloses the integrated circuit of claim 14, but does not disclose the limitations in claim 19. In the same field of art (intrasystem connection), Barot discloses methods that bridge between a first full-duplex multi-wire serial interface and a second full-duplex multi-wire serial interface (par. 5). In one embodiment, Barot further discloses a state machine (fig. 6, state machine 602), the state machine configured to support link training, lane repair, lane reversal, scrambling, descrambling, sideband training, sideband transfer, or any combination thereof (par. 60). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Barot, by comprising a state machine, the state machine configured to support link training, lane repair, lane reversal, scrambling, descrambling, sideband training, sideband transfer, or any combination thereof. The motivation is to improve the functionality of the system (par. 4).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Arbel in view of Jabori et al (US 20180239718, Jabori).
As to claim 13, Arbel discloses the system of claim 8, but does not disclose the limitations in claim 13. In the same field of art (intrasystem connection), Jabori discloses a mechanism that connects an electronic device to a peripheral device such that information may be exchanged (par. 10). In one embodiment, Jabori discloses a device comprises a set of microbumps that are configured to function as spare bumps when a first interface is operating in a first mode and are configured to transmit or receive data when a second interface is operating in the second mode (par. 30). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and abori, by comprising a set of microbumps that are configured to function as spare bumps when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode. The motivation is to improve the performance of the system (par. 1).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Arbel in view of Cole et al (US 7076016, Cole).
As to claim 15, Arbel discloses the integrated circuit of claim 14, but does not disclose the limitations in claim 15. In the same field of art (data transferring), Cole discloses an analog front end (AFE) (fig. 3), the AFE comprising:
a plurality of input/output (IO) buffers (buffer 340, 355);
transmit circuitry (unit 320-335) configured to transmit data to a first IO buffer of the plurality of IO buffers (col 5 ln 25-30); and
receive circuitry (unit 36-370) configured to receive data from a second IO buffer of the plurality of IO buffers (col 7 ln 35-40). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel and Cole in order to improve the reliability of the system (col 1 ln 30-40).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Arbel in view of Cole and further in view of Barot.
As to claim 16, Arbel/Cole discloses the integrated circuit of claim 15, but does not disclose the limitations in claim 16. In the same field of art (intrasystem connection), Barot discloses methods that bridge between a first full-duplex multi-wire serial interface and a second full-duplex multi-wire serial interface (par. 5). In one embodiment, Barot discloses a mapping circuitry comprises a plurality of multiplexers (fig. 6, mux 606, 616) that comprises: a first subset of the plurality of multiplexers (mux 616) to output data to the transmit circuitry based on a selected mode (par. 60); and a second subset of the plurality of multiplexers (par. 606) to select data received from the receive circuitry from a location based at least in part on the selected mode (par. 60). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Arbel/Cole and Barot, by configuring the mapping circuitry with a plurality of multiplexers that comprises: a first subset of the plurality of multiplexers to output data to the transmit circuitry based
on a selected mode; and a second subset of the plurality of multiplexers to select data received from the receive circuitry from a location based at least in part on the selected mode. The motivation is to improve the functionality of the system (par. 4).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184