DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on the reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 8, 9-10, 14 are rejected under 35 U.S.C. 103 as being unpatentable over
Vilner et al (U.S 20220293500, Vilner) in view of Kang (US 20050235088).
As to claim 1, Vilner discloses an electronic device (fig. 3), comprising:
a first integrated circuit (IC 102) comprising an interface (interface 104) configurable to interface with a second integrated circuit (printed circuit board 302), wherein the interface is configurable in a first mode to assign a first bump signal number sequence (fig. 5, par. 54 for instance, balls 502, 504) oriented in a first direction (“a first orientation”) and configurable in a second mode to assign a second bump signal number sequence (balls 506, 508) oriented in a second direction (“a second orientation”).
Vilner does not disclose the interface is configurable in a first mode according to a first interface protocol and configurable in a second mode according to a second interface protocol. In the same field of art (intrasystem connection), Kang discloses a multi-protocol serial interface system to variably regulate roles of port pins connected to an external system in transmission/reception of serial data using a FPGA, which is applied to various kinds of protocols (par. 11). In one embodiment, Kang discloses an interface is configurable in a first mode according to a first interface protocol and configurable in a second mode according to a second interface protocol (par. 27). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner and Kang, by configuring the interface in a first mode to assign a first bump signal number sequence oriented in a first direction according to a first interface protocol and configuring in the second mode to assign a second bump signal number sequence oriented in a second direction according to a second interface protocol. The motivation is to reduce the cost of the system (par. 10).
As to claim 4, Vilner/Kang discloses the electronic device of claim 1, wherein the first direction comprises a horizontal direction (Vilner, par. 54 “horizontal direction orientation”).
As to claim 5, Vilner/Kang discloses the electronic device of claim 1, wherein the second direction comprises a vertical direction (Vilner, par. 54 “vertical direction orientation”).
As to claim 8, Vilner discloses a system, comprising:
a programmable logic device (fig. 3), comprising:
a programmable fabric core (circuit board 302); and
a plurality of identical interfaces (balls 104), each configurable to interface with a respective chiplet (integrated circuit 102) that has one of a plurality of interface types (par. 53) based on a corresponding plurality of modes (par 54, first/second orientation mode), wherein the plurality of identical interfaces comprises a first interface (for instance, balls 502, 504) and a second interface (balls 506, 508), wherein the first interface and the second interface are configurable to operate in a first mode and a second mode of the plurality of modes (par. 54), wherein the first mode corresponds to a first microbump assignment configuration (fig. 5), the second mode corresponds to a second microbump assignment configuration (par. 54).
Vilner does not disclose the first and second interface as in the claim. In the same field of art (intrasystem connection), Kang discloses a multi-protocol serial interface system to variably regulate roles of port pins connected to an external system in transmission/reception of serial data using a FPGA, which is applied to various kinds of protocols (par. 11). In one embodiment, Kang discloses a programmable logic device (fig. 3), comprising: a programmable fabric core (FPGA 200); and a plurality of identical interfaces (pin array 100) wherein a first interface is configurable to communicatively couple the programmable logic device to a first device that uses a first of the plurality of interface protocols via the first interface using a first mode of the plurality of modes (par 27 “USB”), and a second interface is configurable to communicatively couple the programmable logic device to a second device that used a second of the plurality of interface protocols (“ISO standard”) via the second interface using the second mode of the plurality of modes (par. 27). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner and Kang, by configuring the first interface to communicatively couple the programmable logic device to a first chiplet of the respective chiplets that uses a first of the plurality of interface protocols via the first interface using a first mode of the plurality of modes, wherein the first mode corresponds to a first microbump assignment configuration and the second interface is configurable to communicatively couple the programmable logic device to a second chiplet of the respective chiplets that used a second of the plurality of interface protocols via the second interface using the second mode of the plurality of modes, wherein the second mode corresponds to a second microbump assignment configuration. The motivation is to reduce the cost of the system (par. 10).
As to claim 9, Vilner/Kang discloses the system of claim 8, wherein the first microbump assignment configuration comprises a plurality of microbumps oriented vertically (Vilner, par. 54).
As to claim 10, Vilner/Kang discloses the system of claim 8, wherein the second microbump assignment configuration comprises a plurality of microbumps oriented horizontally (Vilner, par. 54).
As to claim 14, Vilner discloses an integrated circuit (fig. 2), comprising:
programmable fabric (fig. 3); and
mapping circuitry (fig. 9) configured to enable a single interface of the programmable fabric to interface in a first mode (par. 54 “first orientation” mode) based on a first microbump assignment of a plurality of microbumps (fig. 5) and enable the programmable fabric to interface (par. 54 “second orientation”) in a second mode (“second orientation” mode) based on a second microbump assignment of the plurality of microbumps (fig. 5, for instance, balls 506, 508).
Vilner does not disclose the mapping circuitry configured to enable a single interface of the programmable fabric to interface with a first interface standard in a first mode and enable the programmable fabric to interface with a second interface standard in a second mode. In the same field of art (intrasystem connection), Kang discloses a multi-protocol serial interface system to variably regulate roles of port pins connected to an external system in transmission/reception of serial data using a FPGA, which is applied to various kinds of protocols (par. 11). In one embodiment, Kang discloses a mapping circuitry configured to enable a single interface of the programmable fabric to interface with a first interface standard in a first mode (par. 27 “USB” standard) and enable the programmable fabric to interface with a second interface standard in a second mode. (ISO standard). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner and Kang, by configuring the mapping circuitry to enable a single interface of the programmable fabric to interface with a first interface standard in a first mode based on a first microbump assignment of a plurality of microbumps and to enable the programmable fabric to interface with a second interface standard in a second mode based on a second microbump assignment of the plurality of microbumps. The motivation is to reduce the cost of the system (par. 10).
Claims 2, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Vilner in view of Kang and further in view of Tang et al (US 20200133902, Tang).
As to claim 2, Vilner/Kang discloses the electronic device of claim 1, but does not disclose wherein the interface protocol comprises an Advanced Interconnect Bus (AIB) standard. In the same field of art (intrasystem connection), Tang discloses various dies configured for data communication, in chiplets, may use various data communication protocols or versions of protocols (par. 7). In one embodiment, Tang discloses a device (fig. 1-2) includes an FPGA die (FPGA die 8) and an Advanced Interconnect Bus (AIB) interconnect circuitry (circuitry 13) to couple to a transceive chiplet (chiplet 10). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and Tang, by using AIB standard so that the first mode causes the bump assignment to be assigned according to an Advanced Interconnect Bus (AIB) standard. The motivation is to standardize the system, to improve the flexibility of the system (par. 8).
As to claim 17, Vilner/Kang discloses the integrated circuit of claim 14, wherein the mapping circuitry maps the plurality of microbumps in a vertical direction (par. 54) but does not disclose the first mode comprises an Advanced Interface Bus (AIB) mode. In the same field of art (intrasystem connection), Tang discloses various dies configured for data communication, in chiplets, may use various data communication protocols or versions of protocols (par. 7). In one embodiment, Tang discloses a device (fig. 1-2) includes an FPGA die (FPGA die 8) and an Advanced Interconnect Bus (AIB) interconnect circuitry (circuitry 13) to couple to a transceive chiplet (chiplet 10). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and Tang, by comprising the first mode as an Advanced Interface Bus (AIB) mode and, in the AIB mode, the mapping circuitry maps the plurality of microbumps in a vertical direction. The motivation is to standardize the system, to improve the flexibility of the system (par. 8).
Claim 3, 7, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Vilner in view of Kang and further in view of Publication (Enabling Optical Interconnects Using the New UCIe Standard, Pub).
As to claim 3, Vilner/Kang discloses the electronic device of claim 1, but does not disclose wherein the second interface protocol comprises a Universal Chiplet Interconnect Express (UCIe) standard. In the same field of art (intrasystem connection), Pub discloses UCIe is a new die to die inteconnect standard for high-bandwidth, power-efficient and cost-effective connectivity between chiplets (page 3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and Pub, by using UCIe standard so that the second mode causes the bump assignment to be assigned according to a Universal Chiplet Interconnect Express (UCIe) standard. The motivation is to improve the performance and the power consumption of the system (page 1).
As to claim 7, Vilner/Kang discloses the electronic device of claim 1, but does not disclose the limitations in claim 7. In the same field of art (intrasystem connection), Pub discloses an optical chiplet using Advanced Interface Bus (AIB) as the interface which is compatible with UCIe standards (page 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and Pub, by configuring a set of bumps to send and/or receive data according to an Advanced Interconnect Bus (AIB) standard in the first mode and to send and/or receive data according to a Universal Chiplet Interconnect Express (UCIe) standard in the second mode. The motivation is to improve the performance and the power consumption of the system (page 1).
As to claim 18, Vilner/Kang discloses the integrated circuit of claim 14, wherein the mapping circuitry maps the plurality of microbumps in a horizontal direction (fig. 2. Note: The microbumps 230 are horizontally oriented to the surface of die 120), but does not disclose the second mode comprises a Universal Chiplet Interconnect Express (UCle) mode. In the same field of art (intrasystem connection), Pub discloses an optical chiplet using Advanced Interface Bus (AIB) as the interface which is compatible with UCIe standards (page 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and Pub, by configuring the second mode as a Universal Chiplet Interconnect Express (UCle) mode and, in the UCIe mode, the mapping circuitry maps the plurality of microbumps in a horizontal direction. The motivation is to improve the performance and the power consumption of the system (page 1).
Claims 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Vilner in view of Kang and further in view of Sardella et al (US 6924986, Sardella).
As to claim 11, Vilner/Kang discloses the system of claim 8, but does not disclose the limitations in claim 11. In the same field of art (intrasystem connection), Sardella discloses a system which includes a circuit board and a plurality of pluggable modules coupled to the circuit board (col 1 ln 49-55). In one embodiment, Sardella discloses a logic device comprises a set of pins that are configured to send and/or receive clock signals when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode (fig. 10, col 5 lns 50-62). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and Sardella, by comprising a set of microbumps that are configured to send and/or receive clock signals when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode. The motivation is to improve the flexibility of the system (col 1 ln 40-43).
As to claim 20, Vilner/Kang discloses the integrated circuit of claim 14, but does not disclose the limitations in claim 20. In the same field of art (intrasystem connection), Sardella discloses a system which includes a circuit board and a plurality of pluggable modules coupled to the circuit board (col 1 ln 49-55). In one embodiment, Sardella discloses a logic device comprises a set of pins that are configured to send and/or receive clock signals when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode (fig. 10, col 5 lns 50-62). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and Sardella, by configuring one or more microbumps of a plurality of microbumps to send and/or receive clock signals, receive data, receive ready signals, loading signals, or any combination thereof based on a selected mode. The motivation is to improve the flexibility of the system (col 1 ln 40-43).
Claim 12, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Vilner in view of Kang and further in view of Barot et al (US 20170329737, Barot).
As to claim 12, Vilner/Kang discloses the system of claim 8, but does not disclose the limitations in claim 12. In the same field of art (intrasystem connection), Barot discloses methods that bridge between a first full-duplex multi-wire serial interface and a second full-duplex multi-wire serial interface (par. 5). In one embodiment, Barot discloses a set of pins that are configured to send and/or receive ready signals and loading signals when a first interface is operating in the first mode and are configured to transmit or receive data when a second interface is operating in the second mode (fig. 2, par. 47). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and Barot, by comprising a set of microbumps that are configured to send and/or receive ready signals and loading signals when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode. The motivation is to improve the functionality of the system (par. 4).
As to claim 19, Vilner/Kang discloses the integrated circuit of claim 14, but does not disclose the limitations in claim 19. In the same field of art (intrasystem connection), Barot discloses methods that bridge between a first full-duplex multi-wire serial interface and a second full-duplex multi-wire serial interface (par. 5). In one embodiment, Barot further discloses a state machine (fig. 6, state machine 602), the state machine configured to support link training, lane repair, lane reversal, scrambling, descrambling, sideband training, sideband transfer, or any combination thereof (par. 60). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kangand and Barot, by comprising a state machine, the state machine configured to support link training, lane repair, lane reversal, scrambling, descrambling, sideband training, sideband transfer, or any combination thereof. The motivation is to improve the functionality of the system (par. 4).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Vilner in view of Kang and further in view of Jabori et al (US 20180239718, Jabori).
As to claim 13, Vilner/Kang discloses the system of claim 8, but does not disclose the limitations in claim 13. In the same field of art (intrasystem connection), Jabori discloses a mechanism that connects an electronic device to a peripheral device such that information may be exchanged (par. 10). In one embodiment, Jabori discloses a device comprises a set of microbumps that are configured to function as spare bumps when a first interface is operating in a first mode and are configured to transmit or receive data when a second interface is operating in the second mode (par. 30). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang and abori, by comprising a set of microbumps that are configured to function as spare bumps when the first interface is operating in the first mode and are configured to transmit or receive data when the second interface is operating in the second mode. The motivation is to improve the performance of the system (par. 1).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Vilner in view of Kang and further in view of Cole et al (US 7076016, Cole).
As to claim 15, Vilner/Kang discloses the integrated circuit of claim 14, but does not disclose the limitations in claim 15. In the same field of art (data transferring), Cole discloses an analog front end (AFE) (fig. 3), the AFE comprising:
a plurality of input/output (IO) buffers (buffer 340, 355);
transmit circuitry (unit 320-335) configured to transmit data to a first IO buffer of the plurality of IO buffers (col 5 ln 25-30); and
receive circuitry (unit 36-370) configured to receive data from a second IO buffer of the plurality of IO buffers (col 7 ln 35-40). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Viner/Kang and Cole in order to improve the reliability of the system (col 1 ln 30-40).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Vilner in view of Kang/Cole and further in view of Barot.
As to claim 16, Vilner/Kang/Cole discloses the integrated circuit of claim 15, but does not disclose the limitations in claim 16. In the same field of art (intrasystem connection), Barot discloses methods that bridge between a first full-duplex multi-wire serial interface and a second full-duplex multi-wire serial interface (par. 5). In one embodiment, Barot discloses a mapping circuitry comprises a plurality of multiplexers (fig. 6, mux 606, 616) that comprises: a first subset of the plurality of multiplexers (mux 616) to output data to the transmit circuitry based on a selected mode (par. 60); and a second subset of the plurality of multiplexers (par. 606) to select data received from the receive circuitry from a location based at least in part on the selected mode (par. 60). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Vilner/Kang/Cole and Barot, by configuring the mapping circuitry with a plurality of multiplexers that comprises: a first subset of the plurality of multiplexers to output data to the transmit circuitry based on a selected mode; and a second subset of the plurality of multiplexers to select data received from the receive circuitry from a location based at least in part on the selected mode. The motivation is to improve the functionality of the system (par. 4).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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