DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed January 14, 2026
Claims 1,2,4-7,9, and 10 are pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments filed January 14, 2026 have been fully considered but they are not persuasive.
Regarding the interpretations under §112(f) the Examiner respectfully disagrees. Applicant’s statement about the ‘acts’ further supports the interpretation that the claim itself includes means plus function language interpretable under §112(f), and supports the maintaining of this interpretation. Specifically, regarding the arguments related to the interpretations under §112(f) the Examiner respectfully disagrees with applicant's assertions on pages 8-11 of the January 14, 2026 remarks. Applicant's arguments essentially argue that the generic placeholders identified in the previous rejections recite sufficient structure while relying on the function of these elements. Applicant’s argues for example that the “operation context” of the claims conveys structure, an argument that on its face is an example of the interpretation at issue. The claims, as written and described in numerous office actions fail to recite specific structure and the reliance and argument related to their operation context, functionality, and what they are configured to do is, again, all function and fails to overcome the interpretation of these elements properly under §112(f) as generic placeholders. Additionally, The Remarks, applicant argues “"a communicator", "an interrupt signal generator", "a tick count detector" and "a calibrator" have a sufficiently definite meaning as the name for the structures that perform the functions.” (Remarks of Sep. 29, 2025 Page 8). Importantly, this is not a rejection for indefiniteness under §112(b) but an interpretation under §112(f). The question of indefiniteness is irrelevant to this interpretation. Instead, the Examiner maintains that the claim terms are generic placeholders as understood under §112(f).
The claim terms do not recite structure but instead serve as a generic placeholder for more specific structures like a mircocontroller or logic circuit or the like, only recited in the specification. As such, these arguments are not persuasive and the interpretations under §112 are maintained. Applicant has the opportunity to amend to include structures for each generic placeholder in question, for example mincrocontrollers and/or logic circuits, but where the claim recites generic placeholders, proper interpretation under §112 is maintained.
Regarding the rejection under §103, the Examiner again respectfully disagrees. Specifically, In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Here, Applicant makes several pages of arguments against rejection mappings the Examiner did not apply, but fails to address those specifically set forth with respect to the contested limitations. Specifically, regarding the limitations newly added to the independent claims, the Examiner set forther specific citations to Suzuki ¶¶47-48, ¶¶59-62 regarding the receiving of start and ending execution ticks which are subtracted, and further ¶35 of Rajagopal teaching dividing execution spans by a processor speed value. As Applicant’s arguments are not persuasive in addressing this specific proposed combination, the rejection is respectfully maintained.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the elements in claim 1 including the “communicator”, “interrupt signal generator”, “tick count detector” and “calibrator.”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,2,5,9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Yim”(US PG Pub 2007/0266376) in view of “Suzuki” (US PG Pub 2015/0339208) and further in view of “Rajagopal” (US PG Pub 2002/0143998).
Regarding Claim 1, Yim teaches;
1. A debug device, comprising: a communicator configured to perform data communication with debug interface of a storage device; (See e.g. 518 Fig. 5, ¶51 teaching a hardware debugger system with a jtag interface to interface with a target system)
an interrupt signal generator coupled to the communicator configured to output, when a request to measure an operation time for an instruction is received, an interrupt signal for controlling an interrupt operation of a processor cored included in the storage device through the communicator; (300, Fig. 3, 314, ¶44 Yim teaches a system for setting breakpoints including hardware/software interrupts for debugging including measuring tick values of processing time of the system ¶¶46-48).
a tick count detector coupled to the communicator configured to: receive first tick counts respectively (Yim teaches measuring tick values of processing time of the system ¶¶46-48).
and receive second tick counts respectively (Yim teaches measuring tick values of processing time of the system ¶¶46-48).
wherein the instruction is executed after the interrupt operation is completed.(Yim e.g. 706 Fig. 7A and 806 Fig. 8 teaches the CPU continuing to execute the next instructions after processing of cpus stops at breakpoints)
Yim does not explicitly teach, but Suzuki teaches:
corresponding to a start time point and an end time point of the interrupt operation through the communicator, (see e.g. ¶¶45-50 teaches a process of recording start and end times for the various processes including the interrupting processes as illustrated further in e.g. Fig. 6)
corresponding to a start time point and an end time point of executing the instruction through the communicator; (see e.g. ¶¶45-50 teaches a process of recording start and end times for the various processes including the interrupting processes as illustrated further in e.g. Fig. 6; e.g. in Fig. 6, ¶¶57-62 teaches recording of times for start and end of interrupts and restarting of processes (e.g. SL2) after interrupt is completed)
and a calibrator configured to determine the operation time using the first tick counts and the second tick counts. (Suzuki ¶¶47-48, ¶¶59-62 teaches adding and subtracting the recorded start and stop execution times of the different processes to determine the actual execution time of the process).
wherein the calibrator determines the operation time by: acquiring a subtraction value by subtracting a difference between the first tick counts from a difference between the second tick counts, (Suzuki ¶¶47-48, ¶¶59-62 teaches adding and subtracting the recorded start and stop execution times of the different processes to determine the actual execution time of the process). In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Suzuki as each is directed to performance debugging systems and Suzuki recognized “an accurate execution time of the interrupted process cannot be measured unless the execution time of the other process is subtracted from the time measured by the hardware timer” (¶6).
Suzuki does not teach, but Rajagopal teaches:
and acquiring the operating time by dividing the subtraction value by a speed of the processor core received through the communicator. (Rajagopal e.g. ¶35 teaches dividing tick values by the processor values to accommodate for different processor speeds in calculating processing time; see further e.g. ¶¶32-34)
In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Rajagopal as each is directed to retrieving and maintaining tick count values and Rajagopal recognized a method by which ” the difference in processor speed can quickly be accommodated.” (¶35).
Regarding Claim 2, Yim et al teach the limitations of claim 1 above, but do not further teach, while Rajagopal teaches:
2. The debug device according to claim 1, wherein the interrupt operation is an operation in which a processor core of the storage device stores tick counts in a register of the storage device. (Rajagopal ¶14 teaches storing tick values in a processor register for retrieval)
in addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Rajagopal as each is directed to retrieving and maintaining tick count values and Rajagopal recognized use of registers to store tick values allows the values to be “updated at the speed of the microprocessor. The value can be read from the register with a standard, simple, assembly language instruction.” (¶14).
Regarding Claim 5, Yim further teaches:
5. The debug device according to claim 1, wherein the communicator is configured to communicate with the debug interface according to a joint test action group (JTAG) standard. (See 518, Fig. 5, ¶¶50-51 of Yim teaches use of a JTAG based debug interface for debugging the target system)
Regarding Claim 9, Yim further teaches:
A debug method, comprising: transmitting, when a request to measure an operation time for an instruction is received, an interrupt signal for controlling an interrupt operation to a controller of a storage device through a debug interface of the storage device; (300, Fig. 3, 314, ¶44 Yim teaches a system for setting breakpoints including hardware/software interrupts for debugging including measuring tick values of processing time of the system ¶¶46-48).
performing, by the processor core, the interrupt operation of storing tick counts in a register included in the controller; (Yim teaches measuring tick values of processing time of the system ¶¶46-48).
acquiring first tick counts (Yim teaches measuring tick values of processing time of the system ¶¶46-48).
acquiring second tick counts (Yim teaches measuring tick values of processing time of the system ¶¶46-48).
executing, by the processor core, the instruction after the interrupt operation is completed (Yim e.g. 706 Fig. 7A and 806 Fig. 8 teaches the CPU continuing to execute the next instructions after processing of cpus stops at breakpoints).
and executing, by the processor core, the instruction after the interrupt operation is completed. (Yim ¶¶44-46 describe setting breakpoints which include interruption of the executing tasks as illustrated in e.g. fig. 4, including resumption of the tasks after the interruption handler completion; and further see 706 Fig. 7A and 806 Fig. 8)
Yim does not explicitly teach, but Suzuki teaches:
respectively corresponding to a start time point and an end time point of the interrupt operation through the debug interface; (see e.g. ¶¶45-50 teaches a process of recording start and end times for the various processes including the interrupting processes as illustrated further in e.g. Fig. 6)
respectively corresponding to a start time point and an end time point of executing the instruction through the debug interface; (see e.g. ¶¶45-50 teaches a process of recording start and end times for the various processes including the interrupting processes as illustrated further in e.g. Fig. 6)
and determining the operation time using the first tick counts and the second tick counts. (Suzuki ¶¶47-48, ¶¶59-62 teaches adding and subtracting the recorded start and stop execution times of the different processes to determine the actual execution time of the process).
wherein the determining the operating time comprises: obtaining a subtraction value by subtracting a difference between the first tick counts from a difference between the second tick counts; (Suzuki ¶¶47-48, ¶¶59-62 teaches adding and subtracting the recorded start and stop execution times of the different processes to determine the actual execution time of the process). In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Suzuki as each is directed to performance debugging systems and Suzuki recognized “an accurate execution time of the interrupted process cannot be measured unless the execution time of the other process is subtracted from the time measured by the hardware timer” (¶6).
Suzuki does not teach, but Rajagopal teaches:
and acquiring the operating time by dividing the subtraction value by a speed of the processor core. (Rajagopal e.g. ¶35 teaches dividing tick values by the processor values to accommodate for different processor speeds in calculating processing time; see further e.g. ¶¶32-34))
In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Rajagopal as each is directed to retrieving and maintaining tick count values and Rajagopal recognized a method by which “the difference in processor speed can quickly be accommodated.” (¶35).
Regarding Claim 10, Yim further teaches:
10. The debug method according to claim 9, further comprising: suspending, by a processor core, all operations, which are performed in the controller, in response to the interrupt signal; (Yim ¶¶44-46 describe setting breakpoints which include interruption of the executing tasks as illustrated in e.g. fig. 4)
the interrupt operation is an operation in which the processor core of storing tick counts in a register included in the controller; (Yim teaches measuring tick values of processing time of the system ¶¶46-48).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Yim”(US PG Pub 2007/0266376) in view of “Suzuki” (US PG Pub 2015/0339208) further in view of “Rajagopal” (US PG Pub 2002/0143998) as applied above and further in view of “Kim” (US PG Pub 2019/00227907).
Regarding Claim 4, Yim et al teach the limitations of claim 1 above but do not further teach, while Kim teaches:
4. The debug device according to claim 1, wherein the communicator is coupled to an additional debug interface different from a host interface coupled to a host device among a plurality of ports included in the storage device. (See Kim 160, Fig. 6, ¶¶4,8 Kim teaches a debugging port of the storage device 100 coupled to the debug device 300 separate from ports connected to host 200, including ports of the storage device described in Fig. 5a/5b, ¶40).
In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Kim as each is directed to debugging systems and Kim recognized with ever increasing computer performance “A separate debugging technique for extracting error information may be used to detect or correct such errors” (¶4).
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Blaine” (US PG Pub 2013/0212425) in view of (“Yim”(US PG Pub 2007/0266376) and “Suzuki” (US PG Pub 2015/0339208) and further in view of “Rajagopal” (US PG Pub 2002/0143998).
Regarding Claim 6, Blaine teaches:
6. A debug system, comprising:
a storage device including a memory device, a controller configured to control the memory device, and a debug interface; (Blaine Fig. 2, 202, Fig. 2 213, 212, debug interface 205, fig 2. ¶25)
a debug device (Blaine 215, Fig. 2 ¶27)
and a host device configured to: output the request to the debug device, (Blaine 217, Fig. 2 teaches e.g. issuing commands to debugger device 215 in ¶25)
Blaine does not explicitly teach, but Yim teaches:
configured to output, when a request to measure an operation time for an instruction is received, an interrupt signal for controlling an interrupt operation to the controller through the debug interface, (300, Fig. 3, 314, ¶44 Yim teaches a system for setting breakpoints including hardware/software interrupts for debugging including measuring tick values of processing time of the system ¶¶46-48).
acquire first tick counts (Yim teaches measuring tick values of processing time of the system ¶¶46-48)
acquire second tick counts (Yim teaches measuring tick values of processing time of the system ¶¶46-48)
wherein the instruction is executed after the interrupt operation is completed. (Yim e.g. 706 Fig. 7A and 806 Fig. 8 teaches the CPU continuing to execute the next instructions after processing of cpus stops at breakpoints)
In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Blaine with those of Yim as each is directed to debugging systems and Yim recognized “conventional hardware debugging technique cannot provide advanced debugging capabilities such as a debugging capability for securing stability, which is valued in the course of software development, such as a debugging of temporarily occurring transient faults. The temporary faults can be caused by an asynchronous control flow, such as interrupt, and synchronizing and communication between tasks” (¶12).
Blaine further does not teach but Suzuki teahes:
…respectively corresponding to a start time point and an end time point of the interrupt operation through the debug interface, …(see e.g. ¶¶45-50 teaches a process of recording start and end times for the various processes including the interrupting processes as illustrated further in e.g. Fig. 6)
…respectively corresponding to a start time point and an end time point of executing the instruction through the debug interface, and output the first tick counts and the second tick counts; (see e.g. ¶¶45-50 teaches a process of recording start and end times for the various processes including the interrupting processes as illustrated further in e.g. Fig. 6)
and determine the operation time using the first tick counts and the second tick counts received from the debug device as a response to the request. (Suzuki ¶¶47-48, ¶¶59-62 teaches adding and subtracting the recorded start and stop execution times of the different processes to determine the actual execution time of the process).
wherein the determining the operating time comprises: obtaining a subtraction value by subtracting a difference between the first tick counts from a difference between the second tick counts; (Suzuki ¶¶47-48, ¶¶59-62 teaches adding and subtracting the recorded start and stop execution times of the different processes to determine the actual execution time of the process). In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Suzuki as each is directed to performance debugging systems and Suzuki recognized “an accurate execution time of the interrupted process cannot be measured unless the execution time of the other process is subtracted from the time measured by the hardware timer” (¶6).
Suzuki does not teach, but Rajagopal teaches:
and acquiring the operating time by dividing the subtraction value by a speed of the processor core. (Rajagopal e.g. ¶35 teaches dividing tick values by the processor values to accommodate for different processor speeds in calculating processing time; see further e.g. ¶¶32-34)
In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Rajagopal as each is directed to retrieving and maintaining tick count values and Rajagopal recognized a method by which “the difference in processor speed can quickly be accommodated.” (¶35).
Regarding Claim 7, Yim further teaches:
7. The debug system according to claim 6, wherein the controller comprises: a processor core configured to perform the interrupt operation and execute the instruction; (300, Fig. 3, 314, ¶44 Yim teaches a system for setting breakpoints including hardware/software interrupts for debugging including measuring tick values of processing time of the system ¶¶46-48) In addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Blaine with those of Yim as each is directed to debugging systems and Yim recognized “conventional hardware debugging technique cannot provide advanced debugging capabilities such as a debugging capability for securing stability, which is valued in the course of software development, such as a debugging of temporarily occurring transient faults. The temporary faults can be caused by an asynchronous control flow, such as interrupt, and synchronizing and communication between tasks” (¶12).
Blaine et al do not teach, but Rajagopal teaches:
and a register configured to store the first tick counts and the second tick counts through the processor core, and wherein the interrupt operation is an operation in which the processor core stores the tick counts in the register. (Rajagopal ¶14 teaches storing tick values in a processor register for retrieval)
in addition, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the application to combine the teachings of Yim and Rajagopal as each is directed to retrieving and maintaining tick count values and Rajagopal recognized use of registers to store tick values allows the values to be “updated at the speed of the microprocessor. The value can be read from the register with a standard, simple, assembly language instruction.” (¶14).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The attached PTO-892 form includes prior art relevant to applicant’s disclosures related to interrupt signal generator systems for us in debug devices systems.Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW J BROPHY whose telephone number is (571)270-1642. The examiner can normally be reached Monday-Friday, 9am-4:30pm.
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MJB
3/31/2026
/MATTHEW J BROPHY/ Primary Examiner, Art Unit 2191