Office Action Predictor
Last updated: April 16, 2026
Application No. 18/077,131

MECHANISM TO OVERRIDE STANDBY POWER IN LARGE MEMORY CONFIGURATION OF WORKSTATIONS TO ELIMINATE THE NEED TO INCREASE POWER OF STANDBY POWER RAIL

Non-Final OA §103
Filed
Dec 07, 2022
Examiner
MYERS, PAUL R
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
91%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
606 granted / 768 resolved
+23.9% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
19 currently pending
Career history
787
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
64.7%
+24.7% vs TC avg
§102
13.0%
-27.0% vs TC avg
§112
8.0%
-32.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 768 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al PN 2013/0016578 in view of Porzio et al PN 2023/0041215. In regards to claim 15: Wu et al teaches circuitry to detect a number of memory modules (Abstract: “The BIOS controls the control chip to output a control signal according to the number of the memory modules mounted in memory slots”) on a printed circuit board (PCB) (motherboard [0004] “These memory modules receive voltage from a voltage regulator arranged on a motherboard of the computer system through the memory slots”), wherein the PCB comprises slots for memory modules (memory slots), and the circuitry is to detect a number of the slots having memory modules installed (“output a control signal according to the number of the memory modules mounted in memory slots”); make a determination of whether a power requirement of the memory modules exceeds a threshold based on the number of memory modules ([0012] “When the number of the memory modules 20 mounted in the memory slots 60 is greater than 3 and less than 6, the power supply mode of the voltage regulator 40 is regulated to a two-phase power mode. When the number of the memory modules 20 mounted in the memory slots 60 is greater than 6, the power supply mode of the voltage regulator 40 is regulated to a full multiphase power mode”); and assert a signal which indicates whether the power requirement of the memory modules exceeds the threshold (signal for greater than 3 and second signal for greater than 6). Wu et al only teaches a “control unit”. Wu et al does not expressly state the control unit being a processor executing instructions. Porzio et al teaches a power control unit that is a processor executing instructions. ([0103] “In some examples, an apparatus as described herein may perform a method or methods, such as the method 600. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a first command to exit a first power mode and enter a second power mode, the first power mode having a lower power consumption than the second power mode”). It would have been obvious to use a processor with instructions to change the power modes of Wu et al because this would have allowed for the ability to change operation without having to change hardware. In regards to claim 19: Wu et al teaches the memories being DIMMs. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al PN 2013/0016578 in view of Porzio et al PN 2023/0041215 as applied to claim 15 above, and further in view of Tanaka et al PN 2013/0124888. In regards to claim 16: Wu et al does not take into account the characteristics of the memory modules. Tanaka et al teaches ([0606] “When the processing power is estimated based on the operating states and independent characteristics of the flash memories 26 instead of simply summing the power levels, the estimated power level can be more accurate”). It would have been obvious to take into account the characteristics of the memory modules for switching the power because this would have made the power requirement “more accurate”. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al PN 2013/0016578 in view of Porzio et al PN 2023/0041215 and Tanaka et al PN 2013/0124888 as applied to claim 16 above, and further in view of Barr et al PN 2005/0044440. In regards to claim 17: Tanaka et al only states “characteristics” without including maximum frequency. Tanaka et al also mentioned adjusting the operating frequency however does not expressly state that maximum frequency is included in the characteristics of the memory modules. Barr et al teaches ([0046] “Field can 306 contain information about power consumption characteristics of the device or memory unit. This can include minimum, average and maximum power consumption, as well as power consumption correlated to clock frequency. This correlation can be in the form of, for example, a table or formula” “This can include minimum, average and maximum clock frequencies, at which the device or memory unit can operate”). It would have been obvious to include maximum operational frequency of the memories because operating frequencies are related to power consumption. Allowable Subject Matter Claim 1-14 allowed. Claim 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: References were found that counted the number of memory modules such as Wu et al PN 2013/0016578 and Kalb et al PN 6,008,665 that adjusts termination resistance based upon the number of memory slots occupied. Also references were found that taught multiple power states/modes with separate main power and auxiliary power. Such as Chary PN 6,560,713, Seligman PN 2009/0079265 and York PN 2016/0062433. A references was even found taught operating on a secondary/aux power in “economy” mode. Dulsrea PN 2024/0097484 ([0157] “If the chosen operating mode is the economy mode MODECO, the method comprises determining STP13, with the controller 25, whether the necessary power Wnec is less than or greater than or equal to the available power Pwdt. When the necessary power Wnec is less than the available power Pwdt, the controller 25 transmits a signal to at least one or indeed each electric machine 21 to implement the economy mode MODECO. If this is not the case, the controller 25 transmits a signal to at least one or indeed each electric machine 21 to implement the standby mode MODV. Optionally, the alerter emits an alert to inform the pilot of this”). However this is not reconnecting the primary power if the auxiliary/secondary power is inadequate. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL R MYERS whose telephone number is (571)272-3639. The examiner can normally be reached telework M-F start 7-8 leave 4-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Paul R. MYERS/ Primary Examiner, Art Unit 2176
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Prosecution Timeline

Dec 07, 2022
Application Filed
Jan 25, 2023
Response after Non-Final Action
Dec 19, 2025
Non-Final Rejection — §103
Mar 30, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
91%
With Interview (+12.1%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 768 resolved cases by this examiner. Grant probability derived from career allow rate.

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