Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 4 10 and 23 is objected to because of the following informalities:
Claim 4 recites “a hardware description language that maps to circuits into the assembly code”. It is believed this would be better written as “a hardware description language that maps to circuits in the assembly code”.
Claims 10 and 23 recite language similar to that of claim 4 and are thus similarly objected to.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 10 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “wherein the compiler is further configured to compile the inline software code coded in a hardware description language that maps to circuits into the assembly code”. There is no antecedent basis for the term “the inline software code coded in a hardware description language”.
For the purposes of this examination the claim will be understood as reciting, e.g., “wherein the inline software code is coded in a hardware description language and the compiler is further configured to compile the inline software code coded in a hardware description language that maps to circuits into the assembly code”.
Claims 10 and 23 recite language similar to that of claim 4 and are thus similarly rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7, 9, 11, 13, 22, 24 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0169294 to Brock et al. (Brock) in view of US 2018/0173529 to Tamir et al. (Tamir).
Claims 1, 9 and 22: Brock discloses a processor circuit comprising a compiler, wherein the compiler is configured to:
receive a software program that comprises software code coded in an assembly language and inline software code coded in a high-level programming language (par. [0034] “The labeled assembler source file can include the assembler source file and the annotations written in high level code”);
compile the inline software code coded in the high-level programming language within the software program into assembly code in the assembly language (par. [0049] “compile the annotation index source 520 and one or more extracted routine files 516 into machine readable code”); and
compile the assembly code and the software code coded in the assembly language into machine code for the processor circuit (par. [0033] “convert the labeled assembler source file 118 into … machine readable code”).
Brock does not disclose:
compiling the inline software code in the high-level programming language into assembly code in the assembly language.
Tamir teaches:
compiling inline software code coded in a high-level programming language into assembly code in an assembly language (par. [0054] “the program 115, written in a high-level programming language … generate an assembly code file 149”); and
compiling the assembly code into machine code for a processor circuit (par. [0054] “assemble the assembly code file 149 … to generate an object file 151”).
It would have been obvious before the effective filing date of the claimed invention to compile the high-level programming language code into assembly code and then machine code. Those of ordinary skill in the art would have been motivated to do so as a known alternative means of generating the machine readable code which would have produced only the expected results (Brock par. [0049] “compile … into machine readable code”, Tamir par. [0054] “object file 151 (in machine code)”).
Claim 2: Brock and Tamir teach the processor circuit of claim 1, wherein the processor circuit is configured to execute the machine code (Brock par. [0046] “an executable object file”, Tamir par. [0025] “a processor and/or memory”).
Claims 3, 11 and 24: Brock and Tamir teach claims 1, 9 and 22, wherein the compiler is further configured to compile the inline software code coded in a C programming language into the assembly code (Brock par. [0032] “C++”).
Claim 5: Brock and Tamir teach claim 1, wherein the compiler is further configured to identify the inline software code in the software program based on a predefined identifier that is placed at a start of each line of the inline software code (Brock par. [0035] “The special comment form “##” … “##@”).
Claims 7, 13 and 26: Brock and Tamir teach claims 1, 9 and 22, wherein the compiler is further configured to extract variable declarations from the software code coded in the assembly language to identify variables used in the inline software code (e.g. Brock par. [0045] “resolving symbolic names for memory locations and other entities”, par. [0051] “maintaining internal variables”).
Claim(s) 4, 10 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0169294 to Brock et al. (Brock) in view of US 2018/0173529 to Tamir et al. (Tamir) in view of US 2020/0371787 to Gupta et al. (Gupta).
Claims 4, 10 and 23: Brock and Tamir teach claims 1, 9 and 22, but do not explicitly teach wherein the compiler is further configured to compile the inline software code coded in a hardware description language that maps to circuits into the assembly code.
Gupta teaches:
compiling software code coded in a hardware description language that maps to circuits into the assembly code (par. [0325] “HDLs … create a definition of a digital circuit design that may be compiled”).
It would have been obvious before the effective filing date of the claimed invention to compile inline HDL code. Those of ordinary skill in the art would have been motivated to do so to represent a digital circuit.
Claim(s) 6, 12 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0169294 to Brock et al. (Brock) in view of US 2018/0173529 to Tamir et al. (Tamir) in view of US 2018/0081677 to Gibbons et al. (Gibbons).
Claims 6, 12 and 25: Brock and Tamir teach claims 1, 9 and 22, but do not teach wherein the compiler is further configured to refrain from generating errors for constructs in the inline software code that are syntactically illegal according to syntax rules of the high-level programming language.
Gibbons teaches:
a compiler configured to refrain from generating errors for instructions in software code that are syntactically illegal according to syntax rules of the high-level programming language (par. [0004]-[0008] “Annotations can be used … to suppress warnings”).
It would have been obvious before the effective filing date of the claimed invention to refrain from generating errors. Those of ordinary skill in the art would have been motivated to do so as a known compiler functionality which would have produced only the expected results.
Claim(s) 8 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0169294 to Brock et al. (Brock) in view of US 2018/0173529 to Tamir et al. (Tamir) in view of US 2013/0117548 to Grover et al. (Grover).
Claims 8 and 14: Brock and Tamir teach claim 1 and 9, but do not explicitly teach the compiler is further configured to combine at least two instructions in the software code coded in the assembly language into one instruction word, and the processor circuit is configured to fetch the instruction word to a single register.
Grover teaches:
a compiler configured to combine at least two instructions in software code coded in assembly language into one instruction word, and the processor circuit is configured to fetch the instruction word to a single register (par. [0031] “two assembly instructions can be combined into one vectorized assembly instruction”).
It would have been obvious before the effective filing date of the claimed invention to combine multiple instructions into on instruction word. Those of ordinary skill in the art would have been motivated to do so to reduce “the number of assembly instructions included in a computer program” (Grover abstract).
Claim 15: Brock and Tamir teach the method of claim 9, but do not teach compiling the first assembly code and the second assembly code into the machine code comprises combining at least two instructions in the second assembly code into one instruction word that is fetched by the processor circuit from one register.
Grover teaches:
a compiler configured to combine at least two instructions in software code coded in assembly language into one instruction word, and the processor circuit is configured to fetch the instruction word to a single register (par. [0031] “two assembly instructions can be combined into one vectorized assembly instruction”).
It would have been obvious before the effective filing date of the claimed invention combine multiple instructions into one instruction word. Those of ordinary skill in the art would have been motivated to do so to reduce “the number of assembly instructions included in a computer program” (Grover abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 6,314,557 to Shenderovich teaches a hybrid programming environment.
US 2005/0044344 to Stevens discloses inline C code.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON D MITCHELL whose telephone number is (571)272-3728. The examiner can normally be reached Monday through Thursday 7:00am - 4:30pm and alternate Fridays 7:00am 3:30pm.
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/JASON D MITCHELL/Primary Examiner, Art Unit 2199
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