DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Information disclosure statement filed 8 December 2022 has been fully considered.
Claim Objections
Claim 16 is objected to because of the following informalities:
Claim 16 recites the limitation, “the dielectric bonding layer is disposed between a portion of the first gate region and a portion the second gate region without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region” This appears to contain a typographical error and may be corrected as, “the dielectric bonding layer is disposed between a portion of the first gate region and a portion the second gate region without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 10, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation, “wherein the dielectric bonding layer is spaced apart from the gate cut portion.” It is unclear how the dielectric bonding layer (120) is spaced apart from the gate cut portion (145) when said dielectric bonding layer contacts said gate cut portion as shown in FIG. 12B.
Claims 10 and 20 recite the limitation, “the [ ] gate contact is on and contacts the second gate region.” It is unclear how the gate contact (e.g. 162-3 shown in FIG. 12B) contacts the second gate region (141b) with the gate cut portion (145) and the dielectric liner layer (165) formed therebetween. For the purposes of applying art, the gate contact may contact the second gate region with a layer formed therebetween.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-10, 17, 19, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gardner et al. (US Patent Application Publication 2023/0178436, hereinafter Gardner ‘436).
With respect to claim 1, Gardner ‘436 teaches (FIGs. 1A-1C) a semiconductor device as claimed, comprising:
a first transistor (110) comprising a first gate region (115) ([0045]);
a second transistor (120) comprising a second gate region (125), wherein the second transistor is stacked on the first transistor in a staggered configuration (the transistors 110 and 120 are staggered in a vertical direction because they are not arranged immediately adjacent to one another) ([0045]);
a dielectric bonding layer (153) between the first transistor (110) and the second transistor (120) ([0048]);
a gate cut portion (opening for contacts 132a and 142a) along a side of the first gate region (115) and a side of the second gate region (125) ([0047]); and
a gate contact (132a and 142a) connected to at least one of the first gate region (115) and the second gate region (125) ([0047]).
With respect to claim 4, Gardner ‘436 teaches wherein the dielectric bonding layer (153) is disposed between a portion of the first gate region (115) and a portion the second gate region (125) without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region ([0048]).
With respect to claim 5, Gardner ‘436 teaches wherein the dielectric bonding layer (153) is spaced apart from the gate cut portion (opening for contacts 132a and 142a) ([0048]).
With respect to claim 6, Gardner ‘436 teaches wherein the gate contact (132 and 142a) is electrically connected to the first gate region (115) without being electrically connected to the second gate region (125) ([0047]).
With respect to claim 7, Gardner ‘436 teaches wherein the gate contact (132a and 142a) is formed through a part of the gate cut portion (opening for contacts 132a and 142a) along the side of the second gate region (125) to contact the first gate region (115) ([0047]).
With respect to claim 8, Gardner ‘436 teaches further comprising a dielectric liner layer (portion of 103) on a side of the gate contact (132a and 142a) between the second gate region (125) and the gate contact ([0048]).
With respect to claim 9, Gardner ‘436 teaches wherein the gate contact (132a and 142a) extends along a side of the dielectric bonding layer (153) to contact the first gate region (115), and wherein the dielectric liner layer (portion of 103) is further on a side of the gate contact between the dielectric bonding layer and the gate contact ([0047]).
With respect to claim 10, Gardner ‘436 teaches wherein: the gate contact (132a and 142a) is on and contacts the second gate region (125) (see interpretation of this limitation provided in the above 35 U.S.C. 112(b) rejection of the claim); and the first gate region (115) is electrically isolated from the second gate region (125) by the dielectric bonding layer (153) and the gate cut portion (opening for contacts 132a and 142a) ([0047]).
With respect to claim 17, Gardner ‘436 teaches (FIGs. 1A-1C) a semiconductor device as claimed, comprising:
a first transistor (110) comprising a first gate region (115) ([0045]);
a second transistor (120) comprising a second gate region (125), wherein the second transistor is stacked on the first transistor in a staggered configuration (the transistors 110 and 120 are staggered in a vertical direction because they are not arranged immediately adjacent to one another) ([0045]);
a dielectric bonding layer (153) between the first transistor (110) and the second transistor (120) ([0048]);
a dielectric trench (103) along a side of the first gate region (115) and a side of the second gate region (125) ([0048]); and
at least one gate contact (132a and 142a) contacting one of the first gate region (115) and the second gate region (125) ([0047]).
With respect to claim 19, Gardner ‘436 teaches wherein the at least one gate contact (132a and 142a) is formed through a part of the dielectric trench (103) along the side of the second gate region (125) to contact the first gate region (115), and a dielectric liner layer (portion of 103) is on a side of the at least one gate contact between the second gate region and the at least one gate contact ([0047]).
With respect to claim 20, Gardner ‘436 teaches wherein: the at least one gate contact (132a and 142a) is on and contacts the second gate region (125) (see interpretation of this limitation provided in the above 35 U.S.C. 112(b) rejection of the claim); and the first gate region (115) is electrically isolated from the second gate region by the dielectric bonding layer (153) and the dielectric trench (103) ([0047]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner ‘436 as applied to claims 1 and 17 above, and further in view of Xie et al. (US Patent Application Publication 2023/0178553, hereinafter Xie ‘553).
With respect to claims 2, 3, 11, and 18, Gardner ‘436 teaches the device as described in claims 1 and 17 above with the exception of the additional limitations wherein the gate cut portion contacts the side of the first gate region and the side of the second gate region; wherein the gate contact is electrically connected to the first gate region through the second gate region; wherein the gate cut portion contacts an edge of the dielectric bonding layer; and wherein the at least one gate contact is on and contacts the second gate region and is electrically connected to the first gate region through the second gate region.
However, Xie ‘553 teaches (FIG. 61B) a gate cut portion (248) contacting a side of a first gate region (267) and a side of a second gate region (251); wherein a gate contact (262) is electrically connected to the first gate region through the second gate region; wherein the gate cut portion contacts an edge of a dielectric bonding layer (230); and wherein the at least one gate contact is on and contacts the second gate region and is electrically connected to the first gate region through the second gate region ([0150, 0164, 0169, 0171, 0177]) in an arrangement that seals an opening and thus ensures that no shared work functional metal is used ([0080, 0127]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Gardner ‘436 wherein the gate cut portion contacts the side of the first gate region and the side of the second gate region; wherein the gate contact is electrically connected to the first gate region through the second gate region; wherein the gate cut portion contacts an edge of the dielectric bonding layer; and wherein the at least one gate contact is on and contacts the second gate region and is electrically connected to the first gate region through the second gate region as taught by Xie ‘553 in an arrangement that seals an opening and thus ensures that no shared work functional metal is used.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Gardner ‘436 in view of Sengupta et al. (US Patent 10,811,415, hereinafter Sengupta ‘415) of record.
With respect to claim 12, Gardner ‘436 teaches (FIGs. 1A-1C) a semiconductor device substantially as claimed, comprising:
a second pair of transistors (110 and 120), wherein the second pair of transistors comprises a fourth transistor (120) stacked on a third transistor (110) in a staggered configuration (the transistors 110 and 120 are staggered in a vertical direction because they are not arranged immediately adjacent to one another), and wherein the third transistor comprises a third gate region (115) and the fourth transistor comprises a fourth gate region (125) ([0045]);
a second gate contact (132a and 142a) electrically connected to the third gate region (115) ([0047]); and
a third gate contact (132b and 142b) electrically connected to the fourth gate region (125) ([0047]).
Thus, Gardner ‘436 is shown to teach all the features of the claim with the exception of:
a first pair of transistors, wherein the first pair of transistors comprises a second transistor stacked on a first transistor in a staggered configuration, and wherein the first transistor comprises a first gate region and the second transistor comprises a second gate region; and
a first gate contact electrically connected to the first gate region and the second gate region.
However, forming a semiconductor device further comprising a first pair of transistors, wherein the first pair of transistors comprises a second transistor stacked on a first transistor in a staggered configuration, and wherein the first transistor comprises a first gate region and the second transistor comprises a second gate region represents a mere duplication of parts of the forming a second pair of transistors, wherein the second pair of transistors comprises a fourth transistor stacked on a third transistor in a staggered configuration, and wherein the third transistor comprises a third gate region and the fourth transistor comprises a fourth gate region of Gardner ‘436. A duplication of parts is generally recognized as being with the level of ordinary skill in the art. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04 VI. B.
Further, Sengupta ‘415 teaches (FIG. 2A) a first gate contact (208) electrically connected to a first gate region (214) and a second gate region (216) (col. 7, ln. 19-62) to provide voltage supply to both of said gate regions (col. 10, ln. 3-5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Gardner ‘436 further comprising a first pair of transistors, wherein the first pair of transistors comprises a second transistor stacked on a first transistor in a staggered configuration, and wherein the first transistor comprises a first gate region and the second transistor comprises a second gate region because this represents a mere duplication of parts; and to have formed the semiconductor device of Gardner ‘436 further comprising a first gate contact electrically connected to the first gate region and the second gate region as taught by Sengupta ‘415 to provide voltage supply to both of said gate regions.
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner ‘436 and Sengupta ‘415 as applied to claim 12 above, and further in view of Xie ‘553.
With respect to claims 13 and 16, Gardner ‘436 and Sengupta ‘415 teach the device as described in claim 12 above with the exception of the additional limitations further comprising: a dielectric bonding layer between the first gate region and the second gate region and between the third gate region and the fourth gate region; and a gate cut portion between the first pair and the second pair of transistors, wherein the gate cut portion is formed through the dielectric bonding layer; and wherein: the first gate contact is on the second gate region and is electrically connected to the first gate region through the second gate region; and the dielectric bonding layer is disposed between a portion of the first gate region and a portion the second gate region without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region
However, Xie ‘553 teaches (FIG. 61B) a dielectric bonding layer (230) between a first gate region (268) and a second gate region (252) and between a third gate region (267) and a fourth gate region (251); and a gate cut portion (248) between a first pair (defined by gate regions 252 and 268) and a second pair of transistors (defined by gate regions 251 and 267), wherein the gate cut portion is formed through the dielectric bonding layer; and wherein: a first gate contact (262) is on the second gate region and is electrically connected to the first gate region through the second gate region; and the dielectric bonding layer is disposed between a portion of the first gate region and a portion the second gate region without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region ([0150, 0164, 0169, 0171, 0177]) in an arrangement that seals an opening and thus ensures that no shared work functional metal is used ([0080, 0127]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Gardner ‘436 further comprising: a dielectric bonding layer between the first gate region and the second gate region and between the third gate region and the fourth gate region; and a gate cut portion between the first pair and the second pair of transistors, wherein the gate cut portion is formed through the dielectric bonding layer; and wherein: the first gate contact is on the second gate region and is electrically connected to the first gate region through the second gate region; and the dielectric bonding layer is disposed between a portion of the first gate region and a portion the second gate region without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region as taught by Xie ‘553 in an arrangement that seals an opening and thus ensures that no shared work functional metal is used.
Allowable Subject Matter
Claims 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the semiconductor device of claim 14 in the combination of limitations as claimed, noting particularly the limitation, “wherein the second gate contact is formed through a part of the gate cut portion along a side of the fourth gate region to contact the third gate region.”
Gardner ‘436 represents the closest prior art of record. See the 35 U.S.C. 103 rejection of claim 13 above. However, Gardner ‘436 is silent to a gate cut portion between the first pair and the second pair of transistors. Xie ‘553 is cited to cure this deficiency. However, Xie ‘553 fails to teach or suggest wherein the second gate contact (262) is formed through a part of the gate cut portion (248) along a side of the fourth gate region (251) to contact the third gate region (267).
Claim 15 is indicated as containing allowable subject matter based merely upon its dependency from claim 14 indicated as containing allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Chanemougame et al. (US Patent Application Publication 2021/0202500); Anderson et al. (US Patent Application Publication 2023/0402519); Xie et al. (US Patent Application Publication 2023/0411358); and Shadman et al. (US Patent Application Publication 2025/0221030) teach gate cut portions to contact gate regions of stacked transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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