DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 29 June 2026 is acknowledged. Claims 5, 10, 13, 14, and 20 have been canceled. Claims 1, 11, 12, and 15-17 have been amended. Claims 1-4, 6-9, 11, 12, and 15-19 are pending.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 135A. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amendments to paragraph [0075] of the specification were received on 29 June 2026. These amendments to the specification are acceptable.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4 recites the limitation, “wherein the dielectric bonding layer is disposed between a portion of the first gate region and a portion the second gate region.” This appears to contain a typographical error and may be corrected as, “wherein the dielectric bonding layer is disposed between a portion of the first gate region and a portion of the second gate region.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US Patent Application Publication 2019/0393214, hereinafter Lilak ‘214) in view of Gardner et al. (US Patent Application Publication 2023/0178436, hereinafter Gardner ‘436) of record.
With respect to claim 1, Lilak ‘214 teaches (FIG. 4) a semiconductor device substantially as claimed, comprising:
a first transistor (transistor defined by channels 461) comprising a first gate region (463) ([0064]);
a second transistor (transistor defined by channels 481) comprising a second gate region (483), wherein the second transistor is stacked on the first transistor (transistor defined by channels 461) in a staggered configuration, wherein the staggered configuration includes the first transistor being disposed in an offset position relative to the second transistor, the offset position being defined in a first direction, the first direction being different than a second direction in which the first transistor and the second transistor are stacked ([0064]);
a dielectric bonding layer (475) between the first transistor (transistor defined by channels 461) and the second transistor (transistor defined by channels 481) ([0062]); and
a gate cut portion (opening for elements 451, 452, and 457) along a side of the first gate region (463) and a side of the second gate region (483) ([0061-0062]).
Thus, Lilak ‘214 is shown to teach all the features of the claim with the exception of a gate contact connected to at least one of the first gate region and the second gate region.
However, Gardner ‘436 teaches a gate contact (132a and 142a) connected to at least one of a first gate region (115) and a second gate region (125) to supply voltage to said first gate region and said second gate region ([0047]). Further, Lilak ‘214 teaches, “The conductor (457) may be used to route signals between the lower device layer (420) and the upper device layer (440).” One or ordinary skill in the art could apply the teachings of Gardner ‘436 to route signals to the first gate region (463) and the second gate region (483) of Lilak ‘214 with a reasonable expectation of success.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Lilak ‘214 further comprising a gate contact connected to at least one of the first gate region and the second gate region as taught by Gardner ‘436 to supply voltage to said first gate region and said second gate region.
With respect to claim 2, Lilak ‘214 teaches wherein the gate cut portion (opening for elements 451, 452, and 457) contacts the side of the first gate region (463) and the side of the second gate region (483) ([0061-0062]).
With respect to claims 3 and 18, Lilak ‘214 and Gardner ‘436 teach the device as described in claims 1 and 17 above, but primary reference Lilak ‘214 does not explicitly teach the additional limitations wherein the gate contact is electrically connected to the first gate region through the second gate region; and wherein the at least one gate contact is on and contacts the second gate region and is electrically connected to the first gate region through the second gate region.
However, Gardner ‘436 teaches a gate contact (132a and 142a) connected to at least one of a first gate region (115) and a second gate region (125) to supply voltage to said first gate region and said second gate region ([0047]). Further, Lilak ‘214 teaches a gate contact (451, 452, and 457) passing through the first gate region (463) and the second gate region (483). Still further, Lilak ‘214 teaches, “The conductor (457) may be used to route signals between the lower device layer (420) and the upper device layer (440).” One or ordinary skill in the art could apply the teachings of Gardner ‘436 to route signals to the first gate region (463) and the second gate region (483) of Lilak ‘214 using the gate contact (451, 452, and 457) on and contacting the second gate region and electrically connected to the first gate region through the second gate region with a reasonable expectation of success. Such an arrangement of passing the gate contact through the gate regions rather than outside said gate regions would reduce device footprint.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Lilak ‘214 and Gardner ‘436 wherein the gate contact is electrically connected to the first gate region through the second gate region; and wherein the at least one gate contact is on and contacts the second gate region and is electrically connected to the first gate region through the second gate region as taught by Lilak ‘214 and Gardner ‘436 in combination to supply voltage to said first gate region and said second gate region while minimizing device footprint.
With respect to claim 4, Lilak ‘214 and Gardner ‘436 teach the device as described in claim 1 above, but primary reference Lilak ‘214 does not explicitly teach the additional limitation wherein the dielectric bonding layer is disposed between a portion of the first gate region and a portion the second gate region without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region.
However, Gardner ‘436 teaches wherein the dielectric bonding layer (153) is disposed between a portion of the first gate region (115) and a portion the second gate region (125) without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region to use only the minimal amount of dielectric bonding layer necessary to insulate and bond said first gate region and said second gate region ([0048]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the dielectric bonding layer of Lilak ‘214 and Gardner ‘436 disposed between a portion of the first gate region and a portion the second gate region without being disposed between a remaining portion of the first gate region and a remaining portion the second gate region as taught by Gardner ‘436 to use only the minimal amount of dielectric bonding layer necessary to insulate and bond said first gate region and said second gate region.
With respect to claims 6-9, Lilak ‘214 and Gardner ‘436 teach the device as described in claim 1 above, but primary reference Lilak ‘214 does not explicitly teach the additional limitations wherein the gate contact is electrically connected to the first gate region without being electrically connected to the second gate region; wherein the gate contact is formed through a part of the gate cut portion along the side of the second gate region to contact the first gate region; further comprising a dielectric liner layer on a side of the gate contact between the second gate region and the gate contact; and wherein the gate contact extends along a side of the dielectric bonding layer to contact the first gate region, and wherein the dielectric liner layer is further on a side of the gate contact between the dielectric bonding layer and the gate contact.
However, Gardner ‘436 teaches wherein the gate contact (132 and 142a) is electrically connected to the first gate region (115) without being electrically connected to the second gate region (125) ([0047]); wherein the gate contact (132a and 142a) is formed through a part of the gate cut portion (opening for contacts 132a and 142a) along the side of the second gate region (125) to contact the first gate region (115) ([0047]); further comprising a dielectric liner layer (portion of 103) on a side of the gate contact (132a and 142a) between the second gate region (125) and the gate contact ([0048]); and wherein the gate contact (132a and 142a) extends along a side of the dielectric bonding layer (153) to contact the first gate region (115), and wherein the dielectric liner layer (portion of 103) is further on a side of the gate contact between the dielectric bonding layer and the gate contact ([0047]) in an arrangement that improves device scaling by providing specific, individual connections to the gate regions in a 3D array ([0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Lilak ‘214 and Gardner ‘436 wherein the gate contact is electrically connected to the first gate region without being electrically connected to the second gate region; wherein the gate contact is formed through a part of the gate cut portion along the side of the second gate region to contact the first gate region; further comprising a dielectric liner layer on a side of the gate contact between the second gate region and the gate contact; and wherein the gate contact extends along a side of the dielectric bonding layer to contact the first gate region, and wherein the dielectric liner layer is further on a side of the gate contact between the dielectric bonding layer and the gate contact as taught by Gardner ‘436 to improve device scaling by providing specific, individual connections to the gate regions in a 3D array.
With respect to claim 17, Lilak ‘214 teaches (FIG. 4) a semiconductor device substantially as claimed, comprising:
a first transistor (transistor defined by channels 461) comprising a first gate region (463) ([0064]);
a second transistor (transistor defined by channels 481) comprising a second gate region (483), wherein the second transistor is stacked on the first transistor (transistor defined by channels 461) in a staggered configuration, wherein the staggered configuration includes the first transistor being disposed in an offset position relative to the second transistor, the offset position being defined in a first direction, the first direction being different than a second direction in which the first transistor and the second transistor are stacked ([0064]);
a dielectric bonding layer (475) between the first transistor (transistor defined by channels 461) and the second transistor (transistor defined by channels 481) ([0062]); and
a dielectric trench (451 and 452) along a side of the first gate region (463) and a side of the second gate region (483) ([0061-0062]).
Thus, Lilak ‘214 is shown to teach all the features of the claim with the exception of at least one gate contact contacting one of the first gate region and the second gate region.
However, Gardner ‘436 teaches at least one gate contact (132a and 142a) contacting one of a first gate region (115) and a second gate region (125) to supply voltage to said first gate region and said second gate region ([0047]). Further, Lilak ‘214 teaches, “The conductor (457) may be used to route signals between the lower device layer (420) and the upper device layer (440).” One or ordinary skill in the art could apply the teachings of Gardner ‘436 to route signals to the first gate region (463) and the second gate region (483) of Lilak ‘214 with a reasonable expectation of success.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Lilak ‘214 further comprising at least one gate contact contacting one of the first gate region and the second gate region as taught by Gardner ‘436 to supply voltage to said first gate region and said second gate region.
With respect to claim 19, Lilak ‘214 and Gardner ‘436 teach the device as described in claim 1 above, but primary reference Lilak ‘214 does not explicitly teach the additional limitation wherein the at least one gate contact is formed through a part of the dielectric trench along the side of the second gate region contact the first gate region, and a dielectric liner layer is on a side of the at least one gate contact between the second gate region and the at least one gate contact.
However, Gardner ‘436 teaches wherein the at least one gate contact (132a and 142a) is formed through a part of the dielectric trench (103) along the side of the second gate region (125) to contact the first gate region (115), and a dielectric liner layer (portion of 103) is on a side of the at least one gate contact between the second gate region and the at least one gate contact ([0047]) in an arrangement that improves device scaling by providing specific, individual connections to the gate regions in a 3D array ([0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the at least one gate contact of Lilak ‘214 and Gardner ‘436 through a part of the dielectric trench along the side of the second gate region contact the first gate region, and a dielectric liner layer is on a side of the at least one gate contact between the second gate region and the at least one gate contact as taught by Gardner ‘436 to improve device scaling by providing specific, individual connections to the gate regions in a 3D array.
Response to Arguments
Applicant’s amendments to claim 16 are sufficient to overcome the objection to claim 16 made in the non-final rejection filed 27 March 2026. The objection to claim 16 has been withdrawn.
Applicant’s cancelation of claims 5, 10, and 20 are sufficient to overcome the 35 U.S.C. 112(b) rejections of claims 5, 10, and 20 made in the non-final rejection filed 27 March 2026. The 35 U.S.C. 112(b) rejections of claims 5, 10, and 20 have been withdrawn.
Applicant’s statement of common ownership (see remarks, pp. 7-8) excepting the Xie et al. (US Patent Application Publication 2023/0178553) reference as prior art under 35 U.S.C. 102(b)(2)(C) is sufficient to overcome the prior 35 U.S.C. 103 rejections of claims 2, 3, 11, 13, 16, and 18 made in the non-final rejection filed 27 March 2026. The prior 35 U.S.C. 103 rejections of claims 2, 3, 11, 13, 16, and 18 have been withdrawn.
Applicant’s amendments to independent claim 12 incorporating the allowable subject matter of now-canceled dependent claim 14 and intervening claim 13 are sufficient to overcome the 35 U.S.C. 103 rejections of claims 12, 13, and 16 made in the non-final rejection filed 27 March 2026. The 35 U.S.C. 103 rejections of claims 12, 13, and 16 have been withdrawn.
Applicant’s arguments with respect to amended claim(s) 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 11, 12, 15, and 16 are allowed. Independent claim 12 has been amended to incorporate the allowable subject matter of now-canceled dependent claim 14 and intervening claim 13, and is allowed for the same reasons as set forth on pp. 12-13 of the non-final rejection filed 27 March 2026. Claims 11, 15, and 16 are allowed based merely upon their dependencies from allowed claim 12.
Statement Concerning Related Prior Art
Examiner identifies the following prior art references that may teach the claimed invention either individually or in combination: Anderson et al. (US Patent Application Publication 2023/0402519) of record, Xie et al. (US Patent Application Publication 2023/0411386), Xie et al. (US Patent Application Publication 2023/0411358) of record, and Chu et al. (US Patent Application Publication 2024/0064951) as sharing a common Applicant and having a publication date after the effective filing date of the claimed invention. In order to expedite prosecution, if these references can be excepted under 35 U.S.C. 102(b)(2)(C), Applicant is respectfully requested to do so in the subsequent response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Chu et al. (US Patent Application Publication 2023/0178619), Song et al. (US Patent Application Publication 2024/0355879), Xie et al. (US Patent Application Publication 2025/0212483), and Reboh et al. (US Patent Application Publication 2025/0212508) teach staggered gate-all-around transistors.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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