DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed, as the title does not indicate the data processing system is in the technical field of in-memory computing. The Examiner suggests inserting “in-memory computing” or alternative to the title.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-5, 12, 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4, 12, 17 recites the limitation "the first number of sub-arrays". There is insufficient antecedent basis for this limitation in the claim as only “a first number of rows” has been declared prior. For examination purposes, the Examiner interprets “the first number of sub-arrays" as “a first number of sub-arrays”.
Claims 5, 18 recites the limitation "the column line". There is insufficient antecedent basis for this limitation in the claim as only “a plurality of column lines” has been declared prior. Furthermore, it is unclear whether “the column line” refers to a single column line or a plurality of column lines. For examination purposes, the Examiner interprets “the column line” to be “the plurality of column lines”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8-12, 14-17, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hoang et al. (US 20210110235 A1, hereinafter “Hoang”) in view of Hush et al. (US 20190189189 A1, hereinafter “Hush”).
As per claim 1, Hoang teaches A data processing system comprising: wherein each of the sub-arrays from the plurality of sub-arrays each include a plurality of memory cells connected between a plurality of row lines and a plurality of column lines (Hoang: Fig. 15 element 1501; [0070]);
and a controller configured to control the processing memory, to detect a valid component from a first operand received from an exterior and having a digital level, to apply a voltage corresponding to the valid component having a digital level to a row line of at least one sub-array (Hoang: Fig. 15 element 1520; [0070]),
and to store a second operand received from an exterior in the at least one sub-array (Hoang: [0068], “The memory cells have been written with a set of weights of a CNN to form a filter for use in a convolution.”).
However, while Hoang discloses the circuitry of a sub-array ([0007]), Hoang does not explicitly disclose the system uses a plurality of sub-arrays. Thus, Hoang does not teach a processing memory including a plurality of sub-arrays,
Hush teaches a processing memory including a plurality of sub-arrays (Hush: Fig. 3),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the system of Hoang with the plurality of sub-arrays teaching of Hush. One would have been motivated to combine these references because both references disclose neural network accelerators using sub-arrays, and combining prior art elements according to known methods to yield predictable results (that the subarray of Hoang is one of a plurality of sub-arrays).
As per claim 2, Hoang/Hush further teaches The data processing system according to claim 1, wherein the processing memory is configured to perform an element-wise summation operation on the first operand and the second operand (Hoang: Fig. 15 elements 1509; [0069]).
As per claim 3, Hoang/Hush further teaches The data processing system according to claim 1, further comprising: an analog-to-digital converter connected (Hoang: Fig. 15 elements 1507; [0069]) to each of the plurality of sub-arrays (Hush: Fig. 3);
and an accumulator configured to sum output signals of the analog- to-digital converter (Hoang: Fig. 15 elements 1509; [0069]).
As per claim 4 Hoang/Hush further teaches The data processing system according to claim 1, wherein the first operand and the second operand are each configured as a matrix (Hoang: [0052]), and the controller is configured to group the first operand and the second operand in units of a first number of rows and to provide the grouped first operand and second operand to the first number of sub-arrays, respectively (Hush: Fig. 1B element 119; [0033], wherein each subarray receives a respective group of rows).
As per claim 6, Hoang/Hush further teaches The data processing system according to claim 1, wherein each of the plurality of memory cells includes a memristor element (Hoang: Fig. 9 elements 903).
As per claims 8-9, the claims are directed to an operating method that implements the same or similar features as the data processing system of claims 1-2, and are therefore rejected for at least the same reasons therein.
As per claim 10, Hoang/Hush further teaches The operating method according to claim 9, further comprising: converting summation operation results of the at least one sub-array into digital values (Hoang: Fig. 15 elements 1507; [0069]).
As per claim 11, Hoang/Hush further teaches The operating method according to claim 10, further comprising: summing the digital values (Hoang: Fig. 15 elements 1509; [0069]).
As per claim 12, the claim is directed to an operating method that implements the same or similar features as the data processing system of claim 4, and is therefore rejected for at least the same reasons therein.
As per claims 14-17, the claims are directed to a computing system that implements the same or similar features as the data processing system of claims 1-4, and are therefore rejected for at least the same reasons therein.
As per claim 19, the claim is directed to a computing system that implements the same or similar features as the data processing system of claim 6, and is therefore rejected for at least the same reasons therein.
Claims 5, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hoang/Hush in further view of Sumbul et al. (US 20190042199 A1, hereinafter “Sumbul”).
As per claim 5, Hoang/Hush further teaches The data processing system according to claim 4, further comprising: an accumulator configured to sum output signals (Hoang: Fig. 15 elements 1509; [0069]).
However, Hoang/Hush does not teach a shared analog-to-digital converter connected in common to the column line of each of the plurality of sub-arrays;
Sumbul teaches a shared analog-to-digital converter connected in common to the column line of each of the plurality of sub-arrays (Sumbul: Fig. 5 element 503; [0044]);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the system of Hoang with the shared analog processor of Sumbul, such that accumulation occurs after the shared analog processor. One would have been motivated to combine these references because both references disclose neural network accelerators using analog arrays, and feeding two CIM analog outputs to an analog processor increase throughput and decreases energy (Sumbul: [0050]).
As per claim 18, the claim is directed to a computing system that implements the same or similar features as the data processing system of claim 5, and is therefore rejected for at least the same reasons therein.
Claims 7, 13, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hoang/Hush in further view of Das et al. (US 20220375538 A1, hereinafter “Das”).
As per claim 7, Hoang/Hush further teaches The data processing system according to claim 1, wherein the second operand includes a weight matrix (Hoang: [0068]).
However, while Hoang discloses multiplying activation matrix with weight matrix ([0052]), Hoang does not explicitly disclose the input matrix as an embedding matrix. Thus, Hoang does not teach the first operand includes an embedding matrix
Das teaches the first operand includes an embedding matrix (Das: [0069]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the activation matrix input of Hoang with the embedding matrix input of Das. One would have been motivated to combine these references because both references disclose neural network processors performing matrix multiplication, and combining prior art elements according to known methods to yield predictable results (changing what the input data represents).
As per claim 13, the claim is directed to an operating method that implements the same or similar features as the data processing system of claim 7, and is therefore rejected for at least the same reasons therein.
As per claim 20, the claim is directed to a computing system that implements the same or similar features as the data processing system of claim 7, and is therefore rejected for at least the same reasons therein.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Li (US 20230049323 A1) discloses a compute-in-memory array that detect inputs that correspond with zero-valued inputs and disables the row associated with the zero-values inputs (Fig. 2; [0055]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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