DETAILED ACTION
This action is in response to the filing of 12-9-2022. Claims 1-20 are pending and have been considered below:
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 19-20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Claims 19-20 recites a "machine-readable medium". The broadest reasonable interpretation of a claim drawn to a medium typically covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of readable mediums. With this understanding claims 19-20 are rejected as covering non-statutory subject matter.
Specification discloses non-transitory medium in an exemplary manner, and therefore is not considered an explicit reading.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over An LLVM-based C++ Compiler Toolchain for Variational Hybrid Quantum-Classical Algorithms and Quantum Accelerators Pradnya Khalate et al. (“Khalate”) pages 1-19, 12-22-2022 in view of Quantum Computer Architecture Toward Full-Stack Quantum Accelerators KOEN BERTELS et al. (“Bertels”), pages 1-17 6-3-2020.
Claim 1: Khalate discloses an apparatus comprising: a host processor (Introduction: CPU, classical computer) to perform a partial compilation on hybrid quantum-classical source code (Page 1, Introduction; source code and Figure 8; hybrid compute) to generate one or more sequential blocks of quantum operations (Page 3, Section 3; runtime produces QBB which is sequence operations);
a quantum compiler accelerator to receive compilation work, offloaded by the host processor including an indication of the one or more sequential blocks of quantum operations (Figure 1 and Introduction; passes (offload) values for the quantum operation);
the quantum compiler to perform optimization operations to optimize runtime execution of one or more of the quantum operations in view if a quantum accelerator architecture to generate optimized quantum operations (Figures 1 and 3; Page 1, Introduction and Page 3, Section II, A, Point 2; analysis and optimization performed);
to manipulate a state of one or more qubits, to measure a state of the one or more qubits, and to provide measurement data indicating the state to the host processor (Figures 3 and 4 (read measurements) Page 4 (read measurements) and Page 11, Section C; evaluation of state).
Khalate discloses a quantum execution accelerator (Figure 4) and features interpreted as having the quantum accelerator architecture to execute the optimized quantum operations (Figure 4; quantum device, execute QBB);
However to more explicitly disclose offloading from a host and a quantum execution accelerator having the quantum accelerator architecture to execute the optimized quantum operations, Bertels is disclosed. Bertels provides a quantum accelerator architecture for optimized operations (Figures 2, 8 and Page 12, Section C) and provides additional functionality where the host processor offloads task (Figure 8(a), Page 1, Introduction, Column 1 and Page 12, Section C, Paragraph 4).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use a known technique to improve a similar device and disclose the accelerator architecture and offloading capabilities for utilization in the quantum system of Khalate. One would have been motivated to provide the functionality because the architecture more clearly details the procedures and capability of the system.
Claim 2: Khalate and Bertels disclose an apparatus of claim 1 wherein the host processor, quantum compiler accelerator, and quantum execution accelerator are integrated on a single integrated circuit chip or a single processor package (Khalate: Page 3, Figure 2; single stack disclosed and Bertels: Figure 8).
Claim 3: Khalate and Bertels disclose an apparatus of claim 1 wherein the optimized quantum operations are stored as instructions executable by the quantum execution accelerator (Khalate: Page 5: Section C, Section II:2).
Claim 4: Khalate and Bertels disclose an apparatus of claim 3 wherein the instructions are stored in a linkable, quantum binary(Khalate: Page 4, Figure 3; ELFQ).
Claim 5: Khalate and Bertels disclose an apparatus of claim 4 wherein the partial compilation on hybrid quantum-classical source code is to further generate a classical binary including instructions to be executed by the host processor(Khalate: Page 9, Figure 8; QRT and Bertels: Figure 8).
Claim 6: Khalate and Bertels disclose an apparatus of claim 5 wherein the quantum binary and the classical binary are linked into a single executable for performing an optimized quantum algorithm (Khalate: Figures 3/8 and Bertels: Page 7, Column 1; binary file for execution).
Claim 7: Khalate and Bertels disclose an apparatus of claim 6 wherein to execute the optimized quantum algorithm, the host processor is to execute the instructions of the classical binary and to offload execution of the instructions in the quantum binary to the quantum execution accelerator(Khalate: Figure 8 and Bertels: Page7, Column 1; binary file for execution, Page 12, Section C, Paragraph 4; offloading to quantum).
Claim 9: Khalate and Bertels disclose an apparatus of claim 1 wherein the optimization operations comprise one or more of: generating additional operations and mapping the additional operations to qubits in accordance with the quantum accelerator architecture (Khalate: Page 7, Bullet: qubit mapping); scheduling the operations based on the quantum accelerator architecture;
and decomposing of all operations to into native instructions based on the quantum accelerator architecture (Khalate: Page 6, Section B decomposition of quantum logic and Page 7, Bullet: Gate decomposition).
Claims 10 and 19 are similar in scope to claim 1 and therefore rejected under the same rationale.
Khalate: Figure 8 and Page 7 Section C (machine code) provides compute which will have machine readable medium.
Claims 11 and 20 are similar in scope to claim 2 and therefore rejected under the same rationale.
Claim 12 is similar in scope to claim 3 and therefore rejected under the same rationale.
Claim 13 is similar in scope to claim 4 and therefore rejected under the same rationale.
Claim 14 is similar in scope to claim 5 and therefore rejected under the same rationale.
Claim 15 is similar in scope to claim 6 and therefore rejected under the same rationale.
Claim 16 is similar in scope to claim 7 and therefore rejected under the same rationale.
Claim 18 is similar in scope to claim 9 and therefore rejected under the same rationale.
Claim 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over An LLVM-based C++ Compiler Toolchain for Variational Hybrid Quantum-Classical Algorithms and Quantum Accelerators Pradnya Khalate et al. (“Khalate”) pages 1-19, 12-22-2022 and Quantum Computer Architecture Toward Full-Stack Quantum Accelerators KOEN BERTELS et al. (“Bertels”), pages 1-17, 6-3-2020 in further view of Chakraborty et al. (“Chakraborty” 11777496 B1).
Claim 8: Khalate and Bertels disclose an apparatus of claim 7 however may not explicitly disclose wherein the quantum execution accelerator comprises: a quantum control processor to execute the instructions of the quantum binary to generate control signals; a pulse generator to generate radio frequency (RF) pulses in response to the control signals; and a qubit device comprising one or more qubits to be manipulated by the RF pulses.
Chakraborty is disclosed to provide a functionality consisting of radio frequency signal generator to provide RF signals utilized to control (manipulate) the qubits (Column 34, Lines 2-10). Therefore it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use a known technique to improve a similar device and provide RF signal generation in the quantum system of Khalate. One would have been motivated to provide the functionality because radio frequency provides precise, high-speed messengers that perform efficient manipulation, utilizing reliable, low-noise communication.
Claim 17 is similar in scope to claim 8 and therefore rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
2022015044 A1 ABSTRACT, QUANTUN STATE
Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
In the interests of compact prosecution, Applicant is invited to contact the examiner via electronic media pursuant to USPTO policy outlined MPEP § 502.03. All electronic communication must be authorized in writing. Applicant may wish to file an Internet Communications Authorization Form PTO/SB/439. Applicant may wish to request an interview using the Interview Practice website: http://www.uspto.gov/patent/laws-and-regulations/interview-practice.
Applicant is reminded Internet e-mail may not be used for communication for matters under 35 U.S.C. § 132 or which otherwise require a signature. A reply to an Office action may NOT be communicated by Applicant to the USPTO via Internet e-mail. If such a reply is submitted by Applicant via Internet e-mail, a paper copy will be placed in the appropriate patent application file with an indication that the reply is NOT ENTERED. See MPEP § 502.03(II).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHERROD KEATON whose telephone number is 571-270-1697. The examiner can normally be reached 9:30am to 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor MICHELLE BECHTOLD can be reached at 571-431-0762. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHERROD L KEATON/Primary Examiner, Art Unit 2148
3-10-2026
Prosecution Insights