DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 10-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because claim 10 recites “one machine readable medium”, which may be interpreted as a propagation medium in view of paragraph 65 of the specification. The examiner suggests the applicant to specify in the claim language that the ”machine readable medium” is non-transitory.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-21 are rejected under 35 U.S.C. 103 as being unpatentable over Cook et al. (US 2003/0056076), “Cook” in view of Radjai et al. (US 2019/0332469), “Radjai”.
2. As per claim 1, Cook discloses a memory to be partitioned to a first region [a first application allocated with a memory partition, abstract] and a second region [a second process deallocating its memory region, paragraph 43]; and a memory controller to include circuitry, the circuitry to: receive an allocation request from an operating system [memory managing OSes, paragraph 4] to allocate memory for data used or generated by a process associated with an application [a first application allocated with a memory partition, abstract]; and allocate a portion of memory capacity included in the first region of the memory to the process based on the allocation request [a first application allocated with a memory partition when sufficient memory capacity is available, abstract, figure 2].
Cook does not disclose expressly that the first region is in-band error correction control (IBECC) memory.
Radjai discloses a memory with in-band ECC module in figure 1.
Cook and Radjai are analogous art because they are from the same field of endeavor of storage device control.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Cook by including the in-band ECC module as taught by Radjai in figure 1.
The motivation for doing so would have been data protection as expressly taught by Radjai in the abstract.
3. As per claim 2, the cited prior arts disclose the circuitry to: receive re-sizing information from the operating system, the re-sizing information to indicate a re-sizing of the memory capacity included in the first region of the memory [re-allocating memory partitions, figure 2, Cook]; and re-size, based on the re-sizing information, the memory capacity to include reducing memory capacity included in the second region of the memory [de-allocating lower priority partitions, figure 2, Cook] and adding the memory capacity reduced from the second region of memory to the first region of the memory [re-allocating memory partitions, figure 2, Cook].
4. As per claim 3, the cited prior arts disclose wherein re-sizing information includes a size of memory capacity [sufficient memory size, figure 2, Cook] to remove from the second region of the memory and a memory address range [lower priority addresses, figure 2, Cook] of the memory associated with the size of memory capacity to remove from the second region of the memory.
5. As per claim 4, the cited prior arts disclose wherein to re-size the memory capacity of the first region of the memory is based on allocated memory capacity reaching a threshold [sufficient memory size, figure 2, Cook].
6. As per claim 5, the cited prior arts disclose a plurality of processing cores [memory requestors, figure 1, Radjai]; and one or more punit registers [a register, paragraph 62, Radjai] configured to receive the re-sizing information from the operating system.
7. As per claim 6, the cited prior arts disclose the circuitry to: receive re-sizing information from the operating system to indicate a re-sizing of the memory capacity included in the first region of the memory; and re-size, based on the re-sizing information, the memory capacity to include reducing memory capacity included in the first region of the memory and adding the memory capacity reduced from the first region of memory to the second region of the memory [re-allocating a partition from a higher priority partition, paragraph 49, Cook].
8. As per claim 7, the cited prior arts disclose wherein re-sizing information includes a size of memory capacity [sufficient memory size, figure 2, Cook] to remove from the first region of the memory and a memory address range [higher priority addresses, paragraph 49, Cook] of the memory associated with the size of memory capacity to remove from the first region of the memory.
9. As per claim 8, the cited prior arts disclose wherein to re-size the memory capacity of the first region of the memory is based on allocated memory capacity to the second region of memory reaching a threshold [sufficient memory size, figure 2, Cook].
10. As per claim 9, the cited prior arts disclose a plurality of processing cores [memory requestors, figure 1, Radjai]; and one or more punit registers [a register, paragraph 62, Radjai] configured to receive the re-sizing information from the operating system.
11. As per claim 10, Cook discloses receive Information from an application to indicate that data used or generated by a process associated with the application is to be stored in memory [an application allocated with a memory partition, abstract, figure 2]; generate, based on the information from the application, process control information for the process [memory request 200, figure 2], the process control information to include an indication that the data used or generated by the process is to be stored in a first region of a memory [a first application allocated with a memory partition, abstract]; and cause a portion of memory capacity included in the first region of the memory to be allocated to the process [a first application allocated with a memory partition when sufficient memory capacity is available, abstract, figure 2].
Cook does not disclose expressly that the memory is in-band error correction control (IBECC) memory.
Radjai discloses a memory with in-band ECC module in figure 1.
Cook and Radjai are analogous art because they are from the same field of endeavor of storage device control.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Cook by including the in-band ECC module as taught by Radjai in figure 1.
The motivation for doing so would have been data protection as expressly taught by Radjai in the abstract.
12. As per claim 11, the cited prior art disclose the instructions to further cause the operating system to: include, in the process control information, an indication of a memory address [lower priority addresses, figure 2, Cook] and a size for the portion of memory capacity to be allocated to the process [sufficient memory size, figure 2, Cook]; and send the memory address and size information to a memory controller for the memory to cause the portion of memory capacity to be allocated to the process [re-allocating memory partitions, figure 2, Cook].
13. As per claim 12, the cited prior arts discloses the instructions to further cause the operating system to: track memory capacity allocated to other processes associated with other application to have data used or generated by the other processes to be stored in IBECC memory provided by the first region of memory [IBECC memory, figure 1, Radjai]; re-size a memory capacity of the first region of the memory based on allocated memory capacity reaching a threshold [sufficient memory size, figure 2, Cook]; and send re-sizing information to a memory controller for the memory to cause the memory capacity of the first region of memory to be re-sized [a first application allocated with a memory partition when sufficient memory capacity is available, abstract, figure 2].
14. As per claim 13, the cited prior arts disclose wherein to re-size the memory capacity of the first region of memory [IBECC memory, figure 1, Radjai] is also based on free memory capacity in a second region of the memory, the second region of the memory is arranged to not provide IBECC memory or is arranged to provide non-IBECC memory [a second process previously allocated with its memory region, paragraph 43, Cook].
15. As per claim 14, the cited prior art disclose wherein the re-sizing information sent to the memory controller indicates a memory capacity of the free memory capacity and a memory address range for the free memory capacity that is to be removed from the second region of the memory [de-allocating lower priority partitions, figure 2, Cook] and added to the second region of the memory in order to re-size the first region of the memory [re-allocating memory partitions, figure 2, Cook] to include an increased memory capacity to provide IBECC memory [IBECC memory, figure 1, Radjai].
16. As per claim 15, Cook discloses circuitry to: receive an allocation request from an operating system [memory managing OSes, paragraph 4] to allocate memory for data used or generated by a process associated with an application [a first application allocated with a memory partition, abstract]; and allocate, to the process based on the allocation request [memory request 200, figure 2], a portion of memory capacity included in a first region of a memory arranged to provide the memory [a first application allocated with a memory partition when sufficient memory capacity is available, abstract, figure 2], wherein a second region of the memory is arranged to provide memory [a second process previously allocated with its memory region, paragraph 43].
Cook does not disclose expressly one or more registers; and that the first region of the memory is in-band error correction control (IBECC) memory.
Radjai discloses a register in paragraph 62 and a memory with in-band ECC module in figure 1.
Cook and Radjai are analogous art because they are from the same field of endeavor of storage device control.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Cook by including the in-band ECC module as taught by Radjai in figure 1.
The motivation for doing so would have been data protection as expressly taught by Radjai in the abstract.
17. As per claim 16, the cited prior arts disclose the one or more registers [a register, paragraph 62, Radjai] configured to receive re-sizing information from the operating system, the re-sizing information to indicate a re-sizing of the memory capacity included in the first region of the memory [re-allocating memory partitions, figure 2, Cook].; and the circuitry configured to re-size, based on the re-sizing information to be received in the one or more registers, the memory capacity to include reducing memory capacity included in the second region of the memory [de-allocating lower priority partitions, figure 2, Cook] and adding the memory capacity reduced from the second region of memory to the first region of the memory.
18. As per claim 17, the cited prior arts disclose wherein the re-sizing information to be received in the one or more registers includes a size of memory capacity [sufficient memory size, figure 2, Cook] to remove from the second region of the memory and a memory address range [lower priority addresses, figure 2, Cook] of the memory associated with the size of memory capacity to remove from the second region of the memory.
19. As per claim 18, the cited prior arts disclose wherein to re-size the memory capacity of the first region of the memory is based on allocated memory capacity reaching a threshold [sufficient memory size, figure 2, Cook].
20. As per claim 19, the cited prior arts disclose the one or more registers configured to receive re-sizing information from the operating system, the re-sizing information to indicate a re-sizing of the memory capacity included in the first region of the memory; and the circuitry configured to re-size, based on the re-sizing information to be received in the one or more registers, the memory capacity to include reducing memory capacity included in the first region of the memory and adding the memory capacity reduced from the first region of memory to the second region of the memory [re-allocating a partition from a higher priority partition, paragraph 49, Cook].
21. As per claim 20, the cited prior arts disclose wherein re-sizing information to be received in the one or more registers includes a size of memory capacity [sufficient memory size, figure 2, Cook] to remove from the first region of the memory and a memory address range [higher priority addresses, paragraph 49, Cook] of the memory associated with the size of memory capacity to remove from the first region of the memory.
22. As per claim 21, the cited prior arts disclose wherein to re-size the memory capacity of the first region of the memory is based on allocated memory capacity to the second region of memory reaching a threshold [sufficient memory size, figure 2, Cook].
Conclusion
A. Claims Rejected
Claims 1-21 are rejected.
B. Direction for Future Remarks
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAE U YU/Primary Examiner, Art Unit 2138