Prosecution Insights
Last updated: April 19, 2026
Application No. 18/079,326

METHOD AND APPARATUS FOR DETERMINING A CLOCK FREQUENCY OFFSET

Non-Final OA §103
Filed
Dec 12, 2022
Examiner
CHOUDHURY, FAISAL
Art Unit
2478
Tech Center
2400 — Computer Networks
Assignee
U-Blox AG
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
666 granted / 784 resolved
+26.9% vs TC avg
Strong +15% interview lift
Without
With
+15.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
38 currently pending
Career history
822
Total Applications
across all art units

Statute-Specific Performance

§101
4.4%
-35.6% vs TC avg
§103
51.6%
+11.6% vs TC avg
§102
19.0%
-21.0% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 784 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/4/2025 has been entered. Claim Rejections - 35 USC § 103 1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pre-Grant Publication US 2018/0302869 to Hollar et al. (hereinafter Hollar) in view of U.S. Pre-Grant Publication US 2019/0199286 to Seth et al. (hereinafter Seth) As to claim 1, Hollar discloses a method for determining a clock frequency offset between a first device having a first clock and at least two second devices, each second device having a respective second clock, the method comprising: receiving, by the at least two second devices, at least one first message from the first device, wherein information regarding a time of departure of the at least one first message is in the at least one first message (Hollar; Fig.1; Fig.2; [0044]-[0045] shows and discloses MD sends out a broadcast (RF packet). A broadcast is an RF message that does not necessarily have a single intended receiver. Multiple devices could receive the same broadcast message. The message includes the MD identifier number (Device id# MD). In some embodiments, the broadcast message includes the time at which the broadcast started transmission, TDEPARTt MD-1 (=time of departure of the at least one first message) as illustrated in FIG 1. Fig.2 of sending RF Packet 1 (=first message) and also discloses TDEPARTt MD-1); determining, by the at least two second devices, a time of arrival of the at least one first message (Hollar; Fig.1; [0044]-[0045] shows and discloses MD sends out a broadcast (RF packet). A broadcast is an RF message that does not necessarily have a single intended receiver. Multiple devices could receive the same broadcast message. The message includes the MD identifier number (Device id# MD). Fig.2 of sending RF Packet 1 (=first message) and also discloses TARRIVAL RD-1 (=a time of arrival of the at least one first message)); receiving, by the at least two second devices, at least one second message from the first device, wherein information regarding a time of departure of the at least one second message is in the at least one second message (Hollar; Fig.1; [0044]-[0045] shows and discloses MD sends out a broadcast (RF packet). A broadcast is an RF message that does not necessarily have a single intended receiver. Multiple devices could receive the same broadcast message. Fig.2 shows and discloses of sending RF packet 2 (=second message) and also shows and discloses TDEPARTt MD-2 (=time of departure of the at least one second message) ; determining, by the at least two second devices, a time of arrival of the at least one second message (Hollar; Fig.1; [0044]-[0045] shows and discloses MD sends out a broadcast (RF packet). A broadcast is an RF message that does not necessarily have a single intended receiver. Multiple devices could receive the same broadcast message. Fig.2 shows and discloses of sending RF packet 2 (=second message) and also shows and discloses TArrival RD-2 (=time of departure of the at least one second message); and wherein a subset of the second clocks and/or the first clock is synchronized with respect to a remaining at least one other second clock of the at least two second devices and/or the first clock based on a weighted zero mean error (Hollar; [0043] discloses A known device (KD) is selected as the master device (MD) illustrated in FIG. 1. The other known devices (KDs) can be synchronized to the selected (MD). As used herein, “synchronized” means that for any given point of time (otherwise called an “event”) that happens or will happen in the future, a KD can directly convert from MD clock units to its KD clock units and vice versa. Here Hollar is applied for the first clock is synchronized with respect to a remaining at least one other second clock of the at least two second devices) Hollar discloses synchronization based on the arrival time and departure time, but fails to explicitly disclose of determining a clock frequency offset. However, Seth discloses determining a clock frequency offset between the first clock and the second clocks based on the time of departure of the at least one first message, the time of arrival of the at least one first message, the time of departure of the at least one second message, and the time of arrival of the at least one second message (Seth; [0016]; Fig.5; [0045]-[0046]) It is obvious for a person of ordinary skilled in the art to combine the teachings before the effective filing date of the invention and calculate the clock offset by a receiving device using time of arrival of a message and a time of departure of the message. One would be motivated to combine the teaching so that the receiving device can send the clock offset to the transmitting device and based on the clock offset the transmitting device can adjust its clock. As to claim 2, the rejection of claim 1 as listed above is incorporated herein. In addition, Hollar-seth discloses wherein the time of departure of the at least one first message is a time, related to the first clock, at which the at least one first message is sent by the first device (Hollar; Fig.1; Fig.2; [0044]-[0045]; [0055]-[0057]) ; the time of arrival of the at least one first message is a time, related to the second clocks, at which the at least one first message is received by the at least two second devices (Hollar; Fig.1; Fig.2; [0044]-[0045]; [0055]-[0057]); the time of departure of the at least one second message is a time, related to the first clock, at which the at least one second message is sent by the first device (Hollar; Fig.1; Fig.2; [0044]-[0045]; [0055]-[0057]); and the time of arrival of the at least one second message is a time, related to the second clocks, at which the at least one second message is received by the second devices (Hollar; Fig.1; Fig.2; [0044]-[0045]; [0055]-[0057]). As to claim 6, the rejection of claim 1 as listed above is incorporated herein. In addition, Hollar-seth discloses wherein the method further comprises: synchronizing the second clocks to the first clock based on the determined clock frequency offset and/or based on a determined clock phase offset (Seth; [0016]; Fig.5; [0045]-[0046]. Here Seth is applied for the 1st alternative the synchronizing the second clocks to the first clock based on the determined clock frequency offset) ; or synchronizing the first clock to the second clocks based on the determined clock frequency offset and/or based on the determined clock phase offset. As to claim 7, the rejection of claim 6 as listed above is incorporated herein. In addition, Hollar-seth discloses wherein the synchronizing of the second clocks or the first clock comprises offsetting timing values of the second clocks or the first clock (Seth; [0016]; Fig.5; [0045]-[0046]). Claims 9, 13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pre-Grant Publication US 2019/0199286 to Seth et al. (hereinafter Seth) in view of U.S. Pre-Grant Publication US 2018/0302869 to Hollar et al. (hereinafter Hollar) As to claims 9 and 15, Seth discloses a system comprising a processor, a receiver and a second clock, wherein: the receiver is arranged to receive a first message from a first device, wherein information regarding a time of departure of the first message is in the first message, and to receive a second message from the first device, wherein information regarding a time of departure of the second message is in the second message (Seth; [0016]; Fig.5; [0045]-[0046]); and the processor is arranged to determine a time of arrival of the first message and a time of arrival of the second message, wherein a clock frequency offset between a first clock of the first device and the second clock is determined based on the time of departure of the first message, the time of arrival of the first message, the time of departure of the second message, and the time of arrival of the second message (Seth; [0016]; Fig.5; [0045]-[0046]) Seth discloses of receiving first message and second message, but fails to disclose wherein the first message and second message are received on a periodic basis. However, Hollar discloses receive, on a periodic basis, a first message from a first device and to receive, on the periodic basis, a second message from the first device (Hollar; Fig.2 shows and discloses RF packet 1 and RF packe 2. [0050] discloses MD sends out periodic broadcasts. The KD receives the periodic broadcasts.) It is obvious for a person of ordinary skilled in the art to combine the teachings before the effective filing date of the invention and sends the 1st message and 2nd message periodically. One would be motivated to combine the teaching in order to use the limited resources in an effective way by sending the messages periodically As to claims 13, the rejection of claim 9 as listed above is incorporated herein. In addition, Seth-Hollar discloses the system comprising: The first device ( Hollar; Fig.1:MD; FiG .2: Root MD) Claims 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pre-Grant Publication US 2019/0199286 to Seth et al. (hereinafter Seth) in view of U.S. Pre-Grant Publication US 2018/0302869 to Hollar et al. (hereinafter Hollar) in view of Applicant submitted prior art EP 2749968 to Sony et al. (hereinafter Sony) As to claim 10, Seth at [0046] discloses the Device A (=second device) sends the Offset back to Device B (=first device) so that Device B can adjust its clock. Using this method, the network knows the frequency offset. Seth-Hollar fails to explicitly discloses of determining clock phase offset between first device and second device. However, Sony discloses further comprising a transmitter, wherein: the transmitter is arranged to send a third message to the first device (Sony; [0006]; [0010]-[0013]); and the processor is further arranged to determine a time of departure of the third message, wherein a clock phase offset between the first clock and the second clock is determined based on the time of arrival of the first message, the time of departure of the first message, the time of arrival of the second message, the time of departure of the second message, the time of departure of the third message, and a time of arrival of the third message (Sony; [0006]; [0010]-[0013]). It is obvious for a person of ordinary skilled in the art to combine the teachings before the effective filing date of the invention. One would be motivated to combine the teaching in order to adjust the time between the master device and slave device. As to claims 11, the rejection of claim 10 as listed above is incorporated herein. In addition, Seth-Hollar-Sony discloses wherein the clock frequency offset and/or the clock phase offset is determined, on the periodic basis, by the processor of the system or by an external device (Seth; [0016]; Fig.5; [0045]-[0047] discloses an example data processing system that can in be included any device associated with the antennas/tags in accordance with embodiments of the present inventive concept . Here Hollar is applied for the 1st alternative) As to claims 12, the rejection of claim 10 as listed above is incorporated herein. In addition, Seth-Hollar-Sony discloses wherein the processor is further arranged to synchronize the second clock to the first clock based on the determined clock frequency offset and/or the determined clock phase offset by offsetting timing values of the second clock (Hollar; [0046] discloses of adjusting clock based on the frequency offset. Here Hollar is applied for the 1st alternative). Allowable Subject Matter Claims 3-5 are objected, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL CHOUDHURY whose telephone number is (571)270-3001. The examiner can normally be reached M-F 8AM-6P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph Avellino can be reached at 5712723905. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAISAL CHOUDHURY/Primary Examiner, Art Unit 2478
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Prosecution Timeline

Dec 12, 2022
Application Filed
Dec 11, 2024
Non-Final Rejection — §103
Apr 17, 2025
Examiner Interview Summary
Apr 17, 2025
Applicant Interview (Telephonic)
May 15, 2025
Response Filed
May 31, 2025
Final Rejection — §103
Nov 04, 2025
Response after Non-Final Action
Dec 04, 2025
Request for Continued Examination
Dec 29, 2025
Response after Non-Final Action
Jan 08, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+15.4%)
2y 9m
Median Time to Grant
High
PTA Risk
Based on 784 resolved cases by this examiner. Grant probability derived from career allow rate.

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