Prosecution Insights
Last updated: April 19, 2026
Application No. 18/079,871

Smart Connector Matrix - an electrical tool to design and test circuits without maneuvering components

Non-Final OA §103§112
Filed
Dec 12, 2022
Examiner
MAUST, TROY A
Art Unit
2189
Tech Center
2100 — Computer Architecture & Software
Assignee
Swaresh Borse
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
3y 6m
To Grant
92%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
77 granted / 102 resolved
+20.5% vs TC avg
Strong +16% interview lift
Without
With
+16.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
11 currently pending
Career history
113
Total Applications
across all art units

Statute-Specific Performance

§101
22.7%
-17.3% vs TC avg
§103
41.2%
+1.2% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
17.9%
-22.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 102 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status Claims 1-3 are pending. Fig. 3-4 are objected to. The specification is objected to. Claim 2 is objected to. Claims 2-3 are rejected under 35 U.S.C. 112(b). Claims 1-3 are rejected under 35 USC 103. Drawings The drawings are objected to because Figures 3 and 4 are illegible when digitally reproduced. See 37 CFR 1.84(l) “Character of lines, numbers, and letters. All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction.” For the sake of examination, the drawings are considered; the original document quality is high enough to be read. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The spacing of the lines of the specification is such as to make reading difficult. New application papers with lines 1 1/2 or double spaced (see 37 CFR 1.52(b)(2)) on good quality paper are required. Claim Objections Claim 2 is objected to because of the following informalities: In claim 2, “An electrical tool as in claim 1” should be “The electrical tool as in claim 1” to refer to claim 1 with correct antecedent basis. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites the limitation “wherein said micro-controller is a plurality of micro-controllers interacting with each other”. It is unclear how a micro-controller could be “a plurality of microcontrollers interacting with each other”. Correction is required. For the sake of examination, it is interpreted that the microcontroller in claim 1 is interacting with a second microcontroller Claim 3 recites the limitation "said software application" in lines 2, 4, and 6. There is insufficient antecedent basis for this limitation in the claim. “said” indicates that there is an initial instance of “a software application” which is not present. Correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Jackson (US 3,922,537) in view of Geist et al. (US 12,197,373 B1). Regarding claim 1, Jackson discloses an electrical tool (Abstract “The present invention pertains to multiplex apparatus for an automatic computerized diagnostic testing system for selectively interconnecting peripheral measurement and stimulus devices to a unit under test (UUT) through various switching subsystems”), capable of communicating with a computer (Abstract “These switch means operate automatically under programmed computer control.”), comprising: a micro-controller (Col. 4 lines 35-40 “In addition, on each card there is a logic element or device controller 7 which is connected to the input/output (1/0) bus 8 of an associated digital computer 9 by the control conductors 9a which receive computer commands.”); a software application (Col. 7 lines 54-57 “A test program, usually constituted of a series of operational steps to be performed upon the UUT by the 55 equipment, is entered into the computer through the operator's terminal 40 (FIG. 6).”); a plurality of reed relays interfacing with said micro-controller (Col. 8 lines 32-36 “S1 is a 1 ampere reed relay. When S1 is closed, link L1 provides connection between a DWG/R test point and the UUT pin. S2 is a 1 ampere reed relay.”); a plurality of connectors interfacing with said reed relays forming a connector matrix to hold electronic components by their electrical pins (Fig. 1-2, Col. 4 lines 20-43, Col. 6 lines 5-7 “Similarly, a cable of conductors 16a from the test fixture 12a converts the UUT pins to the MUX system 12 via the connector 16.”); Jackson does not disclose a USB to UART and UART to USB converter; or and an analog to digital converter interfacing with said micro-controller. Geist teaches a USB to UART and UART to USB converter (Col. 11 lines 38-40 “Referring to FIGS. 11 and 14, the MEB 1100 also includes a USB interface 1128, preferably USB 2.0, is provided for Universal Asynchronous Receiver/Transmitter (UART) over 40 USB functionality.”); and an analog to digital converter interfacing with said micro-controller (Col. 15 lines 49-55 “Each test is specifically designed to check a certain functionality of the SpaceCube hardware. The DUT software 2118 exercises each interface on the SpaceCube processor board 2114, including I/O interfaces (Ethernet, SpaceWire, RS-422 UARTs, etc.), memories (non-volatile and volatile), FPGA configuration interfaces, Analog-to-Digital or Digital-to-Analog devices, and others.”, Col. 12 lines 35-37 “The MEB 1100 further includes an on-board current monitoring ADC 1142 (FIG. 11) which reads out current for each of the low voltage supplies.”). Jackson and Geist are analogous because they are from the “same field of endeavor” electronics testing. Before the effective filing date of the claimed invention, it would have been obvious to one of the ordinary skill in the art, having the teachings of Jackson and Geist before him or her, to modify Jackson to include USB/UART and a DAC as taught by Geist. The suggestion/motivation for doing so would have been Col. 16 lines 18-22 “For testing certain I/O interfaces, such as SpaceWire or UART ports, the GSE software 2112 sends a deterministic 20 test pattern to the DUT software 2118 over the interface under test and the DUT software 2118 echoes the same test pattern back.” The UART port can be used for testing communication. Col. 12 lines 35-37 “The MEB 1100 further includes an on-board current monitoring ADC 1142 (FIG. 11) which reads out current for each of the low voltage supplies.” The analog-digital converter can be used to supply current test data. Regarding claim 2, Jackson in view of Geist teach an electrical tool as in claim 1, and Jackson discloses wherein said micro-controller is a plurality of micro- controllers interacting with each other (See rejection under 35 USC 112(b) for claim interpretation. Col. 4 lines 35-40 “In addition, on each card there is a logic element or device controller 7 which is connected to the input/output (1/0) bus 8 of an associated digital computer 9 by the control conductors 9a which receive computer commands.” Col. 6 lines 25-31 “Each multiplex circuit board, 17, like the circuit boards in the other subsystems, has a logic element or device controller, 17a, and associated digital circuitry electrically connected to the I/O bus of the controlling digital computer and adapted to receive computer 30 commands and control the multiplex circuits on the card in accordance with these commands.”). Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jackson (US 3,922,537) in view of Laldin et al. (US 2022/0291257 A1). Regarding claim 3, Jackson discloses a method of designing and testing circuits physically (Abstract “The present invention pertains to multiplex apparatus for an automatic computerized diagnostic testing system for selectively interconnecting peripheral measurement and stimulus devices to a unit under test (UUT) through various switching subsystems which differ in switching capability, load carrying ability, frequency bandwidth, and mode of operation.”), comprising the steps of: communicating with said software application to receive user commands (Col. 4 lines 35-40 “In addition, on each card there is a logic element or device controller 7 which is connected to the input/output (1/0) bus 8 of an associated digital computer 9 by the control conductors 9a which receive computer commands.”); making and / or breaking several electrical contacts between user defined circuit points with use of said software application (Col. 4 lines 40-44 “Logic circuits on each card respond to the computer commands so as to activate or deactivate designated switches in the relay networks.”); Jackson does not explicitly disclose measuring voltage between two physical points in user designed circuit and displaying said voltage on user interface of said software application. Laldin teaches measuring voltage between two physical points in user designed circuit and displaying said voltage on user interface of said software application ([0012] “[0012] The display interface can be configured to display an analog voltage value based on the magnitude of the voltage at the analog pin.”). Jackson and Laldin are analogous because they are from the “same field of endeavor” electronics testing. Before the effective filing date of the claimed invention, it would have been obvious to one of the ordinary skill in the art, having the teachings of Jackson and Laldin before him or her, to modify Jackson to include voltage measurement and output as taught by Laldin. The suggestion/motivation for doing so would have been Laldin [0006] “The tool can be configured to perform measurements and provide outputs most commonly utilized when developing and diagnosing failures of a hardware platform based around a microcontroller.” Conclusion The examiner respectfully requests, in response to this Office action, support is shown for language added to any original claims on amendment and any new claims. Indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). When responding to this Office Action, the applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111(c). Any inquiry concerning this communication or earlier communications from the examiner should be directed to TROY A MAUST whose telephone number is (571)272-1931. The examiner can normally be reached on Monday-Friday from 8AM to 4PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rehana Perveen, can be reached at telephone number (571) 272-3676. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. /T.A.M./Examiner, Art Unit 2189 /REHANA PERVEEN/Supervisory Patent Examiner, Art Unit 2189
Read full office action

Prosecution Timeline

Dec 12, 2022
Application Filed
Feb 13, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
92%
With Interview (+16.4%)
3y 6m
Median Time to Grant
Low
PTA Risk
Based on 102 resolved cases by this examiner. Grant probability derived from career allow rate.

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