Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is an AIA application filed December 13, 2022.
The earliest effective filing date of this AIA application is seen as December 13, 2022, the actual filing date, there being no earlier priority applications.
The claims originally filed December 13, 2022 are entered, currently outstanding, and subject to examination.
This action is in response to the original filing of the same date.
Claims 1-20 are currently pending and outstanding.
No claims have been amended, cancelled, withdrawn, or added.
Claims 1-20 are currently outstanding and subject to examination.
This is a non-final action and is the first action on the merits.
Allowable subject matter is not indicated below.
Often, in the substance of the action below, formal matters are addressed first, claim rejections second, and any response to arguments third.
Voicemail to Applicant
Examiner called and left a voicemail for Applicant regarding a 35 U.S.C. § 102(b)(2)(c) statement on March 2, 2026. However, researching Applicant’s assignments of record (summaries attached) and finding the primary reference of Mayukh led examiner down a different examination path.
Claim Objections
The following claim is objected to because of the indicated informality/ies:
Claim(s)
Informality/ies
11
"the EIC device" has no antecedent basis in the claim
Appropriate correction is required.
Special Definitions for Claim Language - MPEP § 2111.01(IV)
No special definitions as defined by MPEP § 2111.01(IV) are seen as present in the specification regarding the language used in the claims. Consequently, the words and phrases of the claims are given their plain meaning. MPEP §§ 2173.01, 2173.05(a), and 2111.01.
If special definitions are present, Applicant should bring those to the attention of the examiner and the prosecution history with its next response in a manner both specific and particular. In doing so, there will be no mistake, confusion, and/or ambiguity as to what constitutes the special definition(s). Per above, such special definitions must conform to the requirements of MPEP § 2111.01(IV).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 11-13 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 20230367087 of Mayukh et al. (Mayukh).
With respect to claim 1, Mayukh discloses an apparatus (Figs. 1-6, but particularly Fig. 3), comprising:
a photonic integrated circuit (PIC) device (PIC 320, Fig. 3, ¶ 34) within an opening (right side of Fig. 3) in a glass core substrate (¶ 34, substrate 305, "FIG. 3 is a schematic cross-sectional view of a semiconductor package 300 with an integrated OM in a glass core substrate, in accordance with various embodiments. The semiconductor package 300 includes a substrate 305 having a core 310, one or more dies 315, PIC 320, EIC 325, and an FOC 330a, 330b."),
the PIC device (320) comprising a plurality of first metal bond pads over a surface of the PIC device (¶ 31, "Connections may be routed, for example, through copper pads, copper/metal traces deposited on/in the substrate layer, and through-hole vias, or other suitable interconnects.");
an electronic integrated circuit (EIC) device (EIC 325 and/or die(s) 315) comprising a plurality of second metal bond pads over a surface of the EIC device (325; ¶ 31, "Connections may be routed, for example, through copper pads, copper/metal traces deposited on/in the substrate layer, and through-hole vias, or other suitable interconnects."),
wherein the first metal bond pads are directly bonded to corresponding ones of the second metal bond pads (¶ 37, "For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320."); and
an optical waveguide (core 310) on or within the glass core substrate (¶ 36, "In yet further examples, the core 310 of the substrate 305 may be formed into a waveguide and/or lens, configured to guide and optical signal, through the core 310, to the PIC 320."),
the optical waveguide (310) comprising a terminal end edge coupled to the PIC device within the opening (per Fig. 3 at the left side of PIC 320).
With respect to claim 2, Mayukh as set forth above discloses the apparatus of claim 1, including one wherein
a second surface of the PIC device opposite the surface is substantially coplanar with an upper surface of the glass core substrate.
Per Fig. 3.
With respect to claim 3, Mayukh as set forth above discloses the apparatus of claim 1, including one further comprising:
a microcontroller device (EIC 325 or a duplicate thereof; ¶ 25, "EIC 145 may include electronic components of the OM, such as, without limitation, control circuitry, power circuitry (e.g., electronic amplifiers), filters, converters, and/or other components for managing electrical signals of the OM.” Please note the “control circuitry”.) within a second opening (per Fig. 3) in the glass core substrate (305),
the microcontroller device (325) comprising a plurality of third metal bond pads (additional pads per ¶ 31, "Connections may be routed, for example, through copper pads, copper/metal traces deposited on/in the substrate layer, and through-hole vias, or other suitable interconnects." and ¶ 37, "For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320.") over a surface of the microcontroller device (325),
wherein the third metal bond pads are directly bonded to corresponding ones of the second metal bond pads of the EIC device (¶ 33, "As with the one or more dies 215, the EIC 225 may be coupled to the interposer 210 and/or the PIC 220 utilizing solder bumps (e.g., Cu bumps and/or microbumps) or through copper bonding (e.g., direct copper bonding and/or hybrid copper bonding).” This disclosure is seen to provide regular connections between different circuit elements/dies.).
With respect to claim 4, Mayukh as set forth above discloses the apparatus of claim 1, including one further comprising
a bonding interface between each of the first metal bond pads of the PIC device and the corresponding ones of the second metal bond pads of the EIC device.
This inherently exists in order to establish the connections per ¶ 37 and the coupling of EIC 325 to the PIC 320.
With respect to claim 5, Mayukh as set forth above discloses the apparatus of claim 4, including one wherein
the bonding interface comprises an interdiffusion region of metals from the first and second bond pads.
For product and apparatus claims, when the structure recited in the reference is substantially identical to that of the claims, claimed properties and/or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP § 2112.01(I).
Consequently, because Mayukh as set forth above as set forth above provides the structure of claim 4, the combination is seen as also providing the same claimed properties or functions of claim 5.
Unsupported features are seen to directly result from the supported/claimed structures. No authority is known by which unsupported or “naked” functions/characteristics/features can be claimed and subject to exclusive protection.
Below, this analysis is referred to as “same product/same features”.
With respect to claim 6, Mayukh as set forth above discloses the apparatus of claim 1, wherein the PIC device is abutted against a sidewall of the opening in the glass core substrate or a transparent polymer is between and in contact with the PIC device and the sidewall of the opening.
Per Fig. 3 at the left side of PIC 320
With respect to claim 11, Mayukh as set forth above discloses a system, comprising:
a system substrate (305); and
an electro-optical module (Fig. 3, center right, mostly) coupled to the system substrate (305), the electro-optical module comprising:
a photonic integrated circuit (PIC) device (PIC 320, Fig. 3, ¶ 34) within an opening (right side of Fig. 3) in a glass core substrate (core 310),
the PIC device (320) directly connected to the EIC device (EIC 325 and/or die(s) 315) by interconnects therebetween (¶ 37, "For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320."); and
an optical waveguide (core 310) on or within the glass core substrate (¶ 36, "In yet further examples, the core 310 of the substrate 305 may be formed into a waveguide and/or lens, configured to guide and optical signal, through the core 310, to the PIC 320."),
the optical waveguide (310) comprising a terminal end edge coupled to the PIC device within the opening (per Fig. 3 at the left side of PIC 320).
See claim 1, above.
With respect to claim 12, Mayukh as set forth above discloses the system of claim 11, including one wherein
a surface of the PIC device opposite the EIC device is substantially coplanar with a surface of the glass core substrate.
Fig. 3 shows PIC 320 substantially coplanar with the core 310 surface which is "a surface of the glass core substrate".
With respect to claim 13, Mayukh as set forth above discloses the system of claim 11, further comprising:
a microcontroller device (EIC 325 or a duplicate thereof; ¶ 25, "EIC 145 may include electronic components of the OM, such as, without limitation, control circuitry, power circuitry (e.g., electronic amplifiers), filters, converters, and/or other components for managing electrical signals of the OM.” Please note the “control circuitry”.) within a second opening (per Fig. 3) in the glass core substrate (305),
the microcontroller directly connected to the EIC device by interconnects therebetween (¶ 33, "As with the one or more dies 215, the EIC 225 may be coupled to the interposer 210 and/or the PIC 220 utilizing solder bumps (e.g., Cu bumps and/or microbumps) or through copper bonding (e.g., direct copper bonding and/or hybrid copper bonding).” This disclosure is seen to provide regular connections between different circuit elements/dies.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7 and 14 are rejected under 35 U.S.C. § 103 as being unpatentable over Mayukh as set forth above.
With respect to claim 7, Mayukh as set forth above discloses the apparatus of claim 1, but not one wherein
the opening extends through an entirety of a thickness of the glass core substrate.
Mayukh provides for one or more through-hole vias (Fig. 1, ¶ 22) that pass through an interposer 105 that may be made of glass (¶ 23).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a through-hole configuration for circuit elements (PIC, EIC, etc.) along the lines of Mayukh Fig. 1 in a system according to Mayukh as set forth above in order to provide additional room for dies and/or circuit elements as well as enabling variable/selectable locations for such elements. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the reference) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
the opening extends through an entirety of a thickness of the glass core substrate.
With respect to claim 14, Mayukh as set forth above discloses the system of claim 11, but not one wherein
the opening extends through an entirety of a thickness of the glass core substrate.
Mayukh provides for one or more through-hole vias (Fig. 1, ¶ 22) that pass through an interposer 105 that may be made of glass (¶ 23).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a through-hole configuration for circuit elements (PIC, EIC, etc.) along the lines of Mayukh Fig. 1 in a system according to Mayukh as set forth above in order to provide additional room for dies and/or circuit elements as well as enabling variable/selectable locations for such elements. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the reference) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
the opening extends through an entirety of a thickness of the glass core substrate.
See claim 7, above.
Claims 8, 10, and 15-20 are rejected under 35 U.S.C. § 103 as being unpatentable over Mayukh as set forth above in view of U.S. Patent Application Publication No. 20220216128 of Zhang et al. (Zhang).
With respect to claim 8, Mayukh as set forth above discloses the apparatus of claim 1, but not one further comprising:
a passive cooling structure laterally adjacent the EIC device and on the glass core substrate vertically adjacent the optical waveguide.
Zhang discloses a semiconductor device package having thermally conductive pathways that includes (¶ 10):
"a first thermal conduction means for passively conducting heat generated by the integrated circuit die through the encapsulation means, the first thermal conduction means extending at least partially into the integrated circuit die."
Per ¶ 28 re Fig. 2:
"In some embodiments, heat may be conducted away from the heat-generating components (e.g., IC die 102, NAND dies 112) through thermally conductive material 204 and/or thermally conductive material 208 to the surface treatment 210."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a passive heat sink or cooling structure along the lines of Zhang in a system according to Mayukh as set forth above in order to prevent overheating and/or provide cooling for associated dies/ICs. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
a passive cooling structure laterally adjacent the EIC device and on the glass core substrate vertically adjacent the optical waveguide.
With respect to claim 10, Mayukh as set forth above discloses the apparatus of claim 1, but not one further comprising:
an encapsulation material laterally adjacent the EIC device and on the glass core substrate,
the encapsulation material comprising a surface opposite the glass core substrate that is substantially coplanar with a second surface of the EIC device opposite the surface of the EIC device.
Zhang discloses a semiconductor device package having thermally conductive pathways that includes encapsulation of a semiconductor device package:
¶ 20, "As further illustrated in FIG. 1, one or more components of semiconductor device package 100 are encapsulated by an encapsulant 120, which helps protect the one or more components."
As shown in Fig. 1, the encapsulation layer/encapsulant 120 is highly planar.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to encapsulate the resulting device along the lines of Zhang in a system according to Mayukh as set forth above in order to protect the enclosed components/structures. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the foregoing complete combination would then provide:
an encapsulation material laterally adjacent the EIC device and on the glass core substrate,
the encapsulation material comprising a surface opposite the glass core substrate that is substantially coplanar with a second surface of the EIC device opposite the surface of the EIC device.
With respect to claim 15, Mayukh as set forth above discloses a method, comprising:
providing a glass core substrate,
the glass core substrate comprising an opening therein and the glass core substrate comprising optical waveguide on or within the glass core substrate and having a terminal end adjacent the opening;
direct bonding an electronic integrated circuit (EIC) device to a photonic integrated circuit (PIC) device,
the direct bonding coupling a plurality of first metal bond pads over a surface of the PIC device directly to corresponding ones of a plurality of second metal bond pads over a surface of the EIC device; and
placing the PIC device within the opening;
Mayukh as set forth above does not disclose:
mounting a glass core substrate to a carrier substrate;
forming an encapsulation material over the EIC device and the glass core substrate; and
removing the glass core substrate from the carrier substrate.
Mayukh discloses the use of a carrier substrate in the form of a "glass or silicon carrier". ¶ 41, "Accordingly, in some embodiments, a chip on wafer (CoW) process may be utilized to bond the OM, and specifically the PIC 420, EIC 425, interposer 410, and HBM 415, directly to a glass or silicon carrier."
As can be seen by the drawings, the carrier is ultimately removed to provide the finished device.
As such, mounting and removing elements and devices to and from a carrier substrate is seen as known in the art.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a carrier substrate along the lines of Mayukh per above in a system according to Mayukh as set forth above in order to make/manufacture the device. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the reference) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
mounting a glass core substrate to a carrier substrate, and
removing the glass core substrate from the carrier substrate.
Zhang discloses a semiconductor device package having thermally conductive pathways that includes encapsulation of a semiconductor device package:
¶ 20, "As further illustrated in FIG. 1, one or more components of semiconductor device package 100 are encapsulated by an encapsulant 120, which helps protect the one or more components."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to encapsulate the resulting device along the lines of Zhang in a system according to Mayukh as set forth above in order to protect the enclosed components/structures. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the foregoing complete combination would then provide:
forming an encapsulation material over the EIC device and the glass core substrate; and
mounting a glass core substrate to a carrier substrate,
removing the glass core substrate from the carrier substrate.
With respect to claim 16, Mayukh in view of Zhang as set forth above discloses the method of claim 15, but not one wherein
said direct bonding of the PIC device to the EIC device is performed after said placing the PIC device within the opening.
Selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946), MPEP § 2144.04(IV)(C).
Consequently, the step or order where direct bonding occurs would be obvious.
Below, this is referred to as “step selection”.
Note should be taken that Fig. 3 is seen to generally lend itself to such a step order with the EIC bonded to the PIC after placement of the PIC.
With respect to claim 17, Mayukh in view of Zhang as set forth above discloses the method of claim 15, including one further comprising:
planarizing the encapsulation material to provide a surface of the encapsulation material opposite the glass core substrate that is substantially coplanar with the surface of the EIC device.
Such planarization is generally seen by the indication of flat surfaces in Mayukh Fig. 3.
With respect to claim 18, Mayukh in view of Zhang as set forth above discloses the method of claim 15, further comprising:
direct bonding a microcontroller device (EIC 325 or a duplicate thereof; ¶ 25, "EIC 145 may include electronic components of the OM, such as, without limitation, control circuitry, power circuitry (e.g., electronic amplifiers), filters, converters, and/or other components for managing electrical signals of the OM.” Please note the “control circuitry”.) within a second opening (per Fig. 3) in a glass core substrate (305) to the EIC device (¶ 33, "As with the one or more dies 215, the EIC 225 may be coupled to the interposer 210 and/or the PIC 220 utilizing solder bumps (e.g., Cu bumps and/or microbumps) or through copper bonding (e.g., direct copper bonding and/or hybrid copper bonding).” This disclosure is seen to provide regular connections between different circuit elements/dies.),
the direct bonding coupling a plurality of third metal bond pads over a surface of the microcontroller device directly to corresponding ones of the second metal bond pads of the EIC device (additional pads per ¶ 31, "Connections may be routed, for example, through copper pads, copper/metal traces deposited on/in the substrate layer, and through-hole vias, or other suitable interconnects." and ¶ 37, "For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320.").
The method of claim 18 above would naturally occur in the construction and/or manufacture of a device as set forth in claim 3, above.
With respect to claim 19, Mayukh in view of Zhang as set forth above discloses the method of claim 15, but not one further comprising:
providing a transparent polymer between and in contact with the PIC device and a sidewall of the opening.
Fig. 2 of Mayukh shows an interposer adjacent to a PIC 220.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include an interposer along the lines of Mayukh Fig. 2 in a system according to Mayukh in view of Zhang as set forth above in order to provide additional routing and/or features (Mayukh, ¶ 14). This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
providing a transparent polymer between and in contact with the PIC device and a sidewall of the opening.
With respect to claim 20, Mayukh in view of Zhang as set forth above discloses the method of claim 15, including one further comprising:
securing a passive cooling structure or an active cooling device laterally adjacent the EIC device and on the glass core substrate vertically adjacent the optical waveguide.
See claim 8, above.
Zhang discloses a semiconductor device package having thermally conductive pathways that includes (¶ 10):
"a first thermal conduction means for passively conducting heat generated by the integrated circuit die through the encapsulation means, the first thermal conduction means extending at least partially into the integrated circuit die."
Per ¶ 28 re Fig. 2:
"In some embodiments, heat may be conducted away from the heat-generating components (e.g., IC die 102, NAND dies 112) through thermally conductive material 204 and/or thermally conductive material 208 to the surface treatment 210."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a passive heat sink or cooling structure along the lines of Zhang in a system according to Mayukh as set forth above in order to prevent overheating and/or provide cooling for associated dies/ICs. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
a passive cooling structure laterally adjacent the EIC device and on the glass core substrate vertically adjacent the optical waveguide.
Alternatively, it should be noted that Nakanishi, below, discloses an active cooling structure.
Claims 9 is rejected under 35 U.S.C. § 103 as being unpatentable over Mayukh as set forth above in view of U.S. Patent No. 5403783 of Nakanishi et al. (Nakanishi).
With respect to claim 9, Mayukh as set forth above discloses the apparatus of claim 1, but not one further comprising:
an active cooling device laterally adjacent the EIC device and on the glass core substrate vertically adjacent the optical waveguide,
wherein the active cooling device comprises one or more microchannels to flow cooling fluid therein.
Nakanishi discloses an integrated circuit substrate with cooling accelerator substrate that includes (Fig. 6, col. 6, ll. 11 and adjacent):
"As shown in FIG. 6, the cooling substrate 100 may include coolant passages 12 defined by wall portions 101 of the cooling substrate 100 and by a cover 102. The cover 102 is fixed onto the cooling substrate 100 with an interface 103 by the covalent bond as described before. The coolant 5 is preferably an electrical insulator. The cooling substrate 100 and the integrated circuit substrate 3 may be immersed in the electrically insulating coolant 5 of liquid type, or may be cooled by the electrically insulating coolant 5 of gas type."
As such, Nakanishi provides a cooling substrate 100 for an IC substrate 3, cooling substrate 100 having microchannels in coolant passages 12.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use an active heat sink/cooling system along the lines of Nakanishi in a system according to Mayukh as set forth above in order to provide controlled and/or additional cooling. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optical module) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
an active cooling device laterally adjacent the EIC device and on the glass core substrate vertically adjacent the optical waveguide,
wherein the active cooling device comprises one or more microchannels to flow cooling fluid therein.
Conclusion
Applicant’s publication US 20240194657 A1 published June 13, 2024 is cited.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited references have elements related to Applicant’s disclosure and/or claims or are otherwise associated with the other cited references, particularly with respect to opto-electronic systems and the like.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas (Tom) HOLLWEG can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andrew Jordan/
Primary Examiner, Art Unit 2874
V: (571) 270-1571 (Pacific time)
F: (571) 270-2571
March 5, 2026