DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/08/2026 has been entered.
Response to Arguments
Claims 1-13 are pending, independent claims 1 and 10 and dependent claims 4, 7, 8, and 12 are amended.
Applicant’s arguments on pages 9-13, filed 01/08/2026 with respect to U.S.C. 103 rejection of claims 1-13 have been fully considered but they are not considered persuasive.
Applicant argues that Tamaru, Sato, and Hartzsch do not teach all the limitations of the amended material in independent claims 1 and 10, specifically wherein the processor is configured to determine the failure based on presence or absence of output of the PWM signal and whether a high level state or a low level state is maintained, specifically because Tamaru and Sato do not teach determine the failure based on whether a high level state or a low level state is maintained, and Hartzsch fails to make up for the deficiencies.
Examiner respectfully disagrees. Examiner has found that Tamaru teaches a failure determined by a high level state or a low level state being detected, see [0082]. Hartzsch teaches the detection of a high level or a low level state being maintained in claim 79. It would be reasonable for one of ordinary skill in the art to combine detecting the high or low level state being maintained for a period of time via the switch over being greater than a specific threshold to Tamaru and Sato having already detecting a failure based on if there is a high level (shot to batter or open fault) being detected or a low level (shot to ground) being detected. For at least these reasons, Applicant's arguments are not persuasive.
Applicant argues that Tamaru does not teach the amended limitation "wherein when the PWM signal is not output for a specified first time and the high level state is maintained, the processor determines that a "SBOP (Shot to Battery or Open)" has occurred in a pulse width modulation (PWM) signal line” originally from claim 7, and that Tamaru does not teach the amended limitation "wherein when the PWM signal is not output for the specified first time and the low level state is maintained, the processor determines that a "SG (Shot to Ground)" has occurred in the PWM signal line," originally from claim 8, because Tamaru is silent on the signal being a Pulse width modulation.
Examiner respectfully agrees that Tamaru does not teach the signal being a pulse width modulation, to make up for the deficiencies in the argument, Examiner has added the use of Sato teaching pulse width modulation as the signal in the signal line, found in Col 2 line 43-51. For at least these reasons, Applicant's arguments are not persuasive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamaru (JP 2012257375 A) in view of Sato (US 9436171 B2) and Hartzsch (US 2017/0242075 A1).
Regarding Claim 1, Tamaru teaches an encoder configured to detect rotation information of a motor ([0011] “ an encoder that outputs a pulse signal (hereinafter also referred to as an encoder signal) in synchronization with the rotation of the rotor, detects the rotational position of the rotor based on a count value of the pulse signals,”); and an interface configured to transmit rotation information detected by the encoder to a processor ([0011] “ a CPU (i.e. processor) that has m number of ports to which the pulse signals are input, the ports being electrically connected to the output unit via m number of first signal lines (i.e., interface) through which the pulse signals flow, counting each of the m number of pulse signals input to the m ports, and controlling the rotation drive of the rotor to a target position based on the count value counted by the CPU itself and phase information output from the selection unit.,”, where [0011] “an encoder that outputs a plurality of pulse signals in synchronization with the rotation of the rotor”), wherein the processor is configured to control the motor based on the rotation information of the motor received through the interface ([0011] “the motor control device (i.e., processor) includes a counting section to which all pulse signals output by the encoder are input and counts each pulse signal individually (i.e., counting section has an interface with the encoder to receive the signal output from the encoder), an abnormality diagnosis section which diagnoses whether or not there is an abnormality for each pulse signal based on the counting result by the counting section, and a selection section which selects m output systems required to drive and control the rotation of the motor (i.e., motor is controlled based on the rotation information) from the output systems that output pulse signals diagnosed as normal based on the diagnosis result by the abnormality diagnosis section,”, where [0011] “a motor control device according to claim 1 is a motor control device that drives a motor”) and configured to detect a failure of the encoder and the interface based on the rotation information ([0039] “when two or more of the encoder signals 1 to 3 are abnormal, the state is determined to be 5, and the abnormal encoder signal judgment value is determined to be a multiple encoder failure.), configured to determine the failure based on presence or absence of output of the signal ([0082] “Further, in the present embodiment, not only the failure of a single encoder but also the effect of the encoder signal connector or harness grounding, disconnection, or power failure, the reliability of the entire system can be improved (i.e., disconnection would cause an absence of signal). ” Where [0011] “configured to rotationally drive a motor provided with an encoder that outputs a plurality of pulse signals in synchronization with the rotation of the rotor.”, absence of signal); and determine the failure based on whether a high or low state is detected ([0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault, breakage, or short-to-power (i.e., shot to battery failure) fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.”, where a short to power is when a different point in the circuit, bypassing the intended path for the current. This creates a low-resistance path, causing a large current to flow (i.e., high level state); [0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault (i.e., shot to ground failure), breakage, or short-to-power fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.” Where an electrical short circuit where electricity is flowing through an unintended path to the ground instead of the intended circuit, creating a low-resistance path for the current (low level state)); the high level state is detected for the signal, the processor determines that a "SBOP (Shot to Battery or Open)" has occurred in a signal line ([0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault, breakage, or short-to-power (i.e., shot to battery) fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.”, where a short to power is when a different point in the circuit, bypassing the intended path for the current. This creates a low-resistance path, causing a large current to flow (i.e., high level state)); and the low level state is detected for the signal, the processor determines that a "SG (Shot to Ground)" has occurred in the signal line ([0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault (i.e., shot to ground), breakage, or short-to-power fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.” Where an electrical short circuit where electricity is flowing through an unintended path to the ground instead of the intended circuit, creating a low-resistance path for the current (low level state)).
Tamaru does not teach a pulse width modulation (PWM) signal indicating operation status (angle) information in pulse width form; determine whether a high level state or a low level state is maintained; wherein when the PWM signal is not output for a specified first time.
Sato teaches a pulse width modulation (PWM) signal indicating operation status (angle) information in pulse width form (“A motor control device of the present invention is a control device configured to receive a PWM command signal including a plurality of pulse periods having different pulse-period durations from one another, and each of which a duty factor, i.e. a ratio of a pulse width to pulse-period duration, is modulated by a command signal, and to control operation of a motor in a manner to rotate according to the command signal restored from the PWM command signal received.” Col 2 line 43-51; col 6 lines 8-14 “PWM modulating section 120 determines individual pulse-period duration first, and then determines a pulse width (i.e., pulse width form) corresponding to speed command signal Vr with reference to the determined pulse-period duration in every process of generating each pulse.”); wherein when the PWM signal is not output for a specified first time (“Subsequently, at time too in FIG. 3, number of counts Cnt of the counter in timer output section 123 becomes 0 (zero). Timer output section 123 turns PWM command signal Si into an ON state at this point in time. The counter then starts counting up one by one. Timer output section 123 continues to keep the ON state of PWM command signal Si for a period in which the number of counts Cnt is smaller than count value Non(0). Timer output section 123 turns PWM command signal Si into an OFF state, and outputs preparation command signal Pn at a point (time t01) (i.e., PWM signal is not output for the specified first time) when number 15 of counts Cnt becomes equal to count value Non(0)” col 11 line 6-16; “A motor control device of the present invention is a control device configured to receive a PWM command signal including a plurality of pulse periods having different pulse-period durations from one another, and each of which a duty factor, i.e. a ratio of a pulse width to pulse-period duration, is modulated by a command signal, and to control operation of a motor in a manner to rotate according to the command signal restored from the PWM command signal received.” Col 2 line 43-51).; and after a specified debounce time has elapsed (“The counter in timer output section 123 starts counting from 0 (zero), and continues the counting up to count value Ntp. Timer output section 123 outputs an ON state for a period in which the number of counts Cnt comes from 0 (zero) to count value Non while the counting is continued in the above manner. Thereafter, timer output section 123 outputs an OFF state for another period from the point in time when number of counts Cnt exceeds count value Non and until it comes to count value Ntp (i.e., where the off period has elapsed).” Col 10 line 20-22, where debounce time is a period of time in which things are not recording values).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the use of a PWM signal for angle discussed in Sato to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru for the purpose of being able to read the angle information of the motor drive. This is advantageous because it allows for the angle of the motor drive to be read from a separate signal so it can be read independently from other signals.
Tamaru and Sato do not teach determine the failure based on whether a high level state or a low level state is maintained.
Hartzsch teaches determine whether a high level state or a low level state is maintained. ([claim 79 “A method for obtaining an indication of a possible faulty load condition of a multi-phase electric motor with electric commutation and electric drive control, the motor including a plurality of motor phases and having a drive unit which, per motor phase, comprises a high-side (i.e., high level state) switch and a low-side (i.e., low level state) switch, wherein the high-side and low-side switches of the motor phases are cyclically switched according to a switching scheme which generates time points at which a current through a motor phase experiences, in the motor phase, a zero crossing that, owing to an inductive load portion of the electric motor, is temporally shifted relative to a time point of the zero crossing which would occur with purely ohmic loads, wherein, without a faulty load condition, the time point of the zero crossing is within an expected value range, comprising, detecting, during one of a predetermined high-side and low-side phase connection occurring in the switching scheme, a time when the current through one of a switched-on high-side and switched-on low-side switch becomes greater or smaller than a presettable threshold value, measuring, from a presettable time point of the switching scheme, a time interval within which the current through the one of the switched-on high-side and switched-on low-side switch of one of the plurality of motor phases becomes greater or smaller than the presettable threshold value, comparing one of (1) the measured time intervals of the individual motor phases among each other, and (2) the measured time intervals of each motor phase with one or more other measured time intervals from the respective motor phase and (3) the measured time intervals of the respective motor phases with presettable respective expected value ranges, and evaluating a deviation, from presettable expected value ranges, of (a) the amount of the measured time intervals in the motor phases among each other and (b) the amount of the measured time intervals in one motor phase with one or more other measured intervals from the respective motor phase, as being an indication of a faulty load condition (i.e, failure).”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine detecting a failure depending on level status as discussed in Hartzsch to the system for detecting a failure of a motor drive as discussed in Tamaru and Soto for the purpose of evaluating voltage drops to determining faulty load conditions. This is advantageous because short circuits are normally detected on the basis of voltage drops along the drain-source paths of the internal or external driver transistors of the drive unit that are used to drive the electric motors or other loads (e.g., [0003], Hartzsch).
Regarding Claim 10, Tamaru teaches detecting, by an encoder, rotation information of a motor([0011] “ an encoder that outputs a pulse signal (hereinafter also referred to as an encoder signal) in synchronization with the rotation of the rotor, detects the rotational position of the rotor based on a count value of the pulse signals,”); receiving, by a processor, rotation information detected by the encoder through an interface; ([0011] “ a CPU (i.e. processor) that has m number of ports to which the pulse signals are input, the ports being electrically connected to the output unit via m number of first signal lines (i.e., interface) through which the pulse signals flow, counting each of the m number of pulse signals input to the m ports, and controlling the rotation drive of the rotor to a target position based on the count value counted by the CPU itself and phase information output from the selection unit.,”, where [0011] “an encoder that outputs a plurality of pulse signals in synchronization with the rotation of the rotor”), controlling, by the processor, the motor based on the rotation information of the motor received through the interface ([0011] “the motor control device (i.e., processor) includes a counting section to which all pulse signals output by the encoder are input and counts each pulse signal individually (i.e., counting section has an interface with the encoder to receive the signal output from the encoder) an abnormality diagnosis section which diagnoses whether or not there is an abnormality for each pulse signal based on the counting result by the counting section, and a selection section which selects m output systems required to drive and control the rotation of the motor (i.e., motor is controlled based on the rotation information) from the output systems that output pulse signals diagnosed as normal based on the diagnosis result by the abnormality diagnosis section,” where [0011] “a motor control device according to claim 1 is a motor control device that drives a motor”) and detecting, by the processor, a failure of the encoder and the interface based on the rotation information ([0039] “when two or more of the encoder signals 1 to 3 are abnormal, the state is determined to be 5, and the abnormal encoder signal judgment value is determined to be a multiple encoder failure.” Where [0011] “the motor control device (i.e., processor) includes a counting section to which all pulse signals output by the encoder are input and counts each pulse signal individually, an abnormality diagnosis section which diagnoses whether or not there is an abnormality for each pulse signal based on the counting result by the counting section,”); configured to determine the failure based on presence or absence of output of the signal ([0082] “Further, in the present embodiment, not only the failure of a single encoder but also the effect of the encoder signal connector or harness grounding, disconnection, or power failure, the reliability of the entire system can be improved (i.e., disconnection would cause an absence of signal). ” Where [0011] “configured to rotationally drive a motor provided with an encoder that outputs a plurality of pulse signals in synchronization with the rotation of the rotor.”, absence of signal); and determine the failure based on whether a high or low state is detected ([0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault, breakage, or short-to-power (i.e., shot to battery failure) fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.”, where a short to power is when a different point in the circuit, bypassing the intended path for the current. This creates a low-resistance path, causing a large current to flow (i.e., high level state); [0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault (i.e., shot to ground failure), breakage, or short-to-power fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.” Where an electrical short circuit where electricity is flowing through an unintended path to the ground instead of the intended circuit, creating a low-resistance path for the current (low level state)); the high level state is detected for the PWM signal, the processor determines that a "SBOP (Shot to Battery or Open)" has occurred in a pulse width modulation (PWM) signal line ([0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault, breakage, or short-to-power (i.e., shot to battery) fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.”, where a short to power is when a different point in the circuit, bypassing the intended path for the current. This creates a low-resistance path, causing a large current to flow (i.e., high level state)); and the low level state is detected for the PWM signal, the processor determines that a "SG (Shot to Ground)" has occurred in the PWM signal line ([0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault (i.e., shot to ground), breakage, or short-to-power fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.” Where an electrical short circuit where electricity is flowing through an unintended path to the ground instead of the intended circuit, creating a low-resistance path for the current (low level state)).
Tamaru does not teach a pulse width modulation (PWM) signal indicating operation status (angle) information in pulse width form; determine whether a high level state or a low level state is maintained; wherein when the PWM signal is not output for a specified first time.
Sato teaches a pulse width modulation (PWM) signal indicating operation status (angle) information in pulse width form (“A motor control device of the present invention is a control device configured to receive a PWM command signal including a plurality of pulse periods having different pulse-period durations from one another, and each of which a duty factor, i.e. a ratio of a pulse width to pulse-period duration, is modulated by a command signal, and to control operation of a motor in a manner to rotate according to the command signal restored from the PWM command signal received.” Col 2 line 43-51; col 6 lines 8-14 “PWM modulating section 120 determines individual pulse-period duration first, and then determines a pulse width (i.e., pulse width form) corresponding to speed command signal Vr with reference to the determined pulse-period duration in every process of generating each pulse.”); wherein when the PWM signal is not output for a specified first time (“Subsequently, at time too in FIG. 3, number of counts Cnt of the counter in timer output section 123 becomes 0 (zero). Timer output section 123 turns PWM command signal Si into an ON state at this point in time. The counter then starts counting up one by one. Timer output section 123 continues to keep the ON state of PWM command signal Si for a period in which the number of counts Cnt is smaller than count value Non(0). Timer output section 123 turns PWM command signal Si into an OFF state, and outputs preparation command signal Pn at a point (time t01) (i.e., PWM signal is not output for the specified first time) when number 15 of counts Cnt becomes equal to count value Non(0)” col 11 line 6-16; “A motor control device of the present invention is a control device configured to receive a PWM command signal including a plurality of pulse periods having different pulse-period durations from one another, and each of which a duty factor, i.e. a ratio of a pulse width to pulse-period duration, is modulated by a command signal, and to control operation of a motor in a manner to rotate according to the command signal restored from the PWM command signal received.” Col 2 line 43-51).; and after a specified debounce time has elapsed (“The counter in timer output section 123 starts counting from 0 (zero), and continues the counting up to count value Ntp. Timer output section 123 outputs an ON state for a period in which the number of counts Cnt comes from 0 (zero) to count value Non while the counting is continued in the above manner. Thereafter, timer output section 123 outputs an OFF state for another period from the point in time when number of counts Cnt exceeds count value Non and until it comes to count value Ntp (i.e., where the off period has elapsed).” Col 10 line 20-22, where debounce time is a period of time in which things are not recording values).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the use of a PWM signal for angle discussed in Sato to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru for the purpose of being able to read the angle information of the motor drive. This is advantageous because it allows for the angle of the motor drive to be read from a separate signal so it can be read independently from other signals.
Tamaru and Sato do not teach determine the failure based on whether a high level state or a low level state is maintained.
Hartzsch teaches determine whether a high level state or a low level state is maintained. ([claim 79 “A method for obtaining an indication of a possible faulty load condition of a multi-phase electric motor with electric commutation and electric drive control, the motor including a plurality of motor phases and having a drive unit which, per motor phase, comprises a high-side (i.e., high level state) switch and a low-side (i.e., low level state) switch, wherein the high-side and low-side switches of the motor phases are cyclically switched according to a switching scheme which generates time points at which a current through a motor phase experiences, in the motor phase, a zero crossing that, owing to an inductive load portion of the electric motor, is temporally shifted relative to a time point of the zero crossing which would occur with purely ohmic loads, wherein, without a faulty load condition, the time point of the zero crossing is within an expected value range, comprising, detecting, during one of a predetermined high-side and low-side phase connection occurring in the switching scheme, a time when the current through one of a switched-on high-side and switched-on low-side switch becomes greater or smaller than a presettable threshold value, measuring, from a presettable time point of the switching scheme, a time interval within which the current through the one of the switched-on high-side and switched-on low-side switch of one of the plurality of motor phases becomes greater or smaller than the presettable threshold value, comparing one of (1) the measured time intervals of the individual motor phases among each other, and (2) the measured time intervals of each motor phase with one or more other measured time intervals from the respective motor phase and (3) the measured time intervals of the respective motor phases with presettable respective expected value ranges, and evaluating a deviation, from presettable expected value ranges, of (a) the amount of the measured time intervals in the motor phases among each other and (b) the amount of the measured time intervals in one motor phase with one or more other measured intervals from the respective motor phase, as being an indication of a faulty load condition (i.e, failure).”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine detecting a failure depending on level status as discussed in Hartzsch to the system for detecting a failure of a motor drive as discussed in Tamaru and Soto for the purpose of evaluating voltage drops to determining faulty load conditions. This is advantageous because short circuits are normally detected on the basis of voltage drops along the drain-source paths of the internal or external driver transistors of the drive unit that are used to drive the electric motors or other loads (e.g., [0003], Hartzsch).
Regarding Claim 4 and 12, Tamaru, Sato and Hartzsch teaches the limitations of Claims 1 and 10, respectively.
Tamaru further teaches wherein the processor is further configured to detect a failure of the encoder itself and electrical failures occurring in first and second signal lines of the interface and the (PWM) signal line ([0005] “a fault diagnosis is performed on the encoder itself provided on the motor or on the signal path (signal line, etc.) from the encoder to the CPU (i.e., electrical failures occurring in first and second signal lines of the interface and a pulse width modulation (PWM) signal line).”).
Claim(s) 2 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Tamaru, Sato and Hartzsch and in view of Takayuki (JP H05265541 A).
Regarding Claim 2 and 11, Tamaru teaches the limitations of Claims 1 and 10.
Tamaru further teaches, first and second signals ([0011] “outputs all pulse signals (n signals, n is m+p) of a plurality of pulse signals (m signals, m is a natural number of 2 or more) (i.e., first and second signals) required to drive and control the rotation of the motor”).
Tamaru, Sato and Hartzsch do not teach teaches signal indicating rotation direction information.
Takayuki teaches pulse width modulation (PWM) signal indicating the rotation direction information ([0006] “calculates the change amounts
Δ
up and
Δ
down of pulses per unit time in phase A and phase B of the signal output from an encoder,” where [0007] “if there is a change in the A phase when the rotation command direction is clockwise, then
Δ
up=8 and
Δ
down=0.” And [0015] “when the phase of the B-phase signal leads the phase of the A-phase signal by go0 , it indicates a counterclockwise rotation, and a change appears only on the down pulse side, while no change occurs on the up-pulse side.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to discuss direction that the signals control in the motor drive discussed in Takayuki to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru, Sato and Hartzsch for the purpose of being able to change the direction of the motor drive and run tests on the signals. This is advantageous because it would allow for the change amount in the phase opposite to the phase specified by the rotation command direction of the driven object to be checked and monitored (e.g., [0006] Takayuki).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamaru, Sato and Hartzsch in view of Hachiman (JP 2001208812 A) and further in view of Ikeda (JP 2003115881 A).
Regarding Claim 3, Tamaru, Sato and Hartzsch teaches the limitations of claim 1.
Tamaru, Sato and Hartzsch does not teach a first series resistor connecting a first signal line configured to output a first signal of the encoder to a designated terminal of the processor; a second series resistor connecting a second signal line configured to output a second signal of the encoder to the designated terminal of the processor; and a third series resistor and a pull-up circuit connecting a signal line configured to output the PWM signal of the encoder to the designated terminal of the processor.
Hachiman teaches a first series resistor connecting a first signal line configured to output a first signal of the encoder to a designated terminal of the processor (Fig. 4 where S1 (first signal line) has a resistor that the output of the signal passes through), a second series resistor connecting a second signal line configured to output a second signal of the encoder to the designated terminal of the processor (Fig. 4 where S3 (first signal line) has a resistor that the output of the signal passes through).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the resistors discussed in Hachiman to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru, Sato and Hartzsch for the purpose of having resistors to connect the signal line to designated terminals. This is advantageous because using resistors in the signal path connections will help prevent excessive current flow, ensure known signal states, and provide resistance for voltage splitting.
Tamaru, Sato, Hartzsch and Hachiman do not teach a third series resistor and a pull-up circuit connecting a signal line configured to output the PWM signal of the encoder to the designated terminal of the processor.
Ikeda teaches a third series resistor and a pull-up circuit connecting a signal line configured to output a PWM signal of the encoder to the designated terminal of the processor ([0005] “R31 and R32 (i.e., third series resistors) are pull-up/down resistors (i.e., pull-up circuit) connected to the signal line 68, (referencing Fig 7)”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine a third resistor and a pull up circuit discussed in Ikeda to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru, Sato and Hartzsch for the purpose of ensuring a known signal state for the signal path when the input is not actually active. This is advantageous because it keeps the signal in a high state while not actively driven, to further prevent noise and signal disruptions and allow for reliable signal integrity.
Claim(s) 5, 6, 9, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamaru, Sato, Hartzsch, Hachiman and Takayuki.
Regarding Claim 5 and 13, Tamaru teaches the limitations of Claims 4 and 10.
Tamaru, Sato and Hartzsch does not teach wherein in order to detect the failure in the encoder itself, the processor determines that there is a possibility that the encoder is in an abnormal state, when there is no change in the state of a first and a second signals regardless of a rotation direction of the motor, or when the state of the first and second signal does not change in a specified order and changes in an unspecified order according to the rotation direction of the motor.
Hachiman teaches when there is no change in the state of signals regardless of a rotation direction of the motor ([0014] “only a fixed angle is output regardless of the rotation of the motor, if this failure is not accurately transmitted and the motor is controlled, it may rotate a fixed angle in an unintended direction when starting to move, or may decelerate while moving, causing violent vibrations, which could result in a serious problem that could lead to a traffic accident.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the lack of change in signals state regardless the motor drive rotation discussed in Hachiman to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru for the purpose of being able to test the abnormal behavior of the motor drive apparatus. This is advantageous because a fixed angle output failure when not accurately, may cause a rotation of a fixed angle in an unintended direction when starting to move, or may decelerate while moving, causing violent vibrations, which could result in a serious problem that could lead to a traffic accident (e.g., [0014] Hachiman).
Tamaru, Sato, Hartzsch and Hachiman do not teach wherein in order to detect the failure in the encoder itself, the processor determines that there is a possibility that the encoder is in an abnormal state; when the state of the first and second signal does not change in a specified order and changes in an unspecified order according to the rotation direction of the motor.
Takayuki teaches wherein in order to detect the failure in the encoder itself, the processor determines that there is a possibility that the encoder is in an abnormal state([0006-0007] “the encoder abnormality detection method of the present invention calculates the change amounts Δup and Δdown of pulses per unit time in phase A and phase B of the signal output from an encoder, and checks the change amount in the phase opposite to the phase specified by the rotation command direction of the driven object, and if this value is not 0, it is determined that the encoder signal is abnormal.); when the state of the first and second signals does not change in a specified order and changes in an unspecified order according to the rotation direction of the motor ([0018] “In this example, since the rotation command direction is clockwise, a change usually appears only in the A phase. Therefore, the change amount of the phase opposite to the A phase specified by the rotation command direction, that is, the B phase, is checked to determine whether the value is "0" or not. In FIG. 3, since a Δup pulse of 3 and a Δdown pulse of 2 are inserted between i and i−1, the Δdown of the B phase does not become 0 (i.e., does not change in a specified order and changes in an unspecified order according to the rotation direction of the motor). Therefore, it is determined that there is an abnormality in the encoder signal.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to discuss abnormalities that can occur in the motor drive discussed in Takayuki to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru, Sato, Hartzsch and Hachiman for the purpose of being able to test and type the abnormal behavior of the motor drive apparatus. This is advantageous because not being able to detect the type of abnormality could mean the restoration of the system takes a long time and leaves the possibility of an unsolved abnormality causing the system to be forced out of control, and make a dangerous environment (e.g., [0004] Takayuki).
Regarding Claim 6, Tamaru, Sato, Hartzsch, Hachiman and Takayuki teach all the limitations of Claim 5.
Tamaru further teaches wherein when it is determined that there is a possibility that the encoder is in the abnormal state, the processor performs an Invalid Count, wherein when the Invalid Count is greater than or equal to a specified first reference count for a specified reference time, the processor resets an Invalid Counter ([0038] “The abnormality diagnosis logic circuit 40 determines an abnormal phase (abnormal encoder signal) based on the count values (i.e., invalid count) L_1 to L_n (here, L_1 to L_3) output from the respective counter circuits 31 by mutual comparison thereof.”, and [0039] “when all of the encoder signals 1 to 3 are normal, |L_1-L_2|, |L_1-L_3|, and |L_2-L_3| are all less than K1(i.e., first specific reference count for a specific time)” where an example of an abnormal state is [0039] “when the encoder signal 1 is abnormal, |L_1-L_2| and |L_1-L_3| are greater than K1, |L_2-L_3| is equal to or smaller than K1”, where [0035] “In other words, the counter section 30 receives all the pulse signals output by the encoder and counts each pulse signal individually.” Meaning the counter is reset at the beginning of each pulse signals test), and wherein when the Invalid Count increases above a specified second reference count for the specified reference time, the processor determines the failure of the encoder ([0038] “The abnormality diagnosis logic circuit 40 determines an abnormal phase (abnormal encoder signal) based on the count values (i.e., invalid count) L_1 to L_n (here, L_1 to L_3) output from the respective counter circuits 31 by mutual comparison thereof.”, and [0039] “when all of the encoder signals 1 to 3 are normal, |L_1-L_2|, |L_1-L_3|, and |L_2-L_3| are all less than K1, and ΣL (the sum of the count values L_1 to L_n (here, L_1 to L_3)) is greater than a predetermined value (K0) (i.e., second reference count).” where an example of an abnormal state is [0039] “when the encoder signal 1 is abnormal, |L_1-L_2| and |L_1-L_3| are greater than K1, |L_2-L_3| is equal to or smaller than K1, and ΣL is greater than K0.”)
Regarding Claim 9, Tamaru, Sato, and Hartzsch, teaches the limitations of Claim 4.
Tamaru further teaches first and second signal lines of the interface ([0011] “a CPU (i.e. processor) that has m number of ports to which the pulse signals are input the ports being electrically connected to the output unit via m number of first signal lines (i.e., interface) through which the pulse signals flow,”), the processor forcibly drives the motor in a first direction and the processor forcibly drives the motor in a second direction ([0003] “the rotational drive of the motor by switching the current-carrying phase of the motor in a predetermined sequence via a motor driver based on the count value of the A-phase signal (i.e., signal in the first direction) and the count value of the B-phase signal (i.e., signal in the second direction).” Where [0023] “The motor control device drives and rotates a motor 10 equipped with an encoder that outputs a pulse signal (hereinafter also referred to as an encoder signal) in synchronization with the rotation of the rotor, detects the rotational position of the rotor based on the count value of the pulse signal, and controls and rotates the rotor to a target position (position control) by switching the current phase (i.e., phase of A and B signal control the direction of the motor) of the motor 10 based on the detection result.).
Tamaru, Sato, and Hartzsch does not teach wherein when there is no abnormality in the PWM signal of the encoder, calculates the rotation angle of the motor by the PWM signal and the rotation angle of the motor calculated by the first and second signals of the encoder to check the angle difference and wherein when the angle difference identified is greater than a specified failure reference angle, the processor determines that an electrical failure occurs in the first and second signal lines of the interface.
Hachiman teaches wherein when there is no abnormality in the PWM signal of the encoder ([0018] “in the normal mode in which the "normal" command is output, it is expected that the angle detection circuit 6 can operate normally as usual, and the failure detection means 3 informs the microcomputer 1 that there is no failure.”), calculates the rotation angle of the motor by the PWM signal and the rotation angle of the motor calculated by the first and second signals of the encoder to check the angle difference ([0036] “The R/D converter 2 calculates the difference (θ-φ) between the motor angle θ and the virtual angle φ, performs tracking control so as to eliminate this difference, and outputs this virtual angle φ as the motor angle.”), and wherein when the angle difference identified is greater than a specified failure reference angle ([0036] “The R/D converter 2 calculates the difference (θ-φ) between the motor angle θ and the virtual angle φ, performs tracking control so as to eliminate this difference, and outputs this virtual angle φ as the motor angle. If the motor angle θ and the virtual angle φ do not match (i.e., difference is greater than specified reference angle of 0) due to some kind of failure, the output angle information φ will not match the true motor angle. Therefore, this (θ-φ) is monitored, and an increase in this value indicates a failure (i.e., electrical failure).”), the processor determines that an electrical failure occurs in the signal lines ([0050] “if the information becomes constant at 0 level due to a short circuit in the signal line during the transmission of fault information, for example, the specified duty signal or digital data will not be received, and it can be instantly detected that there is a problem in the transmission of the fault information.” Where [0059] “if there is a fault anywhere including in the fault detection means 3, a diagnostic function abnormality flag is set (discussing the steps in Fig. 14 that are performed by the microcomputer (i.e., processor).”) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the angle difference discussed in Hachiman to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru, Sato, and Hartzsch for the purpose being able to quantify the amount of error in the motor drive. This is advantageous because it gives a quantity in which the device can be altered/fixed so that the motor drive is no longer running in an erroneous fashion.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamaru, Sato, Hartzsch and Hachiman.
Regarding Claim 7, Tamaru teaches the limitations of Claim 4.
Tamaru further teaches determining that a "SBOP“ has occurred ([0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault, breakage, or short-to-power (i.e., shot to battery) fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.”, where a short to power is when a different point in the circuit, bypassing the intended path for the current. This creates a low-resistance path, causing a large current to flow (i.e., high level state)).
Tamaru do not teach after a specified debounce time has elapsed, the processor determines a fault and blocks a motor output end.
Sato teaches wherein after a specified debounce time has elapsed (“The counter in
timer output section 123 starts counting from 0 (zero), and continues the counting up to count value Ntp. Timer output section 123 outputs an ON state for a period in which the
number of counts Cnt comes from 0 (zero) to count value Non while the counting is continued in the above manner. Thereafter, timer output section 123 outputs an OFF state for another period from the point in time when number of counts Cnt exceeds count value Non and until it comes to count value Ntp (i.e., where the off period has elapsed).” Col 10 line 20-22, where debounce time is a period of time in which things are not recording values).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the specific debounce time discussed in Sato to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru for the purpose of not sending out signal while the motor test is restarting/recalibrating. This is advantageous because it allows for possibly false signal to be blocked when the test system resets.
Tamaru, Sato and Hartzsch does not teach the processor determines a fault and blocks a motor output end .
Hachiman teaches the processor determines a fault and blocks a motor output end ([0060]“Here, if the diagnosis function abnormality flag is set, there is a failure somewhere including the failure detection means 3, so the motor is not energized in process 139 and the occupant is notified of the abnormality.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the debounce time and the processor stopping the motor after finding fault discussed in Hachiman to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru, Sato and Hartzsch for the purpose of preventing the motor from continuing to run once a failure has been determined. This is advantageous because it stops the system from continuing to run in an abnormal condition and prevents errors, breakage, and other damage to the motor drive apparatus.
Regarding Claim 8, Tamaru, Sato and Hartzsch teaches the limitations of claim 4.
Tamaru further teaches determining that a "SG” has occurred ([0082] “this embodiment is effective not only in the event of a failure of the encoder itself, but also in the event of a ground fault (i.e., shot to ground), breakage, or short-to-power fault in the encoder signal connector or harness, thereby improving the reliability of the entire system.” Where an electrical short circuit where electricity is flowing through an unintended path to the ground instead of the intended circuit, creating a low-resistance path for the current (low level state)).
Tamaru does not teach after a specified debounce time has elapsed, the processor determines a fault and blocks a motor output end.
Sato teaches after a specified debounce time has elapsed (“The counter in timer output section 123 starts counting from 0 (zero), and continues the counting up to count value Ntp. Timer output section 123 outputs an ON state for a period in which the number of counts Cnt comes from 0 (zero) to count value Non while the counting is continued in the above manner. Thereafter, timer output section 123 outputs an OFF state for another period from the point in time when number of counts Cnt exceeds count value Non and until it comes to count value Ntp (i.e., where the off period has elapsed).” Col 10 line 20-22, where debounce time is a period of time in which things are not recording values).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the specific debounce time discussed in Sato to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru for the purpose of not sending out signal while the motor test is restarting/recalibrating. This is advantageous because it allows for possibly false signal to be blocked when the test system resets.
Tamaru, Sato and Hartzsch does not teach after a specified debounce time has elapsed, and the processor determines a fault and blocks a motor output end.
Hachiman teaches wherein the processor determines a fault and blocks the motor output end ([0060]“Here, if the diagnosis function abnormality flag is set, there is a failure somewhere including the failure detection means 3, so the motor is not energized in process 139 and the occupant is notified of the abnormality.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the debounce time and the processor stopping the motor after finding fault discussed in Hachiman to the apparatus for detecting a failure of motor drive circuit discussed in Tamaru, Sato and Hartzsch for the purpose of preventing the motor from continuing to run once a failure has been determined. This is advantageous because it stops the system from continuing to run in an abnormal condition and prevents errors, breakage, and other damage to the motor drive apparatus.
Conclusion
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/EMMA ALEXANDER/ Patent Examiner, Art Unit 2863
/Catherine T. Rastovski/ Supervisory Primary Examiner, Art Unit 2863