DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 10, 11, 15, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2023/0097189 to Chen et al. (“Chen”) in view of US Patent No. 8,949,768 to Gupta et al. (“Gupta”).
As to independent circuit claim 1, independent system claim 16, and independent circuit claim 19, Chen teaches: an integrated circuit designing system (¶ Fig. 10 discloses a EDA environment.) comprising: at least one processor; and a non-transitory storage medium storing instructions (¶ 0003. EDA tools inherently include a processor and CRMs.) that, when executed by the at least one processor, cause the system to perform a method (¶ 0003. Systems and methods disclosed.) comprising:
accessing a cell library having a plurality of first cells and a plurality of second cells, wherein each first cell comprises corresponding two or more transistor devices and has a corresponding height (¶ 0007, 0024, 0027, 0030, 0040. Chen teaches accessing a cell library with a plurality of first and second cells comprising two or more transistor devices and having different heights measured parallel to the gate structure. Chen discloses synthesizing circuit using standard cells retrieved from at least a cell library from the standard cell library portfolio 111 and that the first standard cell and second standard cell have the same logic function but have different cell heights. Chen further teaches the cell height H2 of the second standard cell Cell-B is smaller than the cell height H1 of the first standard cell Cell-A. Chen also discloses the cells have two or more transistors: “The intersecting area of the gate line 130 and the active region 120p forms a p-type metal oxide semiconductor transistor (PMOS)…The intersecting area of the gate line 130 and the active region 120n forms an n-type metal oxide semiconductor transistor (NMOS)”. Regarding, “height measured in a direction parallel to a length of a gate structure”, Chen teaches cell height is taken along the second direction Y and between an upper edge and a lower edge (¶ 0021), and the gate line 130 extends along the second direction Y (¶ 0027).);
receiving data about a circuit to be implemented using the first cells and the second cells; and designing an integrated circuit structure to implement the circuit (¶ 0003, 0040. Chen teaches receiving circuit data and designing a structure to implement it via a typical design process.), the integrated circuit structure comprising:
a plurality of first cells(¶ 0027, 0030. Chen teaches each Cell-A has two or more transistors.); and a plurality of second cells(¶ 0027, 0030. Chen teaches each Cell-B has two or more transistors.);
wherein the plurality of first cells and the plurality of second cells are arranged in a plurality of rows, such that (i) a row of the plurality of rows includes a first cell laterally adjacent to a second cell (¶ 0008, 0024. Chen teaches arranging cells of different heights such that they are laterally adjacent in the same row.), (ii) an imaginary line passes through the first cell, and divides the first cell into a first upper portion having a first upper height and first low portion having a first lower height that are within 1 nm of each other, and (iii) the imaginary line passes also through the second cell, and divides the second cell into a second upper portion having a second upper height and a second lower portion having a second lower height that are within 1 nm of each other (¶ 0027, 0030, 0035. Chen teaches centerlines 114 and 214 bisect both abutted cells into equal (i.e., arguably “within 1 nm of each other”) upper and lower halves.);
a first transistor device comprising a first source region, a first drain region, a first body comprising semiconductor material extending from the first source region to the first drain region, and a first gate structure on the first body; a second transistor device laterally adjacent to the first transistor device, the second transistor device comprising a second source region, a second drain region, a second body comprising semiconductor material extending from the second source region to the second drain region, and a second gate structure on the second body (¶ 0027. Chen teaches the structure of the laterally adjacent first and second transistor devices. Chen teaches portions of the active regions 120p and 120n at the left side are source regions S of the PMOS and NMOS. The portions of the active regions 120p and 120n at the right side of the gate line 130 are drain regions D of the PMOS and the NMOS. Because the cells are abutted side-by-side (¶ 0024, 0031), devices near the abutment edge in each cell are laterally adjacent across the cell boundary.);
a first rail conductor above or below the first source drain region, and coupled to one of the first source or drain region; and a second rail conductor above or below the second source or drain region, and coupled to one of the second source or drain region (¶ 0029, 0032, Chen teaches the Cell-A includes a power rail 140 and a ground rail 150, and that conductive connectors 142 and 152 are arranged at a same side of the gate line 130, respectively connect to the power rail 140 and the ground rail 150 and partially overlap the source region S of the active regions.);
wherein a first dimension of the first source region is (¶ 0030. Chen teaches a width of the active region 220p, a width of the active region 220n of the second standard Cell-B are respectively smaller than a width of the active region 220p and 220n of the first standard cell Cell-A.); and
wherein the first and second rail conductors are colinear and extend in a second direction perpendicular to the first direction (¶ 0008, 0021, 0023, 0027, 0032. Chen defines the gate lines as extending along a Y-direction and the continuous voltage rails extending along an X-direction, these directions are perpendicular to each other. Furthermore, Chen teaches the rails are colinear by disclosing the power and ground rails of the shorter cells are shifted until their centerlines are aligned with the centerlines of the taller cell’s rails, allowing them to connect smoothly so that continuous power 340 and ground rails 350 are obtained.).
Chen does not explicitly disclose the numerical thresholds recited in the claims, namely, that the plurality of first and second cells have a corresponding height that is specifically “within 1 nanometer (nm)” of a first or second height, the second height is “at least 3nm smaller” than the first height, and the first dimension of the first source region is “at least 2 nanometers greater” than the second dimension of the second source region.
Gupta teaches modern IC manufacturing operates at nanometer scale minimum feature sizes and therefore uses tight dimensional controls and tolerances, including tolerances “as tight as possible (e.g., 1 nm)” (1:21-36, 24:3-14.). Gupta further teaches applying small, nanometer scale layout variations to geometric features to optimize circuit/layout objectives, including defining an “amount of change” by nanometer values in a range such as 1-10 nm (9:20-37, claim 1.).
A POSITA recognizes the Chen teaches each standard cell includes a centerline that divides the cell into two equal portions, but Chen doesn’t not explicitly quantify the tolerance associated with this division or the dimensional relationship between the portions. In view of Gupta’s teaching that nanometer scale tolerances are routinely applied in IC design and manufacturing, it would have been obvious to a POSITA to implement Chen’s centerline defined equal division and cell height uniformity using a tolerance within 1 nm in order to ensure the layout complies with the tight dimensional control required at advanced technology nodes.
Furthermore, Chen teaches the second standard cell is smaller than the first standard cell, including having a smaller cell height and smaller active region dimensions. Chen, however, does not quantify the magnitude of these dimensional differences. Because Chen already teaches the dimensions of the second cell are smaller than those of the first cell, and Gupta teaches implementing layout variations using nanometer scale dimensional adjustments in the range of 1-10 nm, it would have been obvious to a POSITA to implement Chen’s dimensional differences using nanometer scale variations within the range taught by Gupta. Selecting differences of at least 3 nm for the cell height and at least 2 nm for source-drain region dimension would have been a routine design choice within the known nanometer scale range for adjusting IC layout geometries.
As to claim 2, the integrated circuit structure of claim 1, wherein: the first cell comprises a first diffusion region having a first diffusion height; the second cell comprises a second diffusion region having a second diffusion height; the first and second diffusion heights are measured in the direction parallel to the first height and the second height; and the second diffusion height is at least 2 nm smaller than the first diffusion height (As disclosed above, Chen teach an IC structure having cells of different heights. Chen discloses the cells induce diffusion/active regions and teaches the active region dimensions of the smaller cells are smaller than those of the larger cell (¶ 0030). Chen further discloses transistor structures formed where gate lines intersect the active regions, stating “the intersecting area of the gate line 130 and the active region 120p forms a p-type metal oxide semiconductor transistor (PMOS)” and similarly for the NMOS transistor (¶ 0027). Thus, Chen teaches first and second cells each comprising diffusion (active) regions associated with transistor devices and teaches the diffusion regions of the smaller cell are dimensionally smaller than those of the larger cell. As disclosed above, Gupta teaches using nanometer scale dimensional differences. The combination of the Chen and Gupta yields implementing the dimensional difference between the diffusion regions of Chen’s larger and smaller cells of at least 2 nm.).
As to claim 3, the integrated circuit structure of claim 1, wherein: the first cell comprises a first gate structure having a first gate height; the second cell comprises a second gate structure having a second gate height; the first and second gate heights are measured in the direction parallel to the first height and the second height; and the second gate height is at least 2 nm smaller than the first gate height (As disclosed above, Chen teaches cells having gate structures formed over active regions to form transistor devices. Chen teaches gate lines extend across the active regions to form PMOS and NMOS devices (¶ 0030). Chen further teaches the dimensions of features in the smaller cell are smaller than those in the larger cell, including the active region dimensions of the second cell are smaller than those of the first cell. Thus, Chen teaches first and second cells including gate structures associated with transistor devices and teaches that the smaller cell includes correspondingly smaller device features than the larger cell. As disclosed above, Gupta teaches using nanometer scale dimensional differences. The combination of the Chen and Gupta yields implementing the dimensional differences in Chen’s gate structures of at least 2 nm.).
As to claim 10, the integrated circuit structure of claim 1, further comprising:
a first rail conductor to supply power or ground connection to one or more transistor devices of the first cell; and a second rail conductor to supply power or ground connection to one or more transistor devices of the second cell; wherein the first rail conductor and the second rail conductor extend in direction perpendicular to the first height and the second height, and wherein the first rail conductor and the second rail conductor are colinear (Chen: ¶ 0032. Chen teaches shifting the power and ground rails of the shorter cell along the Y direction until they align with the rails of the taller cell, such that the continuous power 340 and ground rails 350 are obtained. Chen defines the rails as extending along the X direction, which is perpendicular to the Y direction (the height direction).).
As to claim 11, the integrated circuit structure of claim 10, wherein: the first rail conductor is above or below one or more diffusion regions of the corresponding one or more transistor devices of the first cell; and the second rail conductor is above or below one or more diffusion regions of the corresponding one or more transistor devices of the second cell (Chen: ¶ 0029. Chen teaches placing the rail conductors over the diffusion (active) regions in the standard BEOL metal layers. Because the power rails are connected to the diffusion regions via vertical contact plugs and conductive connectors built on layout layers (e.g., metal-1 layer), the rail conductors inherently reside “above” the semiconductor diffusion regions in planar stack.).
As to claim 15, the integrated circuit structure of claim 1, wherein:
the height of a given cell included in the first or second pluralities is a distance between opposing first and second edges of the given cell, and length of a gate structure of a given cell extends (1) away from the first edge and toward the second edge and (2) over semiconductor regions of the two or more transistor devices of the given cell; and the first upper and lower heights of the first cell and the second upper and lower heights of the second cell are measured in a direction parallel to the first height and the second height (Chen discloses the overall cell height is measured along the Y-direction (¶ 0027). Chen further teaches dividing the abutment box into two equal parts via the X-axis centerline. By geometric definition, the distances from this centerline to the upper and lower edges (the upper and lower heights) are inherently measured along the exact same Y-axis (parallel to the overall cell height).).
As to claim 18, the integrated circuit designing system of claim 16, wherein the instructions cause the system to perform the method further comprising designing a first rail conductor to supply power or ground connection to one or more transistor devices of the first short cell; and
designing a second rail conductor to supply power or ground connection to one or more transistor devices of the first tall cell; wherein the first rail conductor and the second rail conductor extend in direction perpendicular to the first height and the second height, and wherein the first rail conductor and the second rail conductor are colinear (Chen: ¶ 0008, 0021, 0023, 0027, 0032. Chen teaches designing standard cells having power and ground rails supplying transistor devices of the cells. Chen discloses a standard cell include power rail 140 and ground rail 150, and that conductive connectors 142 and 152 connect to power rail 140 and the ground rail 150 and partially overlap the source regions, thereby supplying power or ground to transistor devices of the cell. Chen further teaches when a taller cell and shorter cell are placed adjacent to one another, the power rail and the ground rail of the second standard cell are shifted to align and connect to the power rails and ground rail of the first standard cell, thereby forming continuous rails. Chen’s figures and description disclose the rails extending in the X-direction (row), which is perpendicular to the Y-direction (height).).
As to claim 20, the integrated circuit structure of claim 19, wherein a first length of the first gate structure is at least 2 nanometers greater than a second length of the second gate structure (Chen in view of Gupta teaches, as shown above, differing transistor gate dimensions using nanometer scale dimensional differences, including selecting a difference of at least 2 nm.).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Gupta and in further view of US Patent No. 8,013,367 to Doris et al. (“Doris”).
Chen in view of Gupta teach the limitations of claim 1 from which claim 13 depends, including the source/drain and gate line. The combination, however, does not expressly define the “width of the gate structure” as extending in the source-to-drain direction.
Doris explicitly defines channel width (i.e., width under the gate) as being in a direction that is parallel to the current flow of the FET (Abstract.). Because current flow is between source and drain, this teaches the same directional relationship recited in claim 13.
It would have been obvious to a POSITA to apply Doris’s conventional device geometry definition of gate/channel width along the source-to-drain (current flow) direction when implementing and/or describing Chen’s transistors (which already have explicitly identified source region, drain region, and gate line). The application fulfills the routine need in IC layout/device description and sizing to use standardized geometric definitions to characterize and control transistor dimensions consistently across cells and libraries.
Claims 14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Gupta and in further view of US Pub. No. 9,871,040 to Shimbo (“Shimbo”).
Chen in view of Guta teaches a mixed height standard cell framework implementing tight nm-scale controls, but does not teach the standard cells use fin-based devices/structures.
Shimbo teaches using fin-based devise with standard cells (Abstract.).
It would have been obvious to a POSITA to implement the semiconductor regions of Chen’s transistor devices using the fin-based transistor structures taught by Shimbo, because Shimbo teaches FinFet-based standard cells for implementing logic cells in ICs, and FinFET device structures are well-known alternatives to planar transistor active regions for improving device scaling and performance.
Allowable Subject Matter
Claims 4-8, 9, 12, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4-8, 9, 12, and 17 would be allowable if amended in the manner above because the prior art of record does not teach or suggest a circuit structure or system having all the combinations of elements as recited in and required by claims 4, 9, 12, or 17. Claims 5-8 depend from claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SURESH MEMULA/Primary Examiner, Art Unit 2851