Detailed action
Summary
1. The office action is in response to application filed on 12/24/2022.
2. Claims 1-17 are pending and have been examined.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Uno et al. (US 20130001792) in view of Chen et al. (US 20190140630).
Regarding Claim 1. Uno et al. disclose A die (figures 1, 2 and 60; (para. 0113)), comprising: a first current sense terminal (-tv terminal of amp 1; as shown on figure 60); a second current sense terminal (+ve terminal of Amp 1; as shown on figure 60): a main power transistor (QH1); a current sense transistor (QS1) having a source electrically connected to a source of the main power transistor (source terminal of QH1); a diode device (Diode connecting VIN to current mirror) electrically connected in series between a drain of the main power transistor (QH1) and a drain of the current sense transistor (QS1); a first voltage protection device electrically connecting the drain of the main power transistor to the first sense terminal; and a second voltage protection device electrically connecting the drain of the current sense transistor to the second sense terminal (it is also possible to connect a diode (not shown schematically) for protection between the source of the power MOSFET QH1 and the source of the sense MOSFET QS1 as a first and second voltage protection devices).
but fails to explicitly disclose GaN (gallium nitride) die and GaN current sense transistor.
Uno et al. disclose GaN (gallium nitride) die (para. 0011) and GaN current sense transistor (SW_MAIN) (para. 0012).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Uno et al. with the teaching of Chen et al. to provide integrated overcurrent and short circuit protection for devices and systems comprising GaN transistors, which mitigates or circumvents one or more limitations of known solutions, or at least provides an alternative (para. 0009).
Regarding Claim 2. Uno et al. disclose A die (figures 1, 2 and 60; (para. 0113)).
but fails to explicitly disclose wherein a channel width of the GaN current sense transistor is in a range of 1:2000 to 1:4000 of a channel width of the main GaN power transistor.
Uno et al. disclose (figure 1) wherein a channel width of the GaN current sense transistor is in a range of 1:2000 to 1:4000 of a channel width of the main GaN power transistor ( For a large gate width high current/high voltage lateral GaN power transistors, a gate width ratio wg/Wg in the range of 1:500 or 1:1000, or even 1:2000 may provide acceptable performance, while the integrated drain voltage sense circuitry takes up minimal area on the GaN die) (para. 0050).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Uno et al. with the teaching of Chen et al. to provide integrated overcurrent and short circuit protection for devices and systems comprising GaN transistors, which mitigates or circumvents one or more limitations of known solutions, or at least provides an alternative (para. 0009).
Regarding Claim 3. Uno et al. disclose a die (figures 1, 2 and 60; (para. 0113)), wherein the diode device is a transistor having a drain electrically connected to the drain of the main power transistor (QH1), a source electrically connected to the drain of the current sense transistor (QS1), and a gate electrically connected to the drain of the transistor (as shown on figure 60).
but fails to explicitly disclose GaN (gallium nitride) die and GaN current sense transistor.
Uno et al. disclose GaN (gallium nitride) die (para. 0011) and GaN current sense transistor (SW_MAIN) (para. 0012).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Uno et al. with the teaching of Chen et al. to provide integrated overcurrent and short circuit protection for devices and systems comprising GaN transistors, which mitigates or circumvents one or more limitations of known solutions, or at least provides an alternative (para. 0009).
Regarding Claim 4. Uno et al. disclose A die (figures 1, 2 and 60; (para. 0113)), wherein the diode device (Diode connecting VIN to current mirror) is a pn diode having an anode electrically connected to the drain of the main power transistor (QH1) and a cathode electrically connected to the drain of the current sense transistor (QS1).
but fails to explicitly disclose GaN (gallium nitride) die and GaN current sense transistor.
Uno et al. disclose GaN (gallium nitride) die (para. 0011) and GaN current sense transistor (SW_MAIN) (para. 0012).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Uno et al. with the teaching of Chen et al. to provide integrated overcurrent and short circuit protection for devices and systems comprising GaN transistors, which mitigates or circumvents one or more limitations of known solutions, or at least provides an alternative (para. 0009).
Regarding Claim 7. Uno et al. disclose A die (figures 1, 2 and 60; (para. 0113)).
but fails to explicitly disclose wherein each of the main GaN power transistor, the GaN current sense transistor, the first voltage protection device, and the second voltage protection device is a Schottky-gate HEMT (high electron mobility transistor) device.
Uno et al. disclose (figure 1) wherein each of the main Gan power transistor, the Gan current sense transistor, the first voltage protection device, and the second voltage protection device is a Schottky-gate HEMT (high electron mobility transistor) device (with reference to simulation results based on a lateral GaN power switch SW_MAIN, which comprises a large area, large gate width lateral GaN E-HEMT. Simulation results for a GaN E-HEMT in the form of a 650V/50 mΩ device which has a gate width Wg=300 mm and a drain-source on-resistance, Rdson, of 50 mΩ are shown in FIGS. 2 to 4) (para. 0040).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Uno et al. with the teaching of Chen et al. to provide integrated overcurrent and short circuit protection for devices and systems comprising GaN transistors, which mitigates or circumvents one or more limitations of known solutions, or at least provides an alternative (para. 0009).
6. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Uno et al. (US 20130001792) in view of Chen et al. (US 20190140630) further in view of Bernacchia et al. (9791881).
Regarding Claim 2. Combination of Uno et al. and Chen et al. disclose a die (figures 1, 2 and 60; (para. 0113)).
but fails to explicitly disclose wherein a channel width of the GaN current sense transistor is in a range of 1:2000 to 1:4000 of a channel width of the main GaN power transistor.
Bernacchia et al. disclose (figure 1) wherein a channel width of the GaN current sense transistor is in a range of 1:2000 to 1:4000 of a channel width of the main GaN power transistor ( the areas of transistors M2 and M1 are in a ratio of 1 to N, so that, because the operating conditions are the same, sense transistor M2 carries 1/N the current flowing through power transistor M1) (Column 3, line 66-Column 4, line 8).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify combination of Uno et al. and Chen et al. with the teaching of Bernacchia et al. to provide the areas of transistors M2 and M1 in a ratio of 1 to N, so that the operating conditions are the same
and improve the efficiency of the circuit.
Allowable Subject Matter
7. Claims 8-17 are allowed.
8. The following is an examiner’s statement of reasons for allowance:
Regarding claim 8. The prior art fails to teach “…a first voltage protection device electrically connecting the drain of the main GaN power transistor of the first sense terminal, and a second voltage protection device electrically connecting the drain of the GaN current sense transistor to the second sense terminal; and a current sense circuit electrically connected to the first and second current sense terminals, wherein the first voltage protection device is configured to protect the current sense circuit from the full drain voltage of the main GaN power transistor and the second voltage protection device is configured to protect the current sense circuit from the full drain voltage of the GaN current sense transistor.”
Dependent claims 9-17 are allowable by virtue of their dependency.
9. Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5. The prior art fails to teach “…wherein the first voltage protection device is a first GaN transistor having a drain electrically connected to the drain of the main GaN power transistor, a source electrically connected to the first sense terminal, and a gate electrically connected to the source of the first GaN transistor, and wherein the second voltage protection device is a second GaN transistor having a drain electrically connected to the drain of the GaN current sense transistor, a source electrically connected to the second sense terminal, and a gate electrically connected to the source of the second GaN transistor. “
Regarding claim 6. The prior art fails to teach “… wherein the first voltage protection device is a first GaN transistor used exclusively as a switch device and configured to be on when the main GaN power transistor is on and to be off when the main GaN power transistor is off, and wherein the second voltage protection device is a second GaN transistor used exclusively as a switch device and configured to be on when the GaN current sense transistor is on and fo be off when the GaN current sense transistor is off.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
11. Examiner's Note(s)
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim(s), other passages and figures may apply as well.
Additionally, in the event that other prior art is provided and made of record by the Examiner, as being relevant or pertinent to applicant's disclosure but not relied upon. The references are provided for the convenience of the applicant. The Examiner request that the references be considered in any subsequent amendments, as they are also representative of the teaches of the art and may apply to the specific limitations of any newly amended claim(s)
It is respectfully requested from the applicant in preparing amendments or responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art and/or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied upon in order to ensure proper interpretation of the newly added limitations and to verify/ascertain the metes and bounds of the claimed invention.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
//AFEWORK DEMISSE//
Examiner, Art Unit 2838
/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
Prosecution Insights