DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment dated 02/26/2026 has been entered. Claims 1, 2, 8 & 10 are amended. Claims 12-20 are canceled. Claims 21-29 are newly added. Claims 1-11, 21-29 remain pending in applications.
Response to Arguments
Argument dated 02/26/026 have been acknowledged but are moot as new ground of rejection is made in view of same primary reference YADA and none of the arguments apply to the new rejection. Particularly, redefining “a stack structure” as “stack of 46 & 32 excluding bottommost pair of 46 & 32, see as marked above”, see as marked in annotated FIG. 18A below, YADA still reads on the amended limitation . Associated rejection reproduced below.
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and wherein the channel structure comprises a semiconductor channel (601 & 602) and a memory film (including blocking dielectric layer 52, charge storage layer 54 & tunneling dielectric layer 56, FIG. 18B, para [0070]) over the semiconductor channel, the semiconductor channel comprises an angled structure (see as marked in FIGs. 18A-18B above), and the angled structure is disposed between the first semiconductor layer (10) and a bottommost conductive layer of the first conductive layers (bottommost 46 of the stack as marked in FIG. 18A above).
Based on this, examiner argues, the rejection is still proper and thus made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3,6,8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YADA et al. (US 2019/0067025 A1)
Regarding claim 1, YADA teaches,
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A three-dimensional (3D) memory device (FIGs. 18A-18B), comprising:
a stack structure (stack of 46 & 32 excluding bottommost pair of 46 & 32, see as marked above) comprising interleaved first conductive layers (46, para [0125], FIG. 18A) and first dielectric layers (32, para [0125];
a channel structure (including 601 & 602, para [0082],[0069] FIG. 18A) extending through the stack structure along a first direction (vertical direction) in contact with a first semiconductor layer (10, para [0043]) at a bottom portion of the channel structure;
and a slit structure extending through the stack structure along the first direction, comprising:
a slit core (76, para [0130], FIG. 18A);
and a second dielectric layer (including 74 & 12, para [0126], para [0048]) surrounding the slit core(FIG. 18A),
wherein a first width of the second dielectric layer near the first semiconductor layer (width of 74 & 12) is larger than a second width of the second dielectric layer (width of 74) away from the first semiconductor layer.
and wherein the channel structure comprises a semiconductor channel (601 & 602) and a memory film (including blocking dielectric layer 52, charge storage layer 54 & tunneling dielectric layer 56, FIG. 18B, para [0070]) over the semiconductor channel, the semiconductor channel comprises an angled structure (see as marked in FIGs. 18A-18B above), and the angled structure is disposed between the first semiconductor layer (10) and a bottommost conductive layer of the first conductive layers (bottommost 46 of the stack as marked in FIG. 18A above).
Regarding claim 2, YADA teaches the 3D memory device of claim 1 and further teaches, wherein a third width of the semiconductor channel at the bottom portion of the channel structure below the angled structure(width of 602 below the angled structure in FIG. 18B above) is smaller than a fourth width of the semiconductor channel at an upper portion of the channel structure above the angled structure (width of 601 & 602 above the angled structure in FIG. 18B above).
Regarding claim 3, YADA teaches the 3D memory device of claim 1 and further teaches, further comprising: a second semiconductor layer (layer of 61, para [0128], FIG. 18A above) below the stack structure, wherein the second semiconductor layer is below a bottom surface of the second dielectric layer (12, FIG. 18A)
Regarding claim 6, YADA teaches the 3D memory device of claim 3 and further teaches, further comprising: a third semiconductor layer (layer of 11 as marked in FIG. 18A above, para [0069]) between the second semiconductor layer (61) and the stack structure, wherein a top surface of the third semiconductor layer (61) is coplanar to the bottom surface of the second dielectric layer (12, see FIG. 18A).
Regarding claim 8, YADA teaches,
A three-dimensional (3D) memory device (Figs. 18A-18B as annotated above), comprising:
a first stack structure comprising a first semiconductor layer (10, para [0043]), a second semiconductor layer (61, para [0128]) above the first semiconductor layer, and a third semiconductor layer (layer of 11, para [0069], see above) surrounding the first semiconductor layer (10) and the second semiconductor layer (61)(see FIG. 18A as annotated above);
a second stack structure (stack of 46 & 32 excluding bottommost pair of 46 & 32, para [0125] see as marked in FIG. 18A above) above the first stack structure, comprising interleaved first conductive layers (46) and first dielectric layers (32);
and a channel structure (including 601 & 602, FIG. 18A) extending through the second stack structure along a first direction (vertical direction) in contact with the third semiconductor layer (11) at a bottom portion of the channel structure (FIG. 18A),
and wherein the channel structure comprises a semiconductor channel (601 & 602) and a memory film (including blocking dielectric layer 52, charge storage layer 54 & tunneling dielectric layer 56, FIG. 18B) over the semiconductor channel, the semiconductor channel comprises an angled structure (see as marked in FIGs. 18A-18B above), and the angled structure is disposed between the first semiconductor layer (10) and a bottommost conductive layer of the first conductive layers (bottommost 46 of the stack as marked in FIG. 18A above).
Regarding claim 9, YADA teaches the 3D memory device of claim 8 and further teaches , further comprising: a slit structure (including 76 & 74) extending through the second stack structure along the first direction, comprising:
a slit core (76, para [0130]) extending through the second stack structure along the first direction in contact with the third semiconductor layer (in indirect contact with 11 via intervening layers 74 and 12) ;
and a second dielectric layer (including 74 & 12) surrounding the slit core, FIG. 18A),
wherein a first width of the second dielectric layer (width of 74 & 12) contacting the third semiconductor layer (11) is larger than a second width of the second dielectric layer (width of 74) away from the third semiconductor layer
Regarding claim 10, YADA teaches the 3D memory device of claim 8 and further teaches, wherein a third width of the semiconductor channel at the bottom portion of the channel structure below the angled structure (width of 602 below the angled structure in FIG. 18B above) is smaller than a fourth width of the semiconductor channel at an upper portion of the channel structure above the angled structure (width of 6001 & 602 above the angled structure in FIG. 18B above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over YADA et al. and further in view of CUI et al. (US 2022/0045092 A1)
Regarding claim 5, YADA teaches the 3D memory device of claim 3 but does not explicitly teach, wherein the second semiconductor layer comprises a p-type doping polysilicon layer.
YADA additionally teaches,
61 is a source region formed by implantation of dopants in to material layer 10 (para [0128]). 10 can be formed of any material that can be employed for substrate layer 9 (para [0047]) which can be other semiconductor material known in art [0043]).
And Cui teaches,
source level semiconductor layer (i.e. source material layer) can be a doped semiconductor material such as doped polysilicon or doped amorphous silicon ( para [0076]).
And it is widely known in art dopant can be p type or n type.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use p doped polysilicon as a source material layer of 61 such that the second semiconductor layer (61) comprises a p-type doping polysilicon layer, according to the teaching of CUI, in order to form 61 as a source region, as taught by YADA above, since it has been held that choosing from a finite number of identified, predictable solutions such as doped polysilicon or amorphous silicon , with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Allowable Subject Matter
Claims 4,7, 11, 21 & 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 4, 7, 11, 21 & 22, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
wherein the second semiconductor layer is below a bottom surface of the semiconductor channel, and a top surface of the second semiconductor layer is ammonia (NH3) treated(claim 4).
wherein the third semiconductor layer comprises an undoped polysilicon layer, and a top surface of the third semiconductor layer is ammonia (NH3) treated (claim 7)
wherein the first semiconductor layer comprises a p-type doping polysilicon layer, and the second semiconductor layer comprises an undoped polysilicon layer(claim 11).
wherein the channel structure comprises a dielectric core in a center of the channel structure, and the dielectric core extends into the first semiconductor layer(claim 21)
wherein the channel structure comprises a dielectric core in a center of the channel structure, and the dielectric core extends into the third semiconductor layer(claim 22).
Claims 23-29 are allowed.
With respect to claim 23, the prior art made of record does not teaches or suggest either alone or in combination “and wherein the second semiconductor layer is below a bottom surface of the semiconductor channel, and a top surface of the second semiconductor layer is ammonia (NH3) treated” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
The above limitation incorporates allowable subject matter of original claim 4 as indicated in previous office action.
Claims 24-29 are allowed being dependent on claim 23.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. (FP 7.40)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2818
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
Prosecution Insights