DETAILED ACTION
This Office Action is in response to the remarks entered on 08/10/2026. Claims 1-3, 5-15, 17-20 are amended. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 08/10/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent 11,556,765 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Arguments
The Applicant’s arguments regarding the rejection of above claims have been fully considered.
In reference to Applicant’s arguments about:
Allowable Subject Matter
Examiner’s response:
Claims 3-4, 7, 12, 15-16, and 19 were previously rejected only under Double Patenting, however, the Double Patenting rejections are withdrawn in view of the Terminal Disclaimer filed. Examiner respectfully suggests Applicant to rewrite these claims in independent form including all of the limitations of the base claim and any intervening claims; or amend independent claims to incorporate all the features from these dependent claims as being considered to have allowable subject matter.
In reference to Applicant’s arguments about:
Double Patenting.
Examiner’s response:
The Double Patenting rejections are withdrawn in view of the Terminal Disclaimer filed on 08/10/2026.
In reference to Applicant’s arguments about:
35 USC 112(f) Interpretation.
Examiner’s response:
Claim interpretation to invoke 112 (f) is withdrawn in view of claim amendments.
In reference to Applicant’s arguments about:
35 USC 103 Rejections.
Examiner’s response:
Applicant’s main arguments, as seen at page 13 in the response dated 08/10/2026, are directed to the amended limitations. Specifically, Applicant argues:
“As shown, while Chen discloses a memory mapping scheme that specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory, Chen fails to disclose generating a shift signal based on the memory mapping scheme and fails to disclose that the separate banks of the memory store the synapse weights based on a shift signal.
Accordingly, Chen fails to disclose, teach, or suggest "one or more processors configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address and configured to generate a shift signal based on the translation address; and a plurality of memories configured to store the plurality of synaptic weights based on the translation address and the shift signal," as recited in independent claim 1”.
These arguments have been fully considered, but are moot in view of new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5-6, 8-11, 13-14, 17-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US PG Pub. 2018/0189645 - hereinafter Chen) in view of Lee et al (NPL: “In Situ Training of CMOL CrossNets”- hereinafter Lee), and further in view of Cooper (US Patent No. 6,601,049- hereinafter Cooper).
Referring to Claim 1, Chen teaches a system for processing neural network, the system comprising:
one or more processors configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address (see Chen at [0003]: “FIG. 1 illustrates a block diagram for an example computing system including a multicore processor that may implement a neural network in accordance with certain embodiments”. Further, at [0044]: “each link between two neurons has a synaptic weight indicating the strength of the relationship between the two neurons. The synapse weights are depicted as WXY, where X indicates the pre-synaptic neuron and Y indicates the post-synaptic neuron”. Further, at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights); and
a plurality of memories configured to store the plurality of synaptic weights based on the translation address (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the storage of the synaptic weights),
wherein the translation address is generated such that at least two of the plurality of synaptic weights corresponding to a same one of the postsynaptic neurons are stored in different memories of the plurality of memories (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights is interpreted as storing the weights in different synapse memories of the plurality of memories).
However, Chen fails to explicitly teach:
“configured to generate a shift signal based on the translation address”; and
“synaptic weights corresponding to a same one of the postsynaptic neurons”.
Lee teaches, in an analogous system,
configured to generate a shift signal based on the translation address (see Lee at p. 2751 left column first paragraph: “Fig.2 shows our idea of our first method, the stochastic multiplication of analog signals.1 It uses the dual-rail presentation for both pre-synaptic (V1) and post-synaptic (V2) signals. Each synapse consists of four groups (arrays) of n×n similar elementary latching switches”. Further, p. 2751, right column: “The alternating global shift signal S(t) = ±S0, together with flipping the signs of signals x1,2, performs time division multiplexing”, and “A global shift signal S(t) = ±S0, with an amplitude S0 somewhat below Vth/2, and the sign alternating in accordance with Table I, is added to the output voltages”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Lee by translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons, and storing weights in different synapse memories, as taught by Chen, and further generating a shift signal, as taught by Lee. The modification would have been obvious because one of ordinary skill in the art would be motivated to perform time division multiplexing, ensuring that the net voltage may exceed Vth, and hence cause switching with a finite rate, only in one group of synapses (as suggested by Lee at p. 2751).
Cooper teaches, in an analogous system, synaptic weights corresponding to a same one of the postsynaptic neurons (see Cooper at Col. 8: line 65- Col. 9: line 1: “Applying the Cohen-Grossberg theorem to the self-adjusting layer architecture, we note immediately that pre- and post-synaptic weights are identical, and thus, use symmetric weights between nodes”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Chen and Lee with the above teachings of Cooper by translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons, storing weights in different synapse memories, and further generating a shift signal, as taught by Chen and Lee, while having the synaptic weights corresponding to a same one of the postsynaptic neurons, as taught by Cooper. The modification would have been obvious because one of ordinary skill in the art would be motivated to store symmetric weights in separate banks of the memory to enable parallel access, thus speeding up the operation of the neural network (as suggested by Cooper at Cooper at Col. 8: line 65- Col. 9: “use symmetric weights between nodes” and Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel. Thus, the fan-out synapses for any particular neuron of layer V may be accessed in parallel, thus speeding up operation of the neural network”).
Referring to Claim 2, the combination of Chen, Lee and Cooper teaches the system of claim 1, wherein the one or more processors are further configured to:
transfer each of the synaptic weights to a memory corresponding to a memory address of the translation address from among the plurality of memories (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”); and
transfer a block address of the translation address to the memory corresponding to the memory address (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”), and
wherein the memory corresponding to the memory address stores the transferred synaptic weight in a memory block that the block address indicates (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 5, the combination of Chen, Lee and Cooper teaches the system of claim 1, wherein the one or more processors are configured to transfer a block address of the translation address to a memory corresponding to a memory address of the translation address from among the plurality of memories, and wherein the memory corresponding to the memory address is configured to output a synaptic weight from a memory block that the block address indicates (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 6, the combination of Chen, Lee and Cooper teaches the system of claim 5, wherein the one or more processors are configured to transfer identical block addresses to the plurality of memories, and wherein the plurality of memories are configured to output synaptic weights corresponding to a specific postsynaptic neuron of the postsynaptic neurons in response to the identical block addresses (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 8, the combination of Chen, Lee and Cooper teaches the system of claim 1, wherein the one or more processors are configured to update the synaptic weights based on a spike of the presynaptic neurons or the postsynaptic neurons, and wherein the plurality of memories are configured to store the updated synaptic weights based on a translation address corresponding to each of the updated synaptic weights (see Chen at [0044]: “For example, a spike that propagates from X1 to X5 may increase or decrease the membrane potential of X5 depending on the value of W15. In various embodiments, the connections may be directed or undirected”. Therefore, this increase or decrease based on the spike is interpreted as the update of the synaptic weights).
Referring to Claim 9, Chen teaches a system for processing neural network, the system comprising:
one or more processors configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address and read each of the plurality of synaptic weights using the translation address (see Chen at [0044]: “each link between two neurons has a synaptic weight indicating the strength of the relationship between the two neurons. The synapse weights are depicted as WXY, where X indicates the pre-synaptic neuron and Y indicates the post-synaptic neuron”. Further, at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel”. Further at [0112]: “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights, and reading them simultaneously is interpreted as reading them using the address); and
a plurality of memories configured to store the plurality of synaptic weights (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the storage of the synaptic weights),
wherein the one or more processors are further configured to read at least two of the plurality of synaptic weights corresponding to a same one of the postsynaptic neurons from different memories of the plurality of memories and reorder the at least two of the plurality of synaptic weights (see Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel”. Further at [0025]: “However, threads 101a and 101b are potentially capable of out-of-order execution, where allocator and renamer block 130 also reserves other resources, such as reorder buffers to track instruction results”. Further at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights, and reading them simultaneously is interpreted as reading them using the address).
However, Chen fails to explicitly teach:
“configured to generate a shift signal based on the translation address”; and
“synaptic weights corresponding to a same one of the postsynaptic neurons”.
Lee teaches, in an analogous system,
configured to generate a shift signal based on the translation address (see Lee at p. 2751 left column first paragraph: “Fig.2 shows our idea of our first method, the stochastic multiplication of analog signals.1 It uses the dual-rail presentation for both pre-synaptic (V1) and post-synaptic (V2) signals. Each synapse consists of four groups (arrays) of n×n similar elementary latching switches”. Further, p. 2751, right column: “The alternating global shift signal S(t) = ±S0, together with flipping the signs of signals x1,2, performs time division multiplexing”, and “A global shift signal S(t) = ±S0, with an amplitude S0 somewhat below Vth/2, and the sign alternating in accordance with Table I, is added to the output voltages”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Lee by translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons, and storing weights in different synapse memories, as taught by Chen, and further generating a shift signal, as taught by Lee. The modification would have been obvious because one of ordinary skill in the art would be motivated to perform time division multiplexing, ensuring that the net voltage may exceed Vth, and hence cause switching with a finite rate, only in one group of synapses (as suggested by Lee at p. 2751).
Cooper teaches, in an analogous system, synaptic weights corresponding to a same one of the postsynaptic neurons (see Cooper at Col. 8: line 65- Col. 9: line 1: “Applying the Cohen-Grossberg theorem to the self-adjusting layer architecture, we note immediately that pre- and post-synaptic weights are identical, and thus, use symmetric weights between nodes”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Chen and Lee with the above teachings of Cooper by translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons, storing weights in different synapse memories, and further generating a shift signal, as taught by Chen and Lee, while having the synaptic weights corresponding to a same one of the postsynaptic neurons, as taught by Cooper. The modification would have been obvious because one of ordinary skill in the art would be motivated to store symmetric weights in separate banks of the memory to enable parallel access, thus speeding up the operation of the neural network (as suggested by Cooper at Cooper at Col. 8: line 65- Col. 9: “use symmetric weights between nodes” and Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel. Thus, the fan-out synapses for any particular neuron of layer V may be accessed in parallel, thus speeding up operation of the neural network”).
Referring to Claim 10, the combination of Chen, Lee and Cooper teaches the system of claim 9, wherein the one or more processors are configured to: receive a read command for the synaptic weights and the address corresponding to each of the synaptic weights; and output the synaptic weights from the plurality of memories based on the translation address corresponding to the address in response to the read command (see Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel”. Further at [0112]: “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights, and reading them simultaneously is interpreted as reading them using the address).
Referring to Claim 11, the combination of Chen, Lee and Cooper teaches the system of claim 10, wherein the one or more processors are configured to: obtain the translation address corresponding to the address; and provide a block address of the translation address to a memory corresponding to a memory address of the translation address from among the plurality of memories, and wherein the memory corresponding to the memory address is configured to output a synaptic weight corresponding to the block address (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 13, Chen teaches a system for processing neural network, the system comprising:
one or more processors configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address (see Chen at [0044]: “each link between two neurons has a synaptic weight indicating the strength of the relationship between the two neurons. The synapse weights are depicted as WXY, where X indicates the pre-synaptic neuron and Y indicates the post-synaptic neuron”. Further, at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights); and
a plurality of memories configured to store the plurality of synaptic weights based on the translation address (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the storage of the synaptic weights),
wherein the translation address is generated such that at least two of the plurality of synaptic weights corresponding to a same one of the presynaptic neurons are stored in different memories of the plurality of memories (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights is interpreted as storing the weights in different synapse memories of the plurality of memories).
However, Chen fails to explicitly teach:
“configured to generate a shift signal based on the translation address”; and
“synaptic weights corresponding to a same one of the postsynaptic neurons”.
Lee teaches, in an analogous system,
configured to generate a shift signal based on the translation address (see Lee at p. 2751 left column first paragraph: “Fig.2 shows our idea of our first method, the stochastic multiplication of analog signals.1 It uses the dual-rail presentation for both pre-synaptic (V1) and post-synaptic (V2) signals. Each synapse consists of four groups (arrays) of n×n similar elementary latching switches”. Further, p. 2751, right column: “The alternating global shift signal S(t) = ±S0, together with flipping the signs of signals x1,2, performs time division multiplexing”, and “A global shift signal S(t) = ±S0, with an amplitude S0 somewhat below Vth/2, and the sign alternating in accordance with Table I, is added to the output voltages”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Lee by translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons, and storing weights in different synapse memories, as taught by Chen, and further generating a shift signal, as taught by Lee. The modification would have been obvious because one of ordinary skill in the art would be motivated to perform time division multiplexing, ensuring that the net voltage may exceed Vth, and hence cause switching with a finite rate, only in one group of synapses (as suggested by Lee at p. 2751).
Cooper teaches, in an analogous system, synaptic weights corresponding to a same one of the postsynaptic neurons (see Cooper at Col. 8: line 65- Col. 9: line 1: “Applying the Cohen-Grossberg theorem to the self-adjusting layer architecture, we note immediately that pre- and post-synaptic weights are identical, and thus, use symmetric weights between nodes”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Chen and Lee with the above teachings of Cooper by translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons, and storing weights in different synapse memories, as taught by Chen, while having the synaptic weights corresponding to a same one of the postsynaptic neurons, as taught by Cooper. The modification would have been obvious because one of ordinary skill in the art would be motivated to store symmetric weights in separate banks of the memory to enable parallel access, thus speeding up the operation of the neural network (as suggested by Cooper at Cooper at Col. 8: line 65- Col. 9: “use symmetric weights between nodes” and Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel. Thus, the fan-out synapses for any particular neuron of layer V may be accessed in parallel, thus speeding up operation of the neural network”).
Referring to Claim 14, the combination of Chen, Lee and Cooper teaches the system of claim 13, wherein the one or more processors are further configured to:
transfer each of the synaptic weights to a memory corresponding to a memory address of the translation address from among the plurality of memories (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”); and
transfer a block address of the translation address to the memory corresponding to the memory address (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”), and
wherein the memory corresponding to the memory address stores the transferred synaptic weight in a memory block that the block address indicates (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 17, the combination of Chen, Lee and Cooper teaches the system of claim 13, wherein the one or more processors are configured to transfer a block address of the translation address to a memory corresponding to a memory address of the translation address from among the plurality of memories, and wherein the memory corresponding to the memory address is configured to output a synaptic weight from a memory block that the block address indicates (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 18, the combination of Chen, Lee and Cooper teaches the system of claim 17, wherein the one or more processors are configured to transfer different block addresses with respect to the plurality of synapse memories, and wherein the plurality of memories are configured to output synaptic weights corresponding to a specific presynaptic neuron of the presynaptic neurons in response to the different block addresses (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 20, the combination of Chen, Lee and Cooper teaches the system of claim 13, wherein the one or more processors are configured to update the synaptic weights based on a spike of the presynaptic neurons or the postsynaptic neurons, wherein the plurality of memories are configured to store the updated synaptic weights based on a translation address corresponding to each of the updated synaptic weights (see Chen at [0044]: “For example, a spike that propagates from X1 to X5 may increase or decrease the membrane potential of X5 depending on the value of W15. In various embodiments, the connections may be directed or undirected”. Therefore, this increase or decrease based on the spike is interpreted as the update of the synaptic weights).
Allowable Subject Matter
Claims 3-4, 7, 12, 15-16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUIS A SITIRICHE whose telephone number is (571)270-1316. The examiner can normally be reached M-F 9am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Yi can be reached at (571) 270-7519. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LUIS A SITIRICHE/ Primary Examiner, Art Unit 2126
Prosecution Insights