DETAILED ACTION
This Office Action is in response to the Preliminary Amendment entered on 03/22/2023. Claims 1-2 are amended. Claims 3-20 are new claims added. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 04/27/2023 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language (foreign references listed in the Foreign Patent Documents table). It has been placed in the application file, but the information referred to therein has not been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9, 11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9, 17-18 of U.S. Patent 11,556,765. Further, Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent 11,556,765 in view of Chen et al (20180189645 - hereinafter Chen); as explained in the table below.
Instant Application
U.S. Patent 11,556,765.
Claim 1
A system for processing neural network, the system comprising:
an address translation device configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address; and
a plurality of synapse memories configured to store the plurality of synaptic weights based on the translation address,
wherein the translation address is generated such that at least two of the plurality of synaptic weights corresponding to a same one of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories.
Claim 1
A neuromorphic system comprising:
an address translation device configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address; and
a plurality of synapse memories configured to store the plurality of synaptic weights based on the translation address,
wherein the translation address is generated such that at least two of the plurality of synaptic weights corresponding to a same one of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of the plurality of synaptic weights corresponding to a same one of the presynaptic neurons are stored in different synapse memories.
Claim 2
Claim 2
Claim 3
Claim 3
Claim 4
Claim 4
Claim 5
Claim 5
Claim 6
Claim 6
Claim 7
Claim 8
Claim 8
Claim 9
Claim 9
Claim 17
Claim 10
Claim 17
The Patent cited above fails to teach the limitation at this claim, however, Chen teaches them at the [0059].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Kim with the above combination of Chen in order to simultaneously read as each data is in parallel (as suggested by Chen at 0059).
Claim 11
Claim 18
Claim 12
Claim 17
Claim 13
Claim 1
Claim 14
Claim 2
Claim 15
Claim 3
Claim 16
Claim 4
Claim 17
Claim 5
Claim 18
Claim 7
Claim 19
Claim 8
Claim 20
Claim 9
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“an address translation device” in claims 1-7, 9-15 and 17-19;
“synapse memories” in claims 1-2, 5-6, 8-11, 13-14, 17-18 and 20;
“a processing device” in claims 8, 20.
Because these claim limitation(s) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation:
Paragraph [0041] recites: “Components in the detailed description may be implemented in the form of software, hardware, or a combination thereof. In an embodiment, the software may be a machine code, firmware, an embedded code, and application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a microelectromechanical system (MEMS), a passive element, or a combination thereof”. Therefore, the corresponding structures of the placeholders “address translation device” and “processing device” recited in the claims are interpreted to be an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a microelectromechanical system (MEMS), a passive element, or a combination thereof.
Paragraph [0058] recites: “Each of the plurality of synapse memories 200 may be implemented with one of a volatile memory device, such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), and a nonvolatile memory device, such as a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), or a flash memory”. Therefore, the corresponding structure of the placeholder “synapse memories” recited in the claims is interpreted to be one of a volatile memory device, such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), and a nonvolatile memory device, such as a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), or a flash memory.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5-6, 8-11, 13-14, 17-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US PG Pub. 2018/0189645 - hereinafter Chen) in view of Cooper (US Patent No. 6,601,049- hereinafter Cooper).
Referring to Claim 1, Chen teaches a system for processing neural network, the system comprising:
an address translation device configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address (see Chen at [0044]: “each link between two neurons has a synaptic weight indicating the strength of the relationship between the two neurons. The synapse weights are depicted as WXY, where X indicates the pre-synaptic neuron and Y indicates the post-synaptic neuron”. Further, at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights); and
a plurality of synapse memories configured to store the plurality of synaptic weights based on the translation address (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the storage of the synaptic weights),
wherein the translation address is generated such that at least two of the plurality of synaptic weights corresponding to a same one of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights is interpreted as storing the weights in different synapse memories of the plurality of memories).
However, Chen fails to explicitly teach synaptic weights corresponding to a same one of the postsynaptic neurons.
Cooper teaches, in an analogous system, synaptic weights corresponding to a same one of the postsynaptic neurons (see Cooper at Col. 8: line 65- Col. 9: line 1: “Applying the Cohen-Grossberg theorem to the self-adjusting layer architecture, we note immediately that pre- and post-synaptic weights are identical, and thus, use symmetric weights between nodes”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Agrawal by storing weights in different synapse memories, as taught by Chen, while having the synaptic weights corresponding to a same one of the postsynaptic neurons, as taught by Cooper. The modification would have been obvious because one of ordinary skill in the art would be motivated to store symmetric weights in separate banks of the memory to enable parallel access, thus speeding up the operation of the neural network (as suggested by Cooper at Cooper at Col. 8: line 65- Col. 9: “use symmetric weights between nodes” and Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel. Thus, the fan-out synapses for any particular neuron of layer V may be accessed in parallel, thus speeding up operation of the neural network”).
Referring to Claim 2, the combination of Chen and Cooper teaches the system of claim 1, wherein the address translation device is further configured to:
transfer each of the synaptic weights to a synapse memory corresponding to a memory address of the translation address from among the plurality of synapse memories (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”); and
transfer a block address of the translation address to the synapse memory corresponding to the memory address (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”), and
wherein the synapse memory corresponding to the memory address stores the transferred synaptic weight in a memory block that the block address indicates (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 5, the combination of Chen and Cooper teaches the system of claim 1, wherein the address translation device is configured to transfer a block address of the translation address to a synapse memory corresponding to a memory address of the translation address from among the plurality of synapse memories, and wherein the synapse memory corresponding to the memory address is configured to output a synaptic weight from a memory block that the block address indicates (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 6, the combination of Chen and Cooper teaches the system of claim 5, wherein the address translation device is configured to transfer identical block addresses to the plurality of synapse memories, and wherein the plurality of synapse memories are configured to output synaptic weights corresponding to a specific postsynaptic neuron of the postsynaptic neurons in response to the identical block addresses (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 8, the combination of Chen and Cooper teaches the system of claim 1, further comprising: a processing device configured to update the synaptic weights based on a spike of the presynaptic neurons or the postsynaptic neurons, wherein the plurality of synapse memories are configured to store the updated synaptic weights based on a translation address corresponding to each of the updated synaptic weights (see Chen at [0044]: “For example, a spike that propagates from X1 to X5 may increase or decrease the membrane potential of X5 depending on the value of W15. In various embodiments, the connections may be directed or undirected”. Therefore, this increase or decrease based on the spike is interpreted as the update of the synaptic weights).
Referring to Claim 9, Chen teaches a system for processing neural network, the system comprising:
an address translation device configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address and read each of the plurality of synaptic weights using the translation address (see Chen at [0044]: “each link between two neurons has a synaptic weight indicating the strength of the relationship between the two neurons. The synapse weights are depicted as WXY, where X indicates the pre-synaptic neuron and Y indicates the post-synaptic neuron”. Further, at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel”. Further at [0112]: “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights, and reading them simultaneously is interpreted as reading them using the address); and
a plurality of synapse memories configured to store the plurality of synaptic weights (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the storage of the synaptic weights),
wherein the address translation device is further configured to read at least two of the plurality of synaptic weights corresponding to a same one of the postsynaptic neurons from different synapse memories of the plurality of synapse memories and reorder the at least two of the plurality of synaptic weights (see Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel”. Further at [0025]: “However, threads 101a and 101b are potentially capable of out-of-order execution, where allocator and renamer block 130 also reserves other resources, such as reorder buffers to track instruction results”. Further at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights, and reading them simultaneously is interpreted as reading them using the address).
However, Chen fails to explicitly teach synaptic weights corresponding to a same one of the postsynaptic neurons.
Cooper teaches, in an analogous system, synaptic weights corresponding to a same one of the postsynaptic neurons (see Cooper at Col. 8: line 65- Col. 9: line 1: “Applying the Cohen-Grossberg theorem to the self-adjusting layer architecture, we note immediately that pre- and post-synaptic weights are identical, and thus, use symmetric weights between nodes”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Agrawal by storing weights in different synapse memories, as taught by Chen, while having the synaptic weights corresponding to a same one of the postsynaptic neurons, as taught by Cooper. The modification would have been obvious because one of ordinary skill in the art would be motivated to store symmetric weights in separate banks of the memory to enable parallel access, thus speeding up the operation of the neural network (as suggested by Cooper at Cooper at Col. 8: line 65- Col. 9: “use symmetric weights between nodes” and Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel. Thus, the fan-out synapses for any particular neuron of layer V may be accessed in parallel, thus speeding up operation of the neural network”).
Referring to Claim 10, the combination of Chen and Cooper teaches the system of claim 9, wherein the address translation device is configured to: receive a read command for the synaptic weights and the address corresponding to each of the synaptic weights; and output the synaptic weights from the plurality of synapse memories based on the translation address corresponding to the address in response to the read command (see Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel”. Further at [0112]: “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights, and reading them simultaneously is interpreted as reading them using the address).
Referring to Claim 11, the combination of Chen and Cooper teaches the system of claim 10, wherein the address translation device is configured to: obtain the translation address corresponding to the address; and provide a block address of the translation address to a synapse memory corresponding to a memory address of the translation address from among the plurality of synapse memories, and wherein the synapse memory corresponding to the memory address is configured to output a synaptic weight corresponding to the block address (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”)..
Referring to Claim 13, Chen teaches a system for processing neural network, the system comprising:
an address translation device configured to translate an address corresponding to each of a plurality of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address (see Chen at [0044]: “each link between two neurons has a synaptic weight indicating the strength of the relationship between the two neurons. The synapse weights are depicted as WXY, where X indicates the pre-synaptic neuron and Y indicates the post-synaptic neuron”. Further, at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the claimed translation of address corresponding to each of a plurality of synaptic weights); and
a plurality of synapse memories configured to store the plurality of synaptic weights based on the translation address (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this memory mapping scheme to specify the storage of synaptic weights based on memory address is interpreted as the storage of the synaptic weights),
wherein the translation address is generated such that at least two of the plurality of synaptic weights corresponding to a same one of the presynaptic neurons are stored in different synapse memories of the plurality of synapse memories (see Chen at [0112]: “In an embodiment, the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron” and “In an embodiment, the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron”. Therefore, this storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights is interpreted as storing the weights in different synapse memories of the plurality of memories).
However, Chen fails to explicitly teach synaptic weights corresponding to a same one of the presynaptic neurons.
Cooper teaches, in an analogous system, synaptic weights corresponding to a same one of the presynaptic neurons (see Cooper at Col. 8: line 65- Col. 9: line 1: “Applying the Cohen-Grossberg theorem to the self-adjusting layer architecture, we note immediately that pre- and post-synaptic weights are identical, and thus, use symmetric weights between nodes”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Agrawal by storing weights in different synapse memories, as taught by Chen, while having the synaptic weights corresponding to a same one of the presynaptic neurons, as taught by Cooper. The modification would have been obvious because one of ordinary skill in the art would be motivated to store symmetric weights in separate banks of the memory to enable parallel access, thus speeding up the operation of the neural network (as suggested by Cooper at Cooper at Col. 8: line 65- Col. 9: “use symmetric weights between nodes” and Chen at [0059]: “Because each bank is independently accessible, each bank may be read simultaneously and thus an output from each bank may be obtained in parallel. Thus, the fan-out synapses for any particular neuron of layer V may be accessed in parallel, thus speeding up operation of the neural network”).
Referring to Claim 14, the combination of Chen and Cooper teaches the system of claim 13, wherein the address translation device is further configured to:
transfer each of the synaptic weights to a synapse memory corresponding to a memory address of the translation address from among the plurality of synapse memories (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”); and
transfer a block address of the translation address to the synapse memory corresponding to the memory address (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”), and
wherein the synapse memory corresponding to the memory address stores the transferred synaptic weight in a memory block that the block address indicates (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 17, the combination of Chen and Cooper teaches the system of claim 13, wherein the address translation device is configured to transfer a block address of the translation address to a synapse memory corresponding to a memory address of the translation address from among the plurality of synapse memories, and wherein the synapse memory corresponding to the memory address is configured to output a synaptic weight from a memory block that the block address indicates (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 18, the combination of Chen and Cooper teaches the system of claim 17, wherein the address translation device is configured to transfer different block addresses with respect to the plurality of synapse memories, and wherein the plurality of synapse memories are configured to output synaptic weights corresponding to a specific presynaptic neuron of the presynaptic neurons in response to the different block addresses (see Chen at [0086]: “memory mapping of synapse weights of the neuromorphic processor is configured based on the selected synapse memory mapping scheme. The configuration may include determining the locations of synapses of the neural network (e.g., determining which neurons are connected via synapses) and the locations in memory in which the weights of the synapses are to be stored”).
Referring to Claim 20, the combination of Chen and Cooper teaches the system of claim 13, further comprising: a processing device configured to update the synaptic weights based on a spike of the presynaptic neurons or the postsynaptic neurons, wherein the plurality of synapse memories are configured to store the updated synaptic weights based on a translation address corresponding to each of the updated synaptic weights (see Chen at [0044]: “For example, a spike that propagates from X1 to X5 may increase or decrease the membrane potential of X5 depending on the value of W15. In various embodiments, the connections may be directed or undirected”. Therefore, this increase or decrease based on the spike is interpreted as the update of the synaptic weights).
Allowable Subject Matter
For claims 3-4, 7, 12, 15-16, and 19, no art rejection is made for these claims, they are only rejected under Double Patenting as explained above in this office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Dong et al, NPL “Network on Chip Architecture for BP Neural Network” (this art is pertinent as it is directed to hardware neural networks and the architecture of neurons in a chip).
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/LUIS A SITIRICHE/ Primary Examiner, Art Unit 2126
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