Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8, 9, 15, 16, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al “TQSim: A Case for Reuse-Focused Tree-Based Quantum Circuit Simulation”, arXiv:2203.13892v1, published 3/25/2022, cited in the IDS filed on 12/15/2022.
Regarding claim 1, Wang teaches a method for reducing a number of shots required to perform a noisy circuit simulation, the method comprising” (Wang Page 7 C. (1) Number of Shot number of shots reduced to 1000 and 3200 respectively to amplify the effect of noise):
applying a noise model to each shot of a plurality of shots of a quantum circuit which randomly selects a gate operation to be performed in simulating said quantum circuit (Wang Abstract, Pg2-B, Pg7-C2 noise models may be applied for simulations, “simulating quantum programs on classical computers with different noise models is a de-facto tool that is used by researchers and practitioners. Unfortunately, noisy quantum simulators iteratively execute the same circuit across multiple trials (shots)”, “Quantum algorithms are expressed as circuits. A circuit is a list of quantum gates that need to be applied, in order, to modify the initial quantum state. Similarly, a quantum subcircuit is a consecutive sub-list of the original list of gate operations in the circuit. The five commonly used gates are, X, Y, Z, Hadamard (H), and CNOT.”)
identifying a subset of said plurality of shots with a selection of a same gate operation (Wang Pg11-Conclusion, Pg1 RtCol Para1 LeftCol 1st 2 Para, multiple shots that apply same subcircuit (gate(s)) are identified); and
performing a single simulation of said quantum circuit for said identified subset of said plurality of shots using said same gate operation (Wang Pg1 RtCol Para1 LeftCol 1st 2 Para, “Previous optimization techniques for quantum circuit simulation [16], [42], [44], [48] and parallelization methods, i.e. multiprocessing and GPU simulation, focus on improving the performance of the single-shot simulation process.”, “ reuses the intermediate states across multiple simulation shots”, Wang Page 11, Col 1, 2nd last Paragraph “Prior works on simulation methods primarily focus on ideal quantum circuits that sample from a single probability distribution [16], [40], [42], [48]. TQSim can be combined with techniques proposed to improve single-shot simulation time to achieve an even better simulation result.”)
Regarding claim 2, Wang teaches the invention as claimed in claim 1 above.
Wang further teaches wherein a plurality of subsets of said plurality of shots are identified, wherein each of said plurality of subsets of said plurality of shots utilizes a different gate operation selected by said noise model (Wang Fig. 2 Pg1 RtCol Para1 LeftCol 1st 2 Para, Pg4 III B, Fig. 8, shots for circuit are identified, shots starting from same subcircuit (gate) are grouped together).
Claim 8 is directed towards a product comprising instructions similar in scope to the instructions performed by the method of claim 1, and is rejected under the same rationale. Wang further teaches a computer program product for reducing a number of shots required to perform a noisy circuit simulation, the computer program product comprising one or more computer readable storage mediums having program code embodied therewith, the program code comprising programming instructions (Wang Pg 7, D. System Configuration).
Claim(s) 9 is/are dependent on claim 8 above, is/are directed towards a product comprising instructions similar in scope to the instructions performed by the method of claim(s) 2 respectively, and is/are rejected under the same rationale.
Claim 15 is directed towards a system executing instructions similar in scope to the instructions performed by the method of claim 1 and is rejected under the same rationale. Wang further teaches system, comprising: a memory for storing a computer program for reducing a number of shots required to perform a noisy circuit simulation; and a processor connected to said memory, wherein said processor is configured to execute program instructions of the computer program comprising (Wang Pg 7, D. System Configuration).
Claim(s) 16 is/are dependent on claim 15 above, is/are directed towards a system executing instructions similar in scope to the instructions performed by the method of claim(s) 2 respectively, and is/are rejected under the same rationale.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-7, 10-14, 17-20, are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, in view of Pednault (US 20190095561 A1).
Regarding claim 3, Wang teaches the invention as claimed in claim 1 above.
Wang does not specifically teach measuring quantum states of qubits of said simulated quantum circuit for said identified subset of said plurality of shots after performing said single simulation; and updating a statevector with said measured quantum states of qubits of said simulated quantum circuit
However Pednault teaches measuring quantum states of qubits of said simulated quantum circuit for said identified subset of said plurality of shots after performing said single simulation; and updating a statevector with said measured quantum states of qubits of said simulated quantum circuit (Pednault [32, 42, 64] tensor is k-dimensional vector, using vectors for states allows representation in k-dimensional space, subcircuits represent shared gates, Pednault [64, 86, 87] state vectors (tensors) are initialized and as subcircuits are simulated the corresponding qubits are measured and corresponding state vectors (tensors) are updated, downstream subcircuits are simulated in order).
It would have been obvious to one of an ordinary skill in the art before the effective filing date of the claimed invention, to have incorporated the concept taught by Pednault of measuring quantum states of qubits of said simulated quantum circuit for said identified subset of said plurality of shots after performing said single simulation; and updating a statevector with said measured quantum states of qubits of said simulated quantum circuit, into the invention suggested by Wang; since both inventions are directed towards executing subcircuits based on quantum shot gate commonality, and incorporating the teaching of Pednault into the invention suggested by Wang would provide the added advantage of allowing representation (vectors) in k-dimensional space and updating the representation as simulation information becomes available, and the combination would perform with a reasonable expectation of success (Pednault [32, 42, 64, 86, 87]).
Regarding claim 4, Wang teaches the invention as claimed in claim 1 above.
Wang does not specifically teach initializing a statevector for said plurality of shots of said quantum circuit; and creating a new statevector for said identified subset of said plurality of shots.
However Pednault teaches initializing a statevector for said plurality of shots of said quantum circuit; and creating a new statevector for said identified subset of said plurality of shots (Pednault [32, 42, 64] tensor is k-dimensional vector, using vectors for states allows representation in k-dimensional space, subcircuits represent shared gates, Pednault [54, 61, 84, 86, 87] state vectors (tensors) are initialized as sub-circuits are being simulated, as each subsequent sub-circuit is simulated- a copy of existing state vector is created for the subcircuit (shared gates)).
It would have been obvious to one of an ordinary skill in the art before the effective filing date of the claimed invention, to have incorporated the concept taught by Pednault of initializing a statevector for said plurality of shots of said quantum circuit; and creating a new statevector for said identified subset of said plurality of shots, into the invention suggested by Wang; since both inventions are directed towards executing subcircuits based on quantum shot gate commonality, and incorporating the teaching of Pednault into the invention suggested by Wang would provide the added advantage of allowing representation (vectors) in k-dimensional space and generating and updating representation as and when needed by not creating state-vector for new subcircuits before they are simulated, and the combination would perform with a reasonable expectation of success (Pednault [32, 42, 64, 54, 61, 84, 86, 87).
Regarding claim 5, Wang and Pednault teach the invention as claimed in claim 4 above.
Wang does not specifically teach wherein said new statevector comprises a copy of said initialized statevector, wherein said new statevector comprises a listing of said identified subset of said plurality of shots
However Pednault teaches wherein said new statevector comprises a copy of said initialized statevector, wherein said new statevector comprises a listing of said identified subset of said plurality of shots (Pednault [54, 61, 78, 84, 86, 87] state vectors (tensors) are initialized as sub-circuits are being simulated, as each subsequent sub-circuit is simulated- a copy of existing state vector is created for the subcircuit (shared gates), list of subcircuit pointers may be present).
Regarding claim 6, Wang and Pednault teach the invention as claimed in claim 5 above.
Wang does not specifically teach measuring quantum states of qubits of said simulated quantum circuit for said identified subset of said plurality of shots after performing said single simulation; and updating said new statevector with said measured quantum states of qubits of said simulated quantum circuit
However Pednault teaches measuring quantum states of qubits of said simulated quantum circuit for said identified subset of said plurality of shots after performing said single simulation; and updating said new statevector with said measured quantum states of qubits of said simulated quantum circuit (Pednault [86, 87, 94-97] new state vector for subsequent subcircuit is initialized with existing state vector states and then updated with states of the subsequent subcircuit based on subcircuit simulation)
Regarding claim 7, Wang and Pednault teach the invention as claimed in claim 4 above.
Wang does not specifically teach storing a list of shots comprising said identified subset of said plurality of shots in an out of memory list in response to a lack of memory for storing said created new statevector
However Pednault teaches storing a list of shots comprising said identified subset of said plurality of shots in an out of memory list in response to a lack of memory for storing said created new statevector (Pednault [148] some subcircuit information may be stored in secondary storage due to insufficient memory, Pednault [54, 61, 78, 84, 86, 87] state vectors (tensors) are initialized as sub-circuits are being simulated, as each subsequent sub-circuit is simulated- a copy of existing state vector is created for the subcircuit (shared gates), list of subcircuit pointers may be present).
Claim(s) 10-14 is/are dependent on claim 8 above, is/are directed towards a product comprising instructions similar in scope to the instructions performed by the method of claim(s) 3-7 respectively, and is/are rejected under the same rationale.
Claim(s) 17-20 is/are dependent on claim 15 above, is/are directed towards a system executing instructions similar in scope to the instructions performed by the method of claim(s) 3-6 respectively, and is/are rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pednault (US 20190347575 A1) discloses simulating a quantum circuit in stages, one stage per sub-circuit, e.g., applying gates, to provide a simulated quantum state tensor for the quantum state circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANCHITA ROY whose telephone number is (571)272-5310. The examiner can normally be reached Monday-Friday 12-8.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Usmaan Saeed can be reached at (571) 272-4046. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
SANCHITA ROY
Primary Examiner
Art Unit 2146
/SANCHITA ROY/Primary Examiner, Art Unit 2146