Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/11/25 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-10, 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar, US Patent Application Publication 2021/0004233 (hereinafter Kumar) in view of Kumar, Grot et al., US Patent Application Publication 2020/0004543 (hereinafter Grot).
Regarding claim 1, Kumar teaches:
A processor, comprising: an instruction processing circuit configured to process an instruction stream comprising a plurality of instructions; an instruction cache memory (see e.g. fig. 1, L1 instruction cache/prefetch buffer); a prefetcher circuit (see e.g. fig. 1, block request multiplexer 150 initiates prefetch requests from cache); and a branch predictor circuit comprising a branch target buffer (BTB) and an instruction cache hit prediction circuit (see e.g. fig. 1, branch prediction unit with BTB and prediction circuit); the instruction cache hit prediction circuit configured to: detect that a first access by the branch predictor circuit to the BTB for a first instruction in the instruction stream results in a miss on the BTB (see e.g. para. [0068], [0116], a BTB miss occurs); and responsive to detecting that the first access by the branch predictor circuit to the BTB for the first instruction in the instruction stream results in the miss on the BTB: generate a first instruction cache prefetch request for the first instruction (see e.g. fig. 1, para. [0047], [0068], a BTB miss probe is generated to request a prefetch for the instruction); and transmit the first instruction cache prefetch request to the prefetcher circuit (see e.g. fig. 1, the BTB miss probe is transmitted to the block request multiplexer to trigger a prefetch from cache).
While Kumar teaches that data is accessed from other memory levels if not present in the L1 cache (see e.g. para. [0068]), Kumar fails to explicitly describe wherein the first instruction cache prefetch request comprises a request to prefetch the first instruction from a higher-level cache memory into the instruction cache memory.
Grot teaches filling both an L1 instruction cache and a BTB during BTB miss resolution due to a BTB miss (see e.g. para. [0056]), wherein the filling is from a higher-level cache memory (see e.g. fig. 1, para. [0024], the prefetch fills from the higher-level Last Level Cache).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Kumar and Grot such that the first instruction cache prefetch request comprises a request to prefetch the first instruction from a higher-level cache memory into the instruction cache memory. This would have ensured that the next block(s) of instructions were present in the instruction cache in order to continue program execution, and ensure that additional instructions in a block(s) could be accessed more quickly to reduce any further stalling.
Regarding claim 2, Kumar in view of Grot teaches or suggests:
The processor of claim 1, wherein: the processor further comprises a Level 2 (L2) cache memory (see e.g. fig. 1, lower cache LLC); and the instruction cache hit prediction circuit is configured to generate the first instruction cache prefetch request by being configured to generate a prefetch request to prefetch data from the L2 cache memory into the instruction cache memory (see e.g. para. [0068], accessed from lower levels if not present in the L1 cache).
Regarding claim 3, Kumar in view of Grot teaches or suggests:
The processor of claim 1, wherein: the BTB comprises a plurality of BTB levels (see e.g. para. [0068]); and the instruction cache hit prediction circuit is configured to detect that the first access by the branch predictor circuit to the BTB for the first instruction in the instruction stream results in the miss on the BTB by being configured to detect a miss on each BTB level of the plurality of BTB levels of the BTB (see e.g. para. [0068]).
Claims 8-10 are rejected for reasons corresponding to those given above for claims 1-3.
Claims 15-17 are rejected for reasons corresponding to those given above for claims 1-3.
Claims 4-6, 11-13, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Grot, further in view of Ono et al., US Patent Application Publication 2013/0246708 (hereinafter Ono).
Regarding claim 4, Kumar in view of Grot teaches or suggests:
The processor of claim 1, wherein: the processor comprises a plurality of BTB levels of the BTB (see e.g. para. [0068]) and the instruction cache hit prediction circuit is further configured to: detect that a second access by the branch predictor circuit to the BTB level for a second instruction in the instruction stream results in a miss on the instruction cache memory (see e.g. para. [0068], [0116], a BTB miss occurs).
Kumar in view of Grot fails to explicitly teach each BTB level of a plurality of BTB levels of the BTB is associated with an instruction cache hit counter and an instruction cache miss counter; and responsive to detecting that the second access by the branch predictor circuit to the BTB level for the second instruction in the instruction stream results in the miss on the instruction cache memory: determine a ratio of a value of the instruction cache hit counter for the BTB level to a value of the instruction cache miss counter for the BTB level; determine that the ratio exceeds a miss rate threshold; and responsive to determining that the ratio exceeds the miss rate threshold: generate a second instruction cache prefetch request for the second instruction; and transmit the second instruction cache prefetch request to the prefetcher circuit.
Ono teaches using cache hit and miss counters to determine whether a prefetch request should be sent (see e.g. para. [0041]) by determining a ratio of hits to misses, determining that the ratio exceeds a miss rate threshold, and responsive to determining that the ratio exceeds the miss rate threshold: generating and transmitting an instruction cache prefetch request for the instruction (see e.g. para. [0060-4]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Kumar, Grot, and Ono such that each BTB level of a plurality of BTB levels of the BTB is associated with an instruction cache hit counter and an instruction cache miss counter; and responsive to detecting that the second access by the branch predictor circuit to the BTB level for the second instruction in the instruction stream results in the miss on the instruction cache memory: determine a ratio of a value of the instruction cache hit counter for the BTB level to a value of the instruction cache miss counter for the BTB level; determine that the ratio exceeds a miss rate threshold; and responsive to determining that the ratio exceeds the miss rate threshold: generate a second instruction cache prefetch request for the second instruction; and transmit the second instruction cache prefetch request to the prefetcher circuit. This would have provided an advantage of improving the efficiency of prefetching by using past miss rates to filter prefetch requests to reduce power and bandwidth overhead while preserving performance (see Ono para. [0039]).
Regarding claim 5, Kumar in view of Grot and Ono teaches or suggests:
The processor of claim 4, wherein: the instruction cache hit prediction circuit is further configured to: detect that a third access by the branch predictor circuit to the BTB level for a third instruction in the instruction stream results in a hit on the instruction cache memory (see e.g. Kumar para. [0065]); and responsive to detecting that the third access by the branch predictor circuit to the BTB level for the third instruction in the instruction stream results in the hit on the instruction cache memory, increment the instruction cache hit counter for the BTB level (see e.g. Ono para. [0041], [0047-8]).
Regarding claim 6, Kumar in view of Grot and Ono teaches or suggests:
The processor of claim 4, wherein the instruction cache hit prediction circuit is further configured to, further responsive to detecting that the second access by the branch predictor circuit to the BTB level for the second instruction in the instruction stream results in the miss on the instruction cache memory, increment the instruction cache miss counter for the BTB level (see e.g. Ono para. [0047-8]).
Claims 11-13 are rejected for reasons corresponding to those given above for claims 4-6.
Claims 18-20 are rejected for reasons corresponding to those given above for claims 4-6.
Claims 7, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Grot and Ono, further in view of Agarwal et al., US Patent Application Publication 2019/0294546 (hereinafter Agarwal).
Regarding claim 7, Kumar in view of Grot and Ono teaches or suggests:
The processor of claim 4.
Kumar in view of Grot and Ono fails to explicitly teach wherein the instruction cache hit prediction circuit is further configured to reset the instruction cache hit counter and the instruction cache miss counter for the BTB level.
Agarwal teaches resetting a hit counter and miss counter used to track hits and misses to a cache (see e.g. para. [0003]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Kumar, Grot, Ono, and Agarwal such that the instruction cache hit prediction circuit is further configured to reset the instruction cache hit counter and the instruction cache miss counter for the BTB level. This would have provided an advantage of being able to clear the counters to remove unwanted history data such as for a new context or program to be executed.
Claim 14 is rejected for reasons corresponding to those given above for claim 7.
Response to Arguments
Applicant's arguments filed 7/11/25 have been fully considered but they are not persuasive.
Applicant argues a lack of teaching of prefetching the first instruction from a higher-level cache memory into an instruction cache memory of the processor responsive to detecting that the first access by the branch predictor circuit to the BTB for the first instruction in the instruction stream results in the miss on the BTB.
Examiner respectfully disagrees. Grot teaches filling both an L1 instruction cache and a BTB during BTB miss resolution due to a BTB miss (see e.g. para. [0056]), wherein the filling is from a higher-level cache memory (see e.g. fig. 1, para. [0024], the prefetch fills from the higher-level Last Level Cache).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Kumar and Grot such that the first instruction cache prefetch request comprises a request to prefetch the first instruction from a higher-level cache memory into the instruction cache memory. This would have ensured that the next block(s) of instructions were present in the instruction cache in order to continue program execution, and ensure that additional instructions in a block(s) could be accessed more quickly to reduce any further stalling.
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183