DETAILED ACTION
The instant application having Application No. 18/083,273 filed on 12/16/2022 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-2, 4-10 and 12-20 are rejected under 35 U.S.C. 112(b) as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01.
As per Claims 1 and 9, the claims recite converting a set of non-zero floating point numbers into a block floating point format value, and generating an encoded sparse block floating point format value. However, as claimed, these two steps are disparate and unconnected, unrelated to one another, which amounts to a gap between the elements. The specification makes clear that generating the encoded sparse block floating point format value is based on the converted block floating point format value, i.e. the previous step (see e.g. Paragraph 0047 of the instant specification). In other words, the BFP result of the “converting” step is used in the subsequent “generating” step. By claiming the steps as unconnected in any way, the claims in question are incomplete for omitting essential elements, such omission amounting to a gap between the elements that fails to particularly point out and distinctly claim the invention.
For examination purposes, the Examiner interprets the claims as reading “generating an encoded sparse block floating point format value based on the block floating point format value.”
As per Claim 16, it recites (1) memory configured to store floating point numbers, (2) converting an encoded block floating point format value to a set of non-zero floating point numbers, and (3) generating a non-sparse set of floating point values. However, as claimed, each element (1), (2) and (3) is unconnected in any way to any other element, which amounts to a gap between the elements. For example, an encoded block floating point format value is converted to a set of non-zero floating point numbers, and separately a non-sparse set of floating point values is generated, and separate from the set of non-zero floating point numbers and the non-sparse set of floating point values, a memory stores floating point numbers. By failing to interrelate any of the claimed elements, the claim is incomplete for omitting essential elements, such omission amounting to a gap between the elements that fails to particularly point out and distinctly claim the invention.
As per dependent Claims 2, 4-8, 10, 12-15 and 17-20, they are rejected for the reasons presented above, due to their dependency upon their respective rejected base claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3 and 5-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per Claim 1, it recites encoding floating point numbers, comprising identifying numbers which represent zero and non-zero values, converting the numbers to a block floating point format value, and generating an encoded sparse block floating point value.
Under Prong One of Step 2A of the USPTO current eligibility guidance (see MPEP § 2106), such limitations cover mathematical calculations, relationships, and/or formulas. See e.g. Figures 3-4 and Paragraphs 0039 and 0045-0046 of the instant specification, which describes identifying and converting the numbers as comprising mathematical comparisons and sorting and shifting numbers. Moreover, converting from one numerical format to another numerical format is necessarily an expression of mathematical relationships. Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a “processing device” comprising “circuitry” configured to perform the numerical format conversion and “memory” configured to store data. However, these elements are recited at a high-level of generality (i.e. as generic computer components performing generic computer function(s) such as mathematical computations and storing data). For example, the “memory” merely operates to generically store and provide data for use in the claimed abstract idea, and the claim fails to recite structural or functional limitations that would make the memory any more particular than a generic computer memory. Moreover, since the claim fails to include any detail(s) as to the structure of the claimed “processing device” or “circuitry”, or how they particularly function to perform the recited calculations or functions, these additional limitations fail to provide a meaningful limitation on the claimed steps, and amount to no more than mere instructions to apply the exception using generic computer components. Accordingly, the abstract idea is not integrated into a practical application because the additional element(s) do not impose any meaningful limits on practicing the abstract idea, i.e. the claim is directed to an abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, using a generic processor or generic computer component(s) to perform the claimed mathematical steps amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. See MPEP § 2106.05(f). Furthermore, storing and retrieving data in a memory is well-understood, routine, conventional activity that fails to qualify as significantly more than the judicial exception. See MPEP 2106.05(d)(II), “storing and retrieving information in memory”. Accordingly, Claim 1 is not patent-eligible under 35 U.S.C. 101.
As per Claims 2-3 and 5-8, they are rejected under 35 U.S.C. 101 as non-statutory for at least the reasons stated above. The claims are dependent on Claim 1, but fail to include any additional elements sufficient to amount to significantly more than the judicial exception.
Claims 2-3 and 5-7 recite further limitations that are abstract mathematical steps or concepts without reciting any additional elements that make the claim(s) any less abstract, that impose meaningful limits on practicing the abstract idea, or are sufficient to amount to significantly more than the judicial exception. Thus, the claims do not qualify as a practical application under Prong Two of Step 2A and do not provide an inventive concept under Step 2B.
Claim 8 recites that the circuitry comprises one of hardware logic gates and a processor. However, the “processor”, for example, is recited at a high-level of generality. For instance, the claim fails to provide any detail as to the structure or function of the processor. Under Prong Two of Step 2A, such limitation(s) do not integrate the abstract idea into a practical application because they fail to provide a meaningful limitation on the claimed steps, and amount to no more than mere instructions to apply the exception using generic computer components. Under Step 2B, mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. See MPEP § 2106.05(f). Thus, the claim does not qualify as a practical application under Prong Two of Step 2A and does not provide an inventive concept under Step 2B.
Accordingly, Claims 2-3 and 5-8 are not patent-eligible under 35 U.S.C. 101.
As per Claim 9, it recites encoding floating point numbers, comprising identifying numbers which represent zero and non-zero values, converting the numbers to a block floating point format value, and generating an encoded sparse block floating point value.
Under Prong One of Step 2A of the USPTO current eligibility, such limitations cover mathematical calculations, relationships, and/or formulas. See e.g. Figures 3-4 and Paragraphs 0039 and 0045-0046 of the instant specification, which describes identifying and converting the numbers as comprising mathematical comparisons and sorting and shifting numbers. Moreover, converting from one numerical format to another numerical format is necessarily an expression of mathematical relationships. Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. In particular, the claim fails to recite any additional elements, and is purely abstract. As described above, the claim recites a series of mathematical steps. However, the claim does not recite a computer implementation, any hardware or software component, or any additional limitation that would make the claim any less abstract. Since the entire claim falls within the “Mathematical Concepts” grouping of abstract ideas, the abstract idea is not integrated into a practical application and the claim is thus directed to an abstract idea.
Under Step 2B, as discussed above, the claim does not include additional elements and therefore cannot amount to significantly more than the judicial exception. Accordingly, Claim 9 is not patent-eligible under 35 U.S.C. 101.
As per Claims 10-15, they are rejected under 35 U.S.C. 101 as non-statutory for at least the reasons stated above. The claims are dependent on Claim 9, but fail to include any additional elements sufficient to amount to significantly more than the judicial exception.
Claims 10-15 recite further limitations that are abstract mathematical steps or concepts without reciting any additional elements that make the claim(s) any less abstract, that impose meaningful limits on practicing the abstract idea, or are sufficient to amount to significantly more than the judicial exception. Thus, the claims do not qualify as a practical application under Prong Two of Step 2A and do not provide an inventive concept under Step 2B.
Accordingly, Claims 10-15 are not patent-eligible under 35 U.S.C. 101.
As per Claim 16, it recites decoding floating point numbers, comprising converting an encoded block floating point format value to a set of non-zero floating point numbers, and generating a non-sparse set of floating-point values.
Under Prong One of Step 2A of the USPTO current eligibility, such limitations cover mathematical calculations, relationships, and/or formulas. See e.g. Figures 5-6, which describes decoding floating point numbers as comprising sorting and shifting numbers. Moreover, converting from one numerical format to another numerical format is necessarily an expression of mathematical relationships. Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a “processing device” comprising “circuitry” configured to perform the numerical format conversion and “memory” configured to store data. However, these elements are recited at a high-level of generality (i.e. as generic computer components performing generic computer function(s) such as mathematical computations and storing data). For example, the “memory” merely operates to generically store and provide data for use in the claimed abstract idea, and the claim fails to recite structural or functional limitations that would make the memory any more particular than a generic computer memory. Moreover, since the claim fails to include any detail(s) as to the structure of the claimed “processing device” or “circuitry”, or how they particularly function to perform the recited calculations or functions, these additional limitations fail to provide a meaningful limitation on the claimed steps, and amount to no more than mere instructions to apply the exception using generic computer components. Accordingly, the abstract idea is not integrated into a practical application because the additional element(s) do not impose any meaningful limits on practicing the abstract idea, i.e. the claim is directed to an abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, using a generic processor or generic computer component(s) to perform the claimed mathematical steps amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. See MPEP § 2106.05(f). Furthermore, storing and retrieving data in a memory is well-understood, routine, conventional activity that fails to qualify as significantly more than the judicial exception. See MPEP 2106.05(d)(II), “storing and retrieving information in memory”. Accordingly, Claim 16 is not patent-eligible under 35 U.S.C. 101.
As per Claims 17-20, they are rejected under 35 U.S.C. 101 as non-statutory for at least the reasons stated above. The claims are dependent on Claim 16, but fail to include any additional elements sufficient to amount to significantly more than the judicial exception.
Claims 17-19 recite further limitations that are abstract mathematical steps or concepts without reciting any additional elements that make the claim(s) any less abstract, that impose meaningful limits on practicing the abstract idea, or are sufficient to amount to significantly more than the judicial exception. Thus, the claims do not qualify as a practical application under Prong Two of Step 2A and do not provide an inventive concept under Step 2B.
Claim 20 recites a display device configured to display information derived from the floating point numbers. However, the “display device” is recited at a high-level of generality, i.e. operating to generically display data resulting from the claimed abstract idea. Additionally, “display[ing]” the information is recited in a way that could be attached to any mathematical calculation or algorithm, and thus fails to impose meaningful limits on practicing the abstract idea. Thus, under Prong Two of Step 2A, the claimed display device amounts to no more than mere instructions to apply the judicial exception using generic computer components, and the step of displaying data is an insignificant extra-solution activity, which fails to integrate the claim(s) into a practical application. Under Step 2B, the claimed display amounts to no more than mere instructions to apply the exception using generic computer components, and furthermore, generically outputting data to/from the recited judicial exception represents mere data output and is insignificant extra-solution activity. The courts have found limitations directed to outputting information electronically, when recited at a high level of generality, to be well-understood, routine, and conventional. See MPEP 2106.05(d)(II), “storing and retrieving information in memory”, “receiving or transmitting data over a network”. Thus, the claim does not qualify as a practical application under Prong Two of Step 2A and does not provide an inventive concept under Step 2B.
Accordingly, Claims 17-20 are not patent-eligible under 35 U.S.C. 101.
Allowable Subject Matter
Claims 1-2, 5-10, and 12-20 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) and 35 U.S.C. 101 set forth in this Office action.
Claims 3 and 11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 101 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 4 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lo et al. (US 2019/0347072) – discloses a system for block floating point computation in a neural network, comprising receiving a plurality of floating point numbers, grouping the mantissa portions of the numbers, and selecting a shared exponent for the grouped mantissas.
Burgess et al. (US 2024/0045653) – discloses converting floating point number(s) into an Enhanced Block Floating Point (EBFP) format comprising a block of shifted mantissas with a shared exponent, and further comprising a tag field, wherein small floating point numbers (that would ordinarily be set to zero) are represented by the difference between the exponent and the shared exponent, and the tag field indicates whether the EBFP number represents a shifted significand or the exponent difference.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SANDIFER whose telephone number is (571)270-5175. The examiner can normally be reached Mon-Fri 9:30am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW D SANDIFER/Primary Examiner, Art Unit 2151
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