DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10790828 B1 Gunter et al., (hereinafter “Gunter”)
Regarding claim 1, Gunter teaches the following:
an integrated circuit for implementing a neural network comprising a plurality of neural network layers (abstract, col 4 lines 12-29), the circuit comprising:
a plurality of compute tiles configured to process data used to generate an output of a neural network layer (fig 1 tiles 102, col 4 line 20-50, col 7 line 14-38 compute layer inferences for generate an output of a neural network layer);
a first vector unit configured to perform operations on first data values provided along a first dimension of the integrated circuit from a first subset of the plurality of compute tiles (fig 1 106, fig 3A 104, col 4 line 51 – col 5 line 19, col 7 line 44-55, col 7 line 60-65, one segment of 106 for first vector unit, 1 DU for first dimension of the integrated circuit);
a second vector unit configured to perform operations on second data values provided along the first dimension of the integrated circuit from a second subset of the plurality of compute tiles (fig 1 106, fig 3A 104, col 4 line 51 – col 5 line 19,col 7 line 44-55, col 7 line 60-65, one segment of 106 for first vector unit, a second segment of 106 for second vector unit, 1 DU for first dimension of the integrated circuit);
a set of data paths configured to couple a given vector unit and a particular subset of compute tiles such that data values are routable between the given vector unit and the particular subset of compute tiles (col 5 line 37-40, col 8 line 2 – line 25); and
a set of vector data paths configured to couple the first vector unit and the second vector unit to support neural network computations that are performed using one or more of the plurality of compute tiles (col 5 37-43, col 6 line 13-17).
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, Gunter teaches the following:
wherein the plurality of compute tiles and the first and second vector units cooperate to generate respective outputs for each layer of the plurality of neural network layers based on data values that are routed using the set of data paths and the set of vector data paths (col 4 line 12-50).
Regarding claim 3, in addition to the teachings addressed in the claim 2 analysis, Gunter teaches the following:
a first set of data paths configured to couple the first vector unit and the first subset of compute tiles such that the first data values are routable between the first vector unit and the first subset of compute tiles (fig 6A left most column direction from T’s to ID, col 16 line 18-65); and
a second set of data paths configured to couple the second vector unit and the second subset of compute tiles such that the second data values are routable between the second vector unit and the second subset of compute tiles (fig 6A second to left most column direction from T’s to ID, col 16 line 18-65) .
Regarding claim 4, in addition to the teachings addressed in the claim 3 analysis, Gunter teaches the following:
a first set of vector data paths configured to couple the first vector unit and the second vector unit along the first dimension of the integrated circuit to support the neural network computations that are performed using one or more of the plurality of compute tiles (col 5 37-43, col 6 line 13-17).
Regarding claim 5, in addition to the teachings addressed in the claim 4 analysis, Gunter teaches the following:
a second set of vector data paths configured to couple the first vector unit or the second vector unit to another vector unit along a second dimension of the integrated circuit to support the neural network computations that are performed using one or more of the plurality of compute tiles (col 11 line 56-59, line 65- col 12 21, fig 2 220, bus lines in second dimension from 101, coupling to a segment of vector units including another vector unit).
Regarding claim 6, in addition to the teachings addressed in the claim 5 analysis, Gunter teaches the following:
the integrated circuit is a neural network processor configured to perform deterministic operations based on a plurality of predetermined instructions that are executed using one or more sets of clock signals (col 5 line 20-36, col 5 line 55 – col 6 line 36); and
the first and second set of data paths and the first and second set of vector data paths are a dynamically configurable routing network of the neural network processor that dynamically routes data processed by the neural network processor (abstract, fig 2, col 10 line 17 – col 12 line 21).
Regarding claim 7, in addition to the teachings addressed in the claim 3 analysis, Gunter teaches the following:
data paths in the first set of data paths are partial-sum buses configured to provide a first portion of partial sums from the first subset of compute tiles to the first vector unit when performing the neural network computations (col 11 line 33 – line 59, fig 2 partial sums, fig 6A, col 15 line 47-52); and
data paths in the second set of data paths are partial-sum buses configured to provide a second portion of partial sums from the second subset of compute tiles to the second vector unit when performing the neural network computations (col 11 line 33 – line 59, fig 2 partial sums, fig 6A, col 15 line 47-52).
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, Gunter teaches the following:
wherein the data comprise: a first plurality of inputs that are processed at the neural network layer to generate a first plurality of activation values representing the output of the neural network layer (col 1 line 19-54, col 2 line 49-col 3 line 56); or
a second plurality of inputs that are processed at a second neural network layer to generate a second plurality of activation values representing an output of the second neural network layer (col 1 line 19-54, col 2 line 49-col 3 line 56) .
Regarding claim 9, in addition to the teachings addressed in the claim 8 analysis, Gunter teaches the following:
the output of the neural network layer is provided as an input to the second neural network layer, such that the first plurality of activation values and the second plurality of inputs are the same (col 1 line 19-27).
Regarding claim 11, in addition to the teachings addressed in the claim 1 analysis, Gunter teaches the following:
each of the plurality of compute tiles includes a respective multi-dimensional array of compute cells that are configured to compute one or more partial sums (fig 1 four tiles shown, 110a, 110b, 110c, and 110d each with compute cells 102, col 13 line 52-col 14 line 3).
Regarding claim 12, Gunter teaches the following:
a method for generating an output of a neural network layer using a plurality of compute tiles of an integrated circuit that implements a neural network comprising a plurality of neural network layers (abstract, col 4 lines 12-29, fig 1, fig 2), the method comprising:
computing, using the plurality of compute tiles, multiple data values from an input dataset (fig 1 tiles 102, col 4 line 20-50, col 7 line 14-38 compute layer inferences for generate an output of a neural network layer) ;
processing, by a first vector unit of the integrated circuit, first data values provided along a first dimension of the integrated circuit from a first subset of the plurality of compute tiles (fig 1 106, fig 3A 104, col 4 line 51 – col 5 line 19, col 7 line 44-55, col 7 line 60-65, one segment of 106 for first vector unit, 1 DU for first dimension of the integrated circuit);
processing, by a second vector unit of the integrated circuit, second data values provided along the first dimension of the integrated circuit from a second subset of the plurality of compute tiles (fig 1 106, fig 3A 104, col 4 line 51 – col 5 line 19,col 7 line 44-55, col 7 line 60-65, one segment of 106 for first vector unit, a second segment of 106 for second vector unit, 1 DU for first dimension of the integrated circuit);
using vector data paths that couple the first and second vector units to route different types of data values between the first vector unit and second vector unit when the first or second data values are being processed (col 5 line 37-40, col 8 line 2 – line 25, col 5 37-43, col 6 line 13-17); and
generating the output of the neural network layer based on the processing of the first or second data values and the different types of data values that are routed between the first and second vector units via the set of vector data paths (col 1 line 19-54, col 2 line 49-col 3 line 56).
Regarding claim 13, in addition to the teachings addressed in the claim 12 analysis, Gunter teaches the following:
wherein processing the first data values comprises: processing the first data values in response to receiving the first data values along the first dimension from the first subset of compute tiles via a first set of data paths that are configured to couple the first subset of compute tiles and the first vector unit, such that the first data values are routable between the first subset of compute tiles and the first vector unit (fig 6A leftmost column).
Regarding claim 14, in addition to the teachings addressed in the claim 13 analysis, Gunter teaches the following:
wherein processing the second data values comprises: processing the second data values in response to receiving the second data values along the first dimension from the first subset of compute tiles via a second set of data paths that are configured to couple the second subset of compute tiles and the second vector unit, such that the second data values are routable between the second subset of compute tiles and the second vector unit (Fig 6A, second to leftmost column).
Regarding claim 15, in addition to the teachings addressed in the claim 14 analysis, Gunter teaches the following:
wherein data paths in the first set of data paths are partial-sum buses and the method comprises: providing, via the first set of data paths, a first portion of partial sums from the first subset of compute tiles to the first vector unit when performing neural network computations at the integrated circuit (col 11 line 33 – line 59, fig 2 partial sums, fig 6A, col 15 line 47-52).
Regarding claim 16, in addition to the teachings addressed in the claim 15 analysis, Gunter teaches the following:
wherein data paths in the second set of data paths are partial- sum buses and the method comprises: providing, via the second set of data paths, a second portion of partial sums from the second subset of compute tiles to the second vector unit when performing the neural network computations at the integrated circuit (col 11 line 33 – line 59, fig 2 partial sums, fig 6A, col 15 line 47-52).
Regarding claim 17, in addition to the teachings addressed in the claim 15 analysis, Gunter teaches the following:
wherein the plurality of compute tiles and the first and second vector units cooperate to generate respective outputs for each layer of the plurality of neural network layers based on data values that are routed using the first and second set of data paths and the vector data paths (fig 1, fig 2, col 1 line 19-54, col 2 line 49-col 3 line 56).
Regarding claim 18, in addition to the teachings addressed in the claim 17 analysis, Gunter teaches the following:
the integrated circuit is a neural network processor configured to perform deterministic operations based on a plurality of predetermined instructions that are executed using one or more sets of clock signals
(col 5 line 20-36, col 5 line 55 – col 6 line 36); and
the method further comprises: dynamically configuring a routing network of the neural network processor to dynamically route data processed by the neural network processor when performing the neural network computations (abstract, fig 2, col 10 line 17 – col 12 line 21).
Regarding claim 19, in addition to the teachings addressed in the claim 18 analysis, Gunter teaches the following:
wherein the routing network comprises the first and second set of data paths and the vector data paths; and the vector data paths comprise:
a first set of vector data paths configured to couple the first vector unit and the second vector unit along the first dimension of the integrated circuit (col 5 37-43, col 6 line 13-17); and
a second set of vector data paths configured to couple the first vector unit or the second vector unit to another vector unit along a second dimension of the integrated circuit (col 11 line 56-59, line 65- col 12 21, fig 2 220, bus lines in second dimension from 101, coupling to a segment of vector units including another vector unit).
Regarding claim 20, Gunter teaches the following:
a processing device ( ig 1);
an integrated circuit that implements a neural network comprising a plurality of neural network layers (fig 1, fig 2, col 4 line 12- col 5 line 36); and
a non-transitory machine-readable storage device storing instructions for generating an output of a neural network layer using a plurality of compute tiles of the integrated circuit, the instructions being executable by the processing device to cause performance of operations (abstract, fig 1, fig 2, col 18 line 33-53, col 19 line 45-53) comprising:
computing, using the plurality of compute tiles, multiple data values from an input dataset (fig 1 tiles 102, col 4 line 20-50, col 7 line 14-38 compute layer inferences for generate an output of a neural network layer);
processing, by a first vector unit of the integrated circuit, first data values provided along a first dimension of the integrated circuit from a first subset of the plurality of compute tiles (fig 1 106, fig 3A 104, col 4 line 51 – col 5 line 19, col 7 line 44-55, col 7 line 60-65, one segment of 106 for first vector unit, 1 DU for first dimension of the integrated circuit);
processing, by a second vector unit of the integrated circuit, second data values provided along the first dimension of the integrated circuit from a second subset of the plurality of compute tiles (fig 1 106, fig 3A 104, col 4 line 51 – col 5 line 19,col 7 line 44-55, col 7 line 60-65, one segment of 106 for first vector unit, a second segment of 106 for second vector unit, 1 DU for first dimension of the integrated circuit);
using vector data paths that couple the first and second vector units to route different types of data values between the first vector unit and second vector unit when the first or second data values are being processed (col 5 line 37-40, col 8 line 2 – line 25, col 5 37-43, col 6 line 13-17); and
generating the output of the neural network layer based on the processing of the first or second data values and the different types of data values that are routed between the first and second vector units via the set of vector data paths (col 1 line 19-54, col 2 line 49-col 3 line 56).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gunter in view of A. Gomperts, et al., Implementation of Neural Network on Parameterized FPGA, AAAI Spring Symposium: Embedded Reasoning, AAAI Spring Symposium: Embeeded Reasoning, 2010 (hereinafter “Gomperts”).
Regarding claim 10, in addition to the teachings addressed in the claim 1 analysis, Gunter teaches a memory unit accessible at the integrated circuit (fig 2 SRAM connected to routing buses). Gunter further discloses performing functional arithmetic operations including non-linear functions (col 4 line 51-62). Gunter does not, however explicitly disclose wherein the memory unit is configured to perform arithmetic operations that enable interpolation of data values obtained from a loadable table of values. However, in the same field of endeavor, Gomperts discloses an apparatus implementing a neural network including performing arithmetic non-linear function operations (abstract, Introduction, Background Information section). Gomperts further discloses a functional memory unit configured to perform arithmetic operations that enable interpolation of data values obtained from a loadable table of values implemented in RAM (Uniform Lookup Table Implementation).
It would have been obvious to one of ordinary skill in the art before the effective filing date to store the lookup table of Gomperts in the SRAM of Gunter for Gunter to use in applying a non-linear function to the output of the tiles of Gunter. It would have been obvious to achieve the benefit of a reduced size LUT with the same degree of accuracy of the cost of arithmetic units to calculation non-linear functions (Gomperts conclusion).
Conclusion
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/EMILY E LAROCQUE/Examiner, Art Unit 2182
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