DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed December 16th, 2022. Claims 1-25 are pending, of which claims 1-25 are currently rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/02/2024 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 1-16 and 21-23 are objected to because of the following informalities which recite grammatical issues:
Claim 1 line 3 “the processor to perform operations” should be “the processor is to perform operations”
Claim 1 lines 4-5 “unsigned integer multiply-accumulate instruction to indicate” should be “unsigned integer multiply-accumulate instruction is to indicate”
Claim 1 lines 5-6 “a first register that is have a third unsigned integer” should be “a first register that is to have a third unsigned integer”
Claims 2-16 are objected to based on their dependence on claim 1.
Claim 4 line 2 “a third register used to store” should be “a third register is used to store”
Claim 21 line 3 “the process to perform” should be “the process is to perform”
Claim 21 lines 4-5 “the unsigned integer multiply-accumulate instruction to indicate” should be “the unsigned integer multiply-accumulate instruction is to indicate”
Claim 21 lines 5-6 “a first register that is have a third unsigned integer” should be “a first register that is to have a third unsigned integer”
Claim 23 line 2 “third and fourth registers respectively used” should be “third and fourth registers are respectively used”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation “the processor is store bit values of zero to all bit positions…”. The entirety of the clause is unclear as what is being referring to because of the lack of clarity in language. Examiner will construe the meaning of the clause to be padding of more significant values of the register with 0 values, for examination purposes. Appropriate correction is required.
Claim 22 recites the limitation “the processor is store bit values of zero to all bit positions…”. The entirety of the clause is unclear as what is being referring to because of the lack of clarity in language. Examiner will construe the meaning of the clause to be padding of more significant values of the register with 0 values, for examination purposes. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 14, 16-17, 20, 21, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal et al. (10649774) (hereinafter “Gopal”).
Regarding claim 1, Gopal teaches:
An apparatus comprising:
A cache (Gopal: Fig. 12 element 1296); and
a processor, the processor to perform operations corresponding to an unsigned integer multiply-accumulate instruction (Gopal: Fig. 12 element 1200, Abstract, Fig. 3 shows operands operated on are unsigned integers of varying precisions; Col. 8 Lines 23-57 multiply instruction followed by add instruction i.e., multiply accumulate instruction), the unsigned integer multiply-accumulate instruction to indicate a first unsigned integer, a second unsigned integer (Gopal: Col. 4 Lines 8-17 accessing of first and second source operand that are registers storing unsigned integers; Fig. 9 shows the unsigned integers in respective registers), a first register that is have a third unsigned integer (Gopal: Col. 8 Lines 47-53 third and fourth unsigned integers are multiplied and stored in destination operand i.e., third unsigned integer in first register), and a second register (Gopal: Col. 9 Lines 50-54 high order and low order bits of [sum] may be stored in two separate registers), the operations including to:
multiply the first unsigned integer and the second unsigned integer to generate a product (Gopal: Col. 9 Lines 50-54 product of first and second source operands is added to this third unsigned integer; Fig 9 and 10 show source operands as registers);
add the product and the third unsigned integer to generate a sum (Gopal: Col. 8 Lines 47-53 third and fourth unsigned integers are multiplied and stored in destination operand i.e., third unsigned integer in first register, product of first and second source operands is added to this third unsigned integer; Figs. 9 and 10 operands as registers);
store a first portion of the sum in the second register wherein the first portion of the sum includes M least significant bits of the sum (Gopal: Col. 9 Lines 50-54 high order and low order bits of [sum] may be stored in two separate registers, including a second register, including the first register; Col. 8 Lines 58-65 DEST register may be overwritten with new results); and
store a second portion of the sum in the first register, wherein the second portion of the sum includes all bits of the sum that are more significant than the M least significant bits (Gopal: Col. 9 Lines 50-54 high order and low order bits of [sum] may be stored in two separate registers, including a second register, including the first register; Col. 8 Lines 58-65 DEST register may be overwritten with new results).
Gopal does not explicitly teach the processor being coupled to the cache, or the instruction being explicitly called a multiply-accumulate instruction.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the cache and processor separate from each other, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179.
Additionally, while Gopal does not teach the instruction being explicitly called a multiply-accumulate, Gopal does teach the multiplication operation being followed by an add instruction, and having new results overwriting previous results within the corresponding registers, which one with ordinary skill in the art would know follows the flow of a multiply-accumulate instruction (Gopal: Col. 9 Lines 50-54 high order and low order bits of [sum] may be stored in two separate registers, including a second register, including the first register; DEST register may be overwritten with new results Col. 8 Lines 58-65).
Regarding claim 2, Gopal teaches:
The apparatus of claim 1, wherein the processor is to store a least significant bit of the second portion of the sum at bit position zero of the first register (Gopal: Col. 9 Lines 50-54 high order and low order bits of [sum] may be stored in two separate registers, including a second register and first register, LSB will be stored in second register starting at bit position 0).
Regarding claim 4, Gopal teaches:
The apparatus of claim 1, wherein the first register is a different type of register than the second register, a third register used to store the first unsigned integer, and a fourth register used to store the second unsigned integer (Gopal: Col. 9 Lines 7-25 first and second registers may be either implicit or explicit destination operands (for facilitating MOV operations), also shown in Fig. 9; Fig. 1 elements SRC1 and SRC2 as third and fourth registers).
Regarding claim 14, Gopal teaches:
The apparatus of claim 1, wherein the processor comprises:
decode circuitry to decode the unsigned integer multiply-accumulate instruction (Gopal: Claim 22 Col. 18 Lines 22-23); and
execution circuitry coupled with the decode circuitry, the execution circuitry to perform the operations corresponding to the unsigned integer multiply-accumulate instruction (Gopal: Claim 22 Col. 18 Lines 24-38).
Regarding claim 16, Gopal teaches:
The apparatus of claim 1, wherein the operations corresponding to the unsigned integer multiply-accumulate instruction do not include accessing a carry flag (Gopal: Col. 1 Lines 17-23 no carry flag used for multiply accumulate instructions; Col. 10 Lines 23-34 instruction may be carried out without accessing carry flag).
Claim 17 recites the method practiced by the apparatus of claim 1 and is therefore rejected for the same reasons therein.
Regarding claim 20, Gopal teaches:
The method of claim 17, further comprising processing the first and second portions of the sum as part of performing addition of integers each larger than 128-bits (Gopal: Col. 6 Lines 60-67 and Col 7 Lines 1-3).
Claim 21 recites the system comprising processor as recited in claim 1 and is therefore rejected for the same reasons therein. Claim 21 additional recites a dynamic random access memory (DRAM) coupled to the processor, which is also taught by Gopal (Gopal: Col. 14 Lines 37-43).
Regarding claim 24, Gopal teaches the instructions for practicing the method executed by the apparatus of claim 1, and is therefore rejected for the same reasons therein. Additionally, Gopal additionally teaches a non-transitory machine-readable storage medium having thereon instructions to be executed for a multiply-accumulate operation (Gopal: Col. 12 Lines 28-45).
Claims 3, 18, 22, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal further in view of Ehlig et al. (US 2005/0278512 A1) (hereinafter “Ehlig”).
Regarding claim 3, while Gopal teaches the apparatus of claim 2, Gopal does not teach storing bit values of zero to all bit positions of the first register more significant than a most significant bit of the second portion of the sum.
However, Ehlig teaches padding of zeros at most significant positions of the registers in order to avoid overflow (Ehlig: ¶ 0064).
It would be obvious before the effective filing date of the claimed invention to combine the padding of zeros in registers as taught by Ehlig with the apparatus as taught by Gopal because both references are directed towards circuit implementation of arithmetic operations. One with ordinary skill in the art would be motivated to combine the teachings because this would help with overflow prevention (Ehlig: ¶ 0064).
Regarding claim 18, Gopal teaches the method of claim 17 as well as storing of least significant bits in all registers (including the second register) starting from bit position zero (Gopal: Fig. 7 and Fig. 8 shows the unsigned integers AX-DX being at lower half of registers, including bit position zero).
Gopal does not explicitly teach storing bit values of zero to all bit positions of the first register more significant than a most significant bit of the second portion of the sum.
However, Ehlig teaches padding of zeros at most significant positions of the registers in order to avoid overflow (Ehlig: ¶ 0064).
The motivation to combine with respect to claim 3 applies equally to claim 18.
Claim 22 recites the system containing the apparatus as recited in claims 2 and 3 and is therefore rejected for the same reasons therein.
Regarding claim 25, recites the non-transitory computer readable medium containing instructions thereon to perform the method practiced by the apparatus of claim 1 and is therefore rejected for the same reasons therein.
Claims 5-10, 19, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal et al. (10649774) (hereinafter “Gopal”) further in view of Bar et al. (WO 2022/100865 A1) (hereinafter “Bar”).
Regarding claim 5, while Gopal teaches the apparatus of claim 1, Gopal does not explicitly teach the first register having more bit positions than a number of bits of each of the first unsigned integer, the second unsigned integer, and the M at least significant bits individually.
However, Bar teaches the accumulation register i.e., first register is twice the length of input operands i.e., unsigned integers, plus some guard bits (Bar: Pg. 1 in specification, Lines 19-23).
It would be obvious before the effective filing date of the claimed invention to combine the destination operand having twice the length of the inputs as taught by Bar with the apparatus as taught by Gopal because both references are directed towards implementation of arithmetic operations. One with ordinary skill in the art would be motivated to combine the teachings because doing so would further prevent overflow (Bar: Pg. 1 of Specification Lines 19-23).
Regarding claim 6, while Gopal teaches the apparatus of claim 1, Gopal does not explicitly teach the first register having more than twice as many bit positions as a number of bits of each of the first unsigned integer, the second unsigned integer, and the M least significant bits individually.
However, Bar teaches the accumulation register i.e., first register is twice the length of input operands i.e., first and second unsigned integers as well as M least significant bits, plus some guard bits (Bar: Pg. 1 in specification, Lines 19-23).
The motivation to combine with respect to claim 5 applies equally to claim 6.
Regarding claim 7, while Gopal teaches the apparatus of claim 1, Gopal does not explicitly teach the first unsigned integer and the second unsigned integer being M-bit unsigned integers, and wherein the first register has more than M bit positions.
However, Bar teaches the accumulation register i.e., first register is twice the length of input operands i.e., first and second unsigned integers, plus some guard bits (Bar: Pg. 1 in specification, Lines 19-23). Therefore, the register has more than the M bit positions.
The motivation to combine with respect to claim 5 applies equally to claim 7.
Regarding claim 8, Gopal in view of Bar further teaches accumulation register i.e., first register is twice the length of input operands i.e., unsigned integers, plus some guard bits, if register is twice the number of input bits plus some guard bits, if input is 16, register would require 16*2 + (2 or more guard bits) - yielding 34 or more bits in length (Bar: Pg. 1 in specification, Lines 19-23).
The motivation to combine with respect to claim 5 applies equally to claim 8.
Regarding claim 9, Gopal in view of Bar further teaches the accumulation register i.e., first register is twice the length of input operands i.e., unsigned integers, plus some guard bits, if register is twice the number of input bits plus some guard bits, if input is 32, register would require 32*2 + (2 or more guard bits) - yielding 66 or more bits in length (Bar: Pg. 1 in specification, Lines 19-23).
The motivation to combine with respect to claim 5 applies equally to claim 9.
Regarding claim 10, Gopal in view of Bar further teaches the accumulation register i.e., first register is twice the length of input operands i.e., unsigned integers, plus some guard bits, if register is twice the number of input bits plus some guard bits, if input is 64, register would require 64*2 + (2 or more guard bits) – yielding 130 or more bits in length (Bar: Pg. 1 in specification, Lines 19-23).
The motivation to combine with respect to claim 5 applies equally to claim 10.
Regarding claim 19, while Gopal teaches the method as recited in claim 17, Gopal does not explicitly teach the first unsigned integer being an M-bit unsigned integer, wherein M is one of 16, 32, and 64, and wherein the first register has more than twice as many bit positions as the M-bit unsigned integer.
However, Bar teaches the accumulation register i.e., first register is twice the length of input operands i.e., unsigned integers, plus some guard bits, if register is twice the number of input bits plus some guard bits (Bar: Pg. 1 in specification, Lines 19-23).
The motivation to combine with respect to claim 5 applies equally to claim 10.
Regarding claim 23, while Gopal teaches the registers being of various types (Gopal: Col. 9 Lines 7-25 first and second registers may be either implicit or explicit destination operands (for facilitating MOV operations), also shown in Fig. 9; Fig. 1 elements SRC1 and SRC2 as third and fourth registers), Gopal does not explicitly teach the first register having more bit positions than a number of bits of each of the first unsigned integer, the second unsigned integer, and the M least significant bits individually, and wherein M is one of 16, 32, and 64.
However, Bar teaches the accumulation register i.e., first register is twice the length of input operands i.e., unsigned integers, plus some guard bits, if register is twice the number of input bits plus some guard bits (Bar: Pg. 1 in specification, Lines 19-23).
The motivation to combine with respect to claim 5 applies equally to claim 23.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal in view of Langhammer (8706790) (hereinafter “Langhammer”), further in view of Ma et al. (US 2023/0206045 A1 (hereinafter “Ma”).
Regarding claim 11, while Gopal teaches the apparatus of claim 1, Gopal does not explicitly teach the first unsigned integer being an M-bit unsigned integer, wherein the second unsigned integer is a 2M-bit unsigned integer, or the first register having at least 3M bit positions.
However, Langhammer teaches varying precision or a first and second input of fixed point i.e., integer inputs, including the second input having two times the bit length of the first input (Langhammer: Col. 5 Lines 39-62 fixed number inputs i.e., integer inputs are of varying inputs, for example 18 by 36 MAC operation is carried out hence first input is M and second input is 2M).
It would be obvious before the effective filing date of the claimed invention to combine the varying precisions as taught by Langhammer with the apparatus as taught by Gopal because both teachings are directed towards circuit implementation of arithmetic operations. One with ordinary skill in the art would be motivated to combine the teachings because this would allow for further flexibility in that operations can be carried out for varying precisions (Langhammer: Col. 5 Lines 39-62).
Gopal in view of Langhammer does not explicitly teach the first register having 3M in bit length positions.
However, Ma teaches an output of the multiply-accumulate operation having three times the length of input operands, which is then stored in a result register (hence the result register would need to have at least three times the length of input operands as well). (Ma: ¶ 0072).
It would be obvious before the effective filing date of the claimed invention to combine the register having three times the length of input operands as taught by Ma with the apparatus as taught by Gopal in view of Langhammer because all references are directed towards circuit implementations of arithmetic operations. One with ordinary skill in the art would be motivated to combine the teachings because doing so would help further prevent overflow (Ma: ¶ 0072).
Regarding claim 12, Gopal in view of Langhammer in view of Ma further teaches the output register having three times the length of the input operands. So given that the input operands have a length of 16, this would require the output register to have at least 48 bits, including the possibility of having 50 bits (Ma: ¶ 0072).
The motivation to combine with respect to claim 11 applies equally to claim 12.
Regarding claim 13, Gopal in view of Langhammer in view of Ma further teaches the output register having three times the length of the input operands. So given that the input operands have a length of 32, this would require the output register to have at least 96 bits, including the possibility of having 98 bits (Ma: ¶ 0072).
The motivation to combine with respect to claim 11 applies equally to claim 13.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Gopal further in view of Ould-Ahmed-Vall et al. (10664270) (hereinafter “Ould”).
While Gopal teaches the apparatus of claim 1 as well as the processor comprising decode circuitry and scheduler circuitry (Gopal: Claim 22; Col. 5 Lines 38-43 scheduling logic), Gopal does not explicitly teach thread-based execution.
However, Ould teaches thread-based execution coupled to execution circuitry in order to carry out a multiply-accumulate instruction (Ould: Col. 20 Lines 4-14).
It would be obvious before the effective filing date of the claimed invention to combine the thread execution as taught by Ould with the apparatus as taught by Gopal because both teachings are directed towards circuit implementation of arithmetic operations. One with ordinary skill int eh art would be motivated to combine the teachings because doing so would allow for more efficient processing by simultaneous thread execution (Ould: Col. 20 Lines 4-14).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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