Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Election
1. Applicant’s election of claims 1-10 and 19-20, without traverse, in the reply filed on March 16, 2026, is acknowledged.
Claims 11-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 16, 2026.
The requirement is deemed proper and is therefore made FINAL.
Information Disclosure Statement
2. The references disclosed within the information disclosure statement (IDS) submitted on December 16, 2022, has been considered and initialed by the Examiner.
Claim Rejections – 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
4. Claims 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over
Liu et al (U.S. 6,492,269).
Liu discloses a semiconductor device comprising a substrate having semiconductor devices with prior alignment marks therein along with a dielectric layer, where trenches are formed used as alignment marks in areas of the substrate (claim 12 of Liu). Although Liu does not explicitly disclose the dielectric layer is disposed in the trench and on an alignment mark, it would have been obvious to one of ordinary skill in the art to rearrange the layer, since it has been held that rearranging the layers of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70, as in claim 1.
Concerning claim 6, although Liu does not explicitly disclose the depth of trench, as claimed, depth modifications involve a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art and therefore obvious. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert, denied, 469 U.S. 830, 225 USPQ 232 (1984) See MPEP 2144.04.
Concerning claim 7, Liu shows a recess in the bottom of the trench in Figures 1B and 1C.
Claim Rejections – 35 USC § 103
5. Claims 2-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over
Liu et al (U.S. 6,492,269) in view of Wristers et al (U.S. 5,930,620).
Liu is taken as above. Liu discloses a semiconductor device comprising a substrate having semiconductor devices with prior alignment marks therein along with a dielectric layer, where trenches are formed used as alignment marks in areas of the substrate (claim 12 of Liu). Liu does not disclose a thermal dielectric layer. Wristers teaches a thermal dielectric layer and an immersing semiconductor substrate,
where the thermal dielectric layer is believed to beneficially result in a higher quality finished product by providing a dielectric layer of improved quality between the semiconductor substrate and the trench dielectric (column 5, lines 9-33).
Liu and Wristers are combinable because they are related to a similar technical field, which is semiconductive substrates. It would have been obvious to one of ordinary skill in the art to have substituted the thermal dielectric layer, as taught in Wristers, for the dielectric layer of Liu to achieve the predictable result of improving the higher quality of the finished product of the article (column 5, lines 9-33 of Wristers), as in claim 2.
Concerning claim 3, Liu discloses a semiconductor device comprising a substrate having semiconductor devices with prior alignment marks therein along with a dielectric layer, where trenches are formed used as alignment marks in areas of the substrate (claim 12 of Liu). Liu does not disclose a thermal dielectric layer. Wristers teaches a thermal oxide liner such as thermal dielectric layer and an immersing semiconductor substrate, where the thermal dielectric layer is believed to beneficially result in a higher quality finished product by providing a dielectric layer of improved quality between the semiconductor substrate and the trench dielectric (column 5, lines 9-33). Liu and Wristers are combinable because they are related to a similar technical field, which is semiconductive substrates. It would have been obvious to one of ordinary skill in the art to have substituted the thermal oxide layer, as taught in Wristers, for the dielectric layer of Liu to achieve the predictable result of improving the higher quality of the finished product of the article (column 5, lines 9-33 of Wristers).
Concerning claim 5, Figure 1B of Liu shows an additional dielectric layer (15).
Claim Rejections – 35 USC § 103
6. Claims 1, 6, 8-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Knickerbocker et al (U.S. 2017/0133345).
Knickerbocker discloses a first substrate bonded to a second substrate comprising a semiconductor device wafer (paragraph 25) where
in one embodiment of the invention, the first substrate comprises a handler wafer which is to be bonded to a thin device wafer (paragraph 21). Knickerbocker discloses
the alignment trench can be formed with other suitable alignment mark patterns which are commonly used in the field of semiconductor fabrication. While only one alignment trench is shown in FIGS. 1A and 1B, it is to be understood that a plurality of alignment trenches are strategically formed in various surface regions of the first substrate to facilitate bonding to a device wafer (paragraph 22). Knickerbocker discloses a dielectric layer (paragraph 32). Although Knickerbocker does not explicitly disclose the dielectric layer is disposed in the trench and on an alignment mark, it would have been obvious to one of ordinary skill in the art to rearrange the layer, since it has been held that rearranging the layers of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70, as in claims 1, 8-10 and 19.
Concerning claim 6, although Knickerbocker does not explicitly disclose the depth of trench, as claimed, depth modifications involve a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art and therefore obvious. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert, denied, 469 U.S. 830, 225 USPQ 232 (1984) See MPEP 2144.04.
Claim Rejections – 35 USC § 103
7. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over
Knickerbocker et al (U.S. 2017/0133345) in view of Wristers et al (U.S. 5,930,620).
Knickerbocker is taken as above. Knickerbocker discloses
a first substrate bonded to a second substrate comprising a semiconductor device wafer (paragraph 25) where
in one embodiment of the invention, the first substrate comprises a handler wafer which is to be bonded to a thin device wafer (paragraph 21). Knickerbocker does not disclose a thermal dielectric layer. Wristers teaches a thermal dielectric layer and an immersing semiconductor substrate, where the thermal dielectric layer is believed to beneficially result in a higher quality finished product by providing a dielectric layer of improved quality between the semiconductor substrate and the trench dielectric (column 5, lines 9-33). Knickerbocker and Wristers are combinable because they are related to a similar technical field, which is semiconductive substrates. It would have been obvious to one of ordinary skill in the art to have substituted the thermal dielectric layer, as taught in Wristers, for the dielectric layer of Knickerbocker to achieve the predictable result of improving the higher quality of the finished product of the article (column 5, lines 9-33 of Wristers), as in claim 20.
Claim Objections
8. Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art does not teach or suggest the recited semiconductor structure further including where one or more dielectric layers comprise a thermal oxide layer.
The prior art does not teach motivation or suggestion for modification to make the invention as instantly claimed.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lawrence Ferguson whose telephone number is 571-272-1522. The examiner can normally be reached on Monday through Friday 9:00 AM – 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Frank Vineis, can be reached on 571-270-1547. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAWRENCE D FERGUSON/Examiner, Art Unit 1781
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