DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/19/2022 was considered by the examiner. Drawings The drawings received on 12/19/2022 have been accepted by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1-21 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Khodabandehlou et al. [US 2012/0096301] . Claim 1 , Khodabandehlou et al. discloses a memory interface circuit [400, par. 0030] comprising: first and second memory controller circuits [elements as described, par. 0032] that asynchronously receive requests for memory accesses to first and second storage circuits [first and second arrays 420 and 430, par. 0032 and par. 0035-0036] ; and first and second clock gate circuits [450 and 460] that disable and then reenable first and second clock signals in response to a clock enable signal [control logic synchronizes the asynchronous control signal to a high speed clock ( par. 0038 ); synchronized update logic generates a one shot signal to prevent data updates from propagating (par. 0040 ); multiplexer selects data from either clock domain (par. 0041 ) , wherein the first and the second memory controller circuits perform the memory accesses to the first and the second storage circuits synchronously in response to the first and the second clock signals that have been reenabled by the first and the second clock gate circuits [data register supplies output data in synchronization with clock_1 (par. 0046 and 0049); control logic synchronizes Adv_n to high speed clock (par. 0038); synchronized update logic prevents propagation until pulse is deasserted (par. 0040)] . Claim 2 , Khodabandehlou et al. discloses t he memory interface circuit of claim 1 further comprising: a first control circuit that generates the clock enable signal and that asynchronously generates a first one of the requests for accessing the first storage circuit [control logic synchronizes the asynchronous control signal to the high-speed control signal generating the control signal Adv_sync_o (par. 0038-0039); address latch 410A latches address under control of asynchronous control signal Adv_n (par. 0036 and 0045)] . Claim 3 , Khodabandehlou et al. discloses t he memory interface circuit of claim 2 further comprising: a second control circuit that asynchronously generates a second one of the requests for accessing the second storage circuit [two independent asynchronous requests paths are shown, par. 0036 and 0033] . Claim 4 , Khodabandehlou et al. discloses t he memory interface circuit of claim 1, wherein the first memory controller circuit asynchronously receives a first one of the requests for a first one of the memory accesses to the first storage circuit, and wherein the second memory controller circuit asynchronously receives a second one of the requests for a second one of the memory accesses to the second storage circuit [two storage array plus interface paths are shown, each receiving asynchronous requests wherein each path is interpreted as a memory controller circuit, par. 0033-0034 and 0036 and 0045] . Claim 5 , Khodabandehlou et al. discloses t he memory interface circuit of claim 1, wherein the first memory controller circuit performs a first one of the memory accesses to the first storage circuit in response to a first one of the requests; and wherein the second memory controller circuit performs a second one of the memory accesses to the second storage circuit in response to a second one of the requests [first storage array accessed via address latch/register to data latch/register (par. 0032, 0036-0037); second storage array accessed via its own clock domain and synchronized update logic (par. 0033, 0040)] . Claim 6 , Khodabandehlou et al. discloses t he memory interface circuit of claim 1, wherein the first memory controller circuit comprises a first register that stores a first one of the requests in response to a third clock signal and a second register that receives the first one of the requests from the first register and stores the first one of the requests in response to the first clock signal [latches, par. 0045-0046] Claim 7 , Khodabandehlou et al. discloses t he memory interface circuit of claim 6, wherein the second memory controller circuit comprises a third register that stores a second one of the requests in response to a fourth clock signal and a fourth register that receives the second one of the requests from the third register and stores the second one of the requests in response to the second clock signal [latches, par. 0048 and 0049] . Claim 8 , Khodabandehlou et al. discloses t he memory interface circuit of claim 1 further comprising: a first clock generator circuit that generates a third clock signal, wherein the first clock gate circuit generates the first clock signal based on the third clock signal; and a second clock generator circuit that generates a fourth clock signal, wherein the second clock gate circuit generates the second clock signal based on the fourth clock signal [see par. 0033-0034 and 0039] . Claim 9 , Khodabandehlou et al. discloses t he memory interface circuit of claim 1 further comprising: a first calibration control circuit that asserts the clock enable signal to disable the first and the second clock gate circuits in response to a first control signal generated by programmable logic circuits in a fabric region of an integrated circuit; and a second calibration control circuit that asynchronously generates one of the requests for accessing the second storage circuit in response to a second control signal generated by the programmable logic circuits [par. 0038-0040] . Claims 10-21 are rejected using the same rationale as Claims 1-9. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lethin et al. [US 11,500,621]; Methods and Apparatus for Data Transfer Optimization. See Claims 1, 20-21, 25. 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