Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This action is in response to the amendment and argument field on 17 October 2025.
2. Claims 1-20 remain Pending and Rejected.
Responses to the Argument
3. The applicant’s arguments filed on 17 October 2025 have been fully considered but they are not persuasive. In the Remarks, the applicant has argued in substance:
Argument:
Case does not teach at least "creating, by a control entity, a secure maintenance challenge comprising a unique identification (ID) of a chip of an electronic device," as recited in claim 1. And Case does not teach at least "providing, to the control entity by the signing entity, the response," as recited in claim 1.
Response:
Examiner respectfully disagrees, because, prior arts teach use of nonce, which is security token in order to gain access (Peterka, ¶6), using challenge/response mechanism (Case, ¶11). A challenge/response process using a key of the IC device and a challenge value generated at the IC device for authentication purpose and the code signing server ( a signature authentication module, Case, ¶34) then generates a response value based on the challenge value and provides the response value to the IC device via the debug interface. Once the boot code signature and the new boot code image have been encrypted together, the resulting encrypted component is included in an access token object created and signed by the access token server 38. The access token also can include the chip serial number, which was supplied to the access token server 38 by the end user. Please see Peterka, ¶44. Therefore, combination od Peterka and Case teach the limitation of claim 1 and dependent claims.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C §103 as being unpatentable over Case et al. (US Publication No. 20100199077), hereinafter Case and in view of Peterka et al. (US Publication No. 20100217964), hereinafter Peterka.
Regarding claim 1:
creating, by a control entity, a secure maintenance challenge comprising a unique identification (ID) of a chip of an electronic device (Case, ¶11, ¶15, ¶27, ¶30).
providing, to a signing entity by the control entity, the secure maintenance challenge (Case, ¶15, 39, 42).
signing, by the signing entity, the secure maintenance challenge to provide a response comprising the secure maintenance challenge and a signature (Case, ¶31-32, 34).
providing, to the control entity by the signing entity, the response (Case, ¶11, 31).
Case does not explicitly suggest, based at least in part on the response, creating, by the control entity, a secure maintenance image comprising the secure maintenance challenge and the signature; however, in a same field of endeavor Peterka discloses this limitation (Peterka, ¶40, 69, FIG. 4).
providing, by the control entity, the secure maintenance image to a non-volatile memory of the chip; however, in a same field of endeavor Peterka discloses this limitation (Peterka, Fig.4).
during a boot process of the electronic device, authenticating, by a boot image, the secure maintenance image; however, in a same field of endeavor Peterka discloses this limitation (Peterka, ¶40-42, 45).
and based at least in part on authenticating the secure maintenance image, enabling, by the chip, a feature of the chip (Case, ¶27).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include the method of challenge/response of Case with the method of new boot-image generation disclosed in Peterka to enable access particular portion of the code to test stated by Peterka at ¶49.
Regarding claim 2:
wherein the chip comprises a system-on-chip (SoC) and enabling the feature of the chip comprises: enabling debugging of one or more processors of the SoC (Case, ¶27, abstract).
Regarding claim 3:
wherein enabling the feature of the chip comprises: programming of fuses (Case, ¶10).
Regarding claim 4:
wherein programming of fuses comprises: programming of lifecycle fuses (Case, ¶10).
Regarding claim 5:
wherein enabling the feature of the chip comprises: enabling access to maintenance ports of the chip (Case, ¶11).
Regarding claim 6:
wherein enabling access to maintenance ports of the chip comprises: enabling access to maintenance ports of the chip for debugging of a next stage boot image located on the non-volatile memory (Case, ¶15).
Regarding claim 7:
Case does not explicitly suggest, wherein authenticating, by the boot image, the secure maintenance image comprises: authenticating an exclusive chip ID (ECID) of the chip; authenticating a hash of a loader; and authenticating debug lifecycles within the secure maintenance image (Peterka, ¶26-27, 50).
Same motivation for combining the respective features of Case and Peterka applies herein, as discussed in the rejection of claim 1.
Regarding claim 8:
further comprising: based at least in part on a delay within the secure maintenance image, delaying loading, by the firmware executing from read-only memory (ROM) on the chip, a boot code (Case, ¶11).
Regarding claim 9:
one or more processors (Case, ¶23).
and one or more non-transitory computer-readable media storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform actions comprising (Case, ¶29): creating, by a control entity, a secure maintenance challenge comprising a unique identification (ID) of a chip of an electronic device (Case, ¶11, ¶15, ¶27, ¶30).
providing, to a signing entity by the control entity, the secure maintenance challenge (Case, ¶15, 39, 42).
signing, by the signing entity, the secure maintenance challenge to provide a response comprising the secure maintenance challenge and a signature (Case, ¶31-32, 34).
providing, to the control entity by the signing entity, the response (Case, ¶11, 31).
Case does not explicitly suggest, based at least in part on the response, creating, by the control entity, a secure maintenance image comprising the secure maintenance challenge and the signature; however, in a same field of endeavor Peterka discloses this limitation (Peterka, ¶40, 69, FIG. 4).
providing, by the control entity, the secure maintenance image to a non-volatile memory of the chip; however, in a same field of endeavor Peterka discloses this limitation (Peterka, Fig.4).
during a boot process of the electronic device, authenticating, by a boot image, the secure maintenance image; however, in a same field of endeavor Peterka discloses this limitation (Peterka, ¶40-42, 45).
and based at least in part on authenticating the secure maintenance image, enabling, by the chip, a feature of the chip (Case, ¶27).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include the method of challenge/response of Case with the method of new boot-image generation disclosed in Peterka to enable access particular portion of the code to test stated by Peterka at ¶49.
Regarding claim 10:
wherein the chip comprises a system-on-chip (SoC) and enabling the feature of the chip comprises: enabling debugging of one or more processors of the SoC (Case, ¶27, abstract).
Regarding claim 11:
wherein enabling the feature of the chip comprises: programming of fuses (Case, ¶10).
Regarding claim 12:
wherein programming of fuses comprises: programming of lifecycle fuses (Case, ¶10).
Regarding claim 13:
wherein enabling the feature of the chip comprises: enabling access to maintenance ports of the chip (Case, ¶11).
Regarding claim 14:
wherein enabling access to maintenance ports of the chip comprises: enabling access to maintenance ports of the chip for debugging of a next stage boot image located on the non-volatile memory (Case, ¶15).
Regarding claim 15:
Case does not explicitly suggest, wherein authenticating, by the boot image, the secure maintenance image comprises: authenticating an exclusive chip ID (ECID) of the chip; authenticating a hash of a loader; and authenticating debug lifecycles within the secure maintenance image (Peterka, ¶26-27, ¶50).
Same motivation for combining the respective features of Case and Peterka applies herein, as discussed in the rejection of claim 9.
Regarding claim 16:
wherein the actions further comprise: based at least in part on a delay within the secure maintenance image, delaying loading, by the firmware executing from read-only memory (ROM) on the chip, a boot code (Case, ¶11).
Regarding claim 17:
creating, by a control entity, a secure maintenance challenge comprising a unique identification (ID) of a chip of an electronic device (Case, ¶11, ¶15, ¶27, ¶30).
providing, to a signing entity by the control entity, the secure maintenance challenge (Case, ¶15, 39, 42).
signing, by the signing entity, the secure maintenance challenge to provide a response comprising the secure maintenance challenge and a signature (Case, ¶31-32, 34).
providing, to the control entity by the signing entity, the response (Case, ¶11, 31).
Case does not explicitly suggest, based at least in part on the response, creating, by the control entity, a secure maintenance image comprising the secure maintenance challenge and the signature; however, in a same field of endeavor Peterka discloses this limitation (Peterka, ¶40, 69, FIG. 4).
providing, by the control entity, the secure maintenance image to a non-volatile memory of the chip; however, in a same field of endeavor Peterka discloses this limitation (Peterka, Fig.4).
during a boot process of the electronic device, authenticating, by a boot image, the secure maintenance image; however, in a same field of endeavor Peterka discloses this limitation (Peterka, ¶40-42, 45).
and based at least in part on authenticating the secure maintenance image, enabling, by the chip, a feature of the chip (Case, ¶27).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include the method of challenge/response of Case with the method of new boot-image generation disclosed in Peterka to enable access particular portion of the code to test stated by Peterka at ¶49.
Regarding claim 18:
wherein enabling the feature of the chip comprises: enabling access to maintenance ports of the chip (Case, ¶11).
Regarding claim 19:
wherein enabling access to maintenance ports of the chip comprises: enabling access to maintenance ports of the chip for debugging of a next stage boot image located on the non-volatile memory (Case, ¶15).
Regarding claim 20:
Case does not explicitly suggest, wherein authenticating, by the boot image, the secure maintenance image comprises: authenticating an exclusive chip ID (ECID) of the chip; authenticating a hash of a loader; and authenticating debug lifecycles within the secure maintenance image (Peterka, ¶26-27, ¶50).
Same motivation for combining the respective features of Case and Peterka applies herein, as discussed in the rejection of claim 17.
Conclusion
5. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure (See form “PTO-892 Notice of reference cited).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONJUR RAHIM whose telephone number is (571)270-3890.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shewye Gelagay can be reached on 571-272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Monjur Rahim/
Patent Examiner
United States Patent and Trademark Office
Art Unit: 2436; Phone: 571.270.3890
E-mail: monjur.rahim@uspto.gov
Fax: 571.270.4890