DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-17 are presented for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on December 19, 2022; July 8, 2025; and March 6, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 16 is objected to because of the following informalities: “OR gate configured” should be “OR gate is configured”. Claim 17 is objected to for dependency on claim 16. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sumbul et al. (US 20190042909) (“Sumbul”) in view of Barton (WO 2020190825) (“Barton”).
Regarding claim 1, Sumbul discloses “[a] neuron circuit comprising:
a first internal circuit configured to receive a plurality of spike input signals, to generate a first sum value by summing a plurality of synaptic weights corresponding to the plurality of spike input signals, and to output a second sum value by adding a membrane potential value to the first sum value (the neuron may perform a function utilizing the values of its inputs and its current membrane potential; for example, the inputs may be added to the current membrane potential of the neuron to generate an updated membrane potential [i.e., if there are two or more inputs, adding each of them to the membrane potential is equivalent to adding the inputs to generate a first sum and adding the sum of the inputs to the existing membrane potential to generate a second sum]; when a neuron spikes, the spike may be propagated to one or more connected neurons residing on the same neuro-synaptic core block [i.e., the inputs are spikes]– Sumbul, paragraph 31; see also Figs. 3B and 4 (showing multiple neurosynaptic cores [including a first internal circuit]));
a spike generating circuit configured to generate a spike output signal by comparing the second sum value with a threshold potential value (neuron may propagate a spike signal to connected neurons when a threshold associated with the neuron is surpassed [i.e., the second sum value is compared with the threshold] – Sumbul, paragraph 2);
a membrane potential generating circuit configured to generate the membrane potential value, which is obtained by subtracting the threshold potential value from the second sum value1, based on the spike output signal (see footnote 1 and mapping to the first two limitations of this claim and note that Sumbul paragraph 31 discloses that the membrane potential value is based on the inputs to the neuron and that the inputs are spikes output from other neurons, i.e., the membrane potential value is based on the spike output signal) …;
a second internal circuit configured to count a last spike time based on the spike output signal (neuron core [internal circuit] may track spike timing [count a last spike time, based on the spike] if online learning is implemented and send out appropriate learn signals – Sumbul, paragraph 75; see also Fig. 3B (showing that there are multiple neurosynaptic cores, i.e., multiple internal circuits)); and
an online learning circuit configured to:
receive a last input time from the first internal circuit and perform long-term potentiation (LTP) learning based on the last input time (if a learn signal is received, the weight is updated with the appropriate learning rule by synapse processing circuitry; for instance, for an online STDP learning rule, LTP is performed and a weight is increased by a pre-set delta amount utilizing an adder when a post-neuron spikes later than a pre-neuron within a time window for learning – Sumbul, paragraph 68 [note that pre- and post-neuron spikes are based on input times, including a last input time that causes the neurons to spike; note also that the pre- and post-neurons may be located on any core, including the first core]); or
receive the last spike time from the second internal circuit and to perform long-term depression (LTD) learning based on the last spike time (if a learn signal is received, the weight is updated with the appropriate learning rule by synapse processing circuitry; for instance, for an online STDP learning rule, LTD is performed and the weight is decreased by a pre-set delta amount when the pre-neuron spikes later than the post-neuron [i.e., based on the last spike time] within a time window for learning – Sumbul, paragraph 68 [note that the pre- and post-neurons may be located on any core, including the second core]).”
Sumbul appears not to disclose explicitly the further limitations of the claim. However, Barton discloses “generat[ing a] … value … based on … a lateral suppression signal (output spikes of all CCUs are unioned together by an OR gate to form a single combined spike stream; the output of this OR gate is labeled “ANY,” because a spike is expected to occur at its output [value] so long as it occurs at the FORd output of any CCU [i.e., the gate suppresses any lateral output signal indicating that no spike has occurred at a CCU when there is another, lateral CCU that has spiked] – Barton, p. 5, ll. 16-20) ….”
Barton and the instant application both relate to spiking neural networks and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sumbul to generate a value based on a lateral suppression signal, as disclosed by Barton, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would reduce computational load by allowing several spike signals to be combined into a single signal. See Barton, p. 5, ll. 16-20.
Regarding claim 10, Sumbul, as modified by Barton, discloses that “the online learning circuit includes:
an LTP learning circuit configured to update the plurality of synaptic weights based on the last input time (if a learn signal is received, the weight is updated with the appropriate learning rule by synapse processing circuitry; for instance, for an online STDP learning rule, LTP is performed and a weight is increased [updated] by a pre-set delta amount utilizing an adder when a post-neuron spikes later than a pre-neuron within a time window for learning – Sumbul, paragraph 68 [note that pre- and post-neuron spikes are based on input times, including a last input time that causes the neurons to spike]); and
an LTD learning circuit configured to update the plurality of synaptic weights based on the last spike time (if a learn signal is received, the weight is updated with the appropriate learning rule by synapse processing circuitry; for instance, for an online STDP learning rule, LTD is performed and the weight is decreased [updated] by a pre-set delta amount when the pre-neuron spikes later than the post-neuron [i.e., based on the last spike time] within a time window for learning – Sumbul, paragraph 68).”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sumbul in view of Barton and further in view of Li, “Energy Efficient Spiking Neuromorphic Architectures for Pattern Recognition,” master’s thesis, Texas A&M University (2016) (“Li”).
Regarding claim 9, neither Sumbul nor Barton appears to disclose explicitly the further limitations of the claim. However, Li discloses that “the second internal circuit includes:
a second count register configured to count the last spike time, which is a time elapsed after a spike has finally generated (neuron unit contains three important register files that store, inter alia, the firing [spiking] time stamp [time elapsed since a spike was generated] – Li, p. 29), and
wherein the second count register is further configured to:
reset the last spike time when the spike output signal is '1' (a membrane potential above a threshold means that the corresponding neuron fires and its firing flag S [spike output signal] is set; at the same time, its firing time stamp [last spike time] is recorded as the current biological time t [i.e., reset] – Li, sec. 3.2.1, penultimate paragraph spanning pp. 25-27; see also p. 26, Algorithm 1 (showing that when the membrane potential is above a threshold, the spike output signal S(i) is set to 1 and the firing timestamp Tfire(i) is set to t)).”
Li and the instant application both relate to spiking neural networks and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sumbul and Barton to include a count register that records last spike time and resets when a spike occurs, as disclosed by Li, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would facilitate STDP learning by allowing the system to compare pre- and post-synaptic neuron firing times. See Li, p. 27, first full paragraph.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Barton in view of Sumbul.
Regarding claim 15, Barton discloses “[a] spiking neural network circuit (Barton p. 3, ll. 26-29 indicate that the system is used in spiking neural networks) … comprising:
a plurality of neuron circuits, each of which performs … learning (Barton p. 6, ll. 6-20 describe a series of cross-correlation units (CCUs) [plurality of neuron circuits] each containing a Learn Delay subunit [i.e., each CCU performs learning]) …; and
an OR gate configured to perform an OR operation on a first spike output signal, which is an output of a first neuron circuit, and a second spike output signal, which is an output of a second neuron circuit, with respect to the first neuron circuit and the second neuron circuit, which are adjacent to each other, among the plurality of neuron circuits (Barton Fig. 1 depicts OR gate 0120 performing an OR operation on adjacent outputs FORd of CCUs [first and second neuron circuits]; p. 5, ll. 16-20 show that the output spikes of all CCUs are unioned together by the OR gate to form a single combined spike stream [i.e., the outputs FORd represent spike output signals]).”
Barton appears not to disclose explicitly the further limitations of the claim. However, Sumbul discloses “[a] spiking neural network circuit including one hidden layer (spiking Liquid State Machine may classify MNIST digits with 784 neurons on a visible layer and 512 neurons in a hidden reservoir layer – Sumbul, paragraph 34), the one hidden layer comprising:
a plurality of neuron circuits, each of which performs online learning based on a spike timing dependent plasticity (STDP) algorithm (when an online learning rule such as STDP is implemented, the synapse core may update the weights appropriately when a learn signal is received – Sumbul, paragraph 74; Figs. 3B and 4 depict multiple neurosynaptic cores each containing neuron processing circuitry) ….”
Sumbul and the instant application both relate to spiking neural networks and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Barton to perform online learning using an STDP rule, as disclosed by Sumbul, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow for weight updates to occur in real-time, assuring that the network remains properly updated at all times. See Sumbul, paragraph 74.
Regarding claim 16, Barton, as modified by Sumbul, discloses that “the OR gate [is] configured to generate a lateral suppression signal based on the first spike output signal and the second spike output signal (output spikes of all CCUs are unioned together by an OR gate to form a single combined spike stream; the output of this OR gate is labeled “ANY,” because a spike is expected to occur at its output so long as it occurs at the FORd output of any CCU [i.e., the gate suppresses any lateral output signal indicating that no spike has occurred at a CCU when there is another, lateral CCU that has spiked] – Barton, p. 5, ll. 16-20).”
Regarding claim 17, the rejection of claim 16 is incorporated. Barton further discloses “generat[ing a] … value … based on … a lateral suppression signal (output spikes of all CCUs are unioned together by an OR gate to form a single combined spike stream; the output of this OR gate is labeled “ANY,” because a spike is expected to occur at its output [value] so long as it occurs at the FORd output of any CCU [i.e., the gate suppresses any lateral output signal indicating that no spike has occurred at a CCU when there is another, lateral CCU that has spiked] – Barton, p. 5, ll. 16-20) ….”
Barton appears not to disclose explicitly the further limitations of the claim. However, Sumbul discloses that “each of the plurality of neuron circuits includes:
a first internal circuit configured to receive a plurality of spike input signals, to generate a first sum value by summing a plurality of synaptic weights corresponding to the plurality of spike input signals, and to output a second sum value by adding a membrane potential value to the first sum value (the neuron may perform a function utilizing the values of its inputs and its current membrane potential; for example, the inputs may be added to the current membrane potential of the neuron to generate an updated membrane potential [i.e., if there are two or more inputs, adding each of them to the membrane potential is equivalent to adding the inputs to generate a first sum and adding the sum of the inputs to the existing membrane potential to generate a second sum]; when a neuron spikes, the spike may be propagated to one or more connected neurons residing on the same neuro-synaptic core block [i.e., the inputs are spikes]– Sumbul, paragraph 31; see also Figs. 3B and 4 (showing multiple neurosynaptic cores [including a first internal circuit]));
a spike generating circuit configured to generate a spike output signal by comparing the second sum value with a threshold potential value (neuron may propagate a spike signal to connected neurons when a threshold associated with the neuron is surpassed [i.e., a value is compared with the threshold] – Sumbul, paragraph 2);
a membrane potential generating circuit configured to generate the membrane potential value, which is obtained by subtracting the threshold potential value from the second sum value, based on the spike output signal (see footnote 1 and mapping to the first two limitations of this claim and note that Sumbul paragraph 31 discloses that the membrane potential value is based on the inputs to the neuron and that the inputs are spikes output from other neurons, i.e., the membrane potential value is based on the spike output signal) …;
a second internal circuit configured to count a last spike time based on the spike output signal (neuron core [internal circuit] may track spike timing [count a last spike time, based on the spike] if online learning is implemented and send out appropriate learn signals – Sumbul, paragraph 75; see also Fig. 3B (showing that there are multiple neurosynaptic cores, i.e., multiple internal circuits)); and
an online learning circuit configured to:
receive a last input time from the first internal circuit and perform LTP learning based on the last input time (if a learn signal is received, the weight is updated with the appropriate learning rule by synapse processing circuitry; for instance, for an online STDP learning rule, LTP is performed and a weight is increased by a pre-set delta amount utilizing an adder when a post-neuron spikes later than a pre-neuron within a time window for learning – Sumbul, paragraph 68 [note that pre- and post-neuron spikes are based on input times, including a last input time that causes the neurons to spike; note also that the pre- and post-neurons may be located on any core, including the first core]); or
receive the last spike time from the second internal circuit and to perform LTD learning based on the last spike time (if a learn signal is received, the weight is updated with the appropriate learning rule by synapse processing circuitry; for instance, for an online STDP learning rule, LTD is performed and the weight is decreased by a pre-set delta amount when the pre-neuron spikes later than the post-neuron [i.e., based on the last spike time] within a time window for learning – Sumbul, paragraph 68 [note that the pre- and post-neurons may be located on any core, including the second core]).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Barton to utilize the above-described architecture, as disclosed by Sumbul, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the system efficiently to support different types of neural networks with opposing resource requirements by providing reconfigurable resources to perform as neurons or synapses depending onf the target network type. See Sumbul, paragraph 37.
Allowable Subject Matter
Claims 2-8 and 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (all references disclose spiking neural networks with similar architectures):
Beidas et al. (US 20230100670);
Linares-Barranco et al. (US 11301753);
Chen et al. (US 20190197391).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C VAUGHN whose telephone number is (571)272-4849. The examiner can normally be reached M-R 7:00a-5:00p ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamran Afshar can be reached at 571-272-7796. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN C VAUGHN/ Primary Examiner, Art Unit 2125
1 This limitation adds nothing to the claim because it follows mathematically from the previous limitations. Let S1 be the first sum value, S2 be the second sum value, MP be the membrane potential, and T be the threshold potential value. The first limitation says essentially that S2 = S1 + MP, or equivalently, MP = S2 – S1. This limitation states that MP = S2 – T. Substituting the first equation into the second, S2 – T = S2 – S1, or in other words, T = S1. But if this is the case, then this limitation merely states something mathematically equivalent to what was already stated in the first limitation, with the language “threshold potential value” substituted for “first sum value”.
Prosecution Insights