DETAILED ACTION
Claims 1-20 are presented for examination.
Claim 17 remains canceled.
This office action is in response to RCE of application on 28-AUGUST-2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 28-AUGUST-2026 has been entered.
Response to Arguments
Applicant's arguments filed 28-AUGUST-2026 have been fully considered but they are not persuasive.
1. Regarding Applicant’s arguments that the Herdrich reference teaches overriding a lock and thereby permitting use of a region by a higher priority requester, and therefore cannot teach that the cache region is not allocable to another requester, as claimed in the independent claims, Examiner respectfully disagrees. As discussed in the previous office action, there is nothing in the claim which says that the cache region is not allocable in response to every single request from every other requester. The broadest reasonable interpretation of “not allocable to another requester to prevent eviction of data from the region by the other requester” encompasses any system in which one region is allocated to one requester, and there exists at least one other requester in the system which that region is not allocable to. As discussed in the previous office action, Herdrich does teach that there are scenarios in which a request from another requester will not override the lock, and the request would be denied. Therefore, Herdrich meets the requirements of this limitation. Examiner also notes more generally that, given the broadest reasonable interpretation of the claim element, merely pointing out a special case in only one embodiment which Herdrich does teach overriding the lock is insufficient to prove that Herdrich does not teach non-allocability.
2. Examiner further notes that even if Applicant amended the independent claim or if Examiner and Applicant were to otherwise accept the interpretation which Applicant relies on to attack the Herdrich reference, such an interpretation would render the instant application self-contradictory, as claim 19 contains the limitation of “the memory controller accepting the request based at least on the request being associated with a higher priority level than a priority level of the requester associated with the portion of the region”, while depending on claims 15/14 which contain the same “the region is not allocable to another requester” limitation argued by the applicant. In other words, in a narrow interpretation where “the region is not allocable to another requester” means denying the request in every single case, the requirement to deny the request in every single case would contradict with claim 19 which accepts the request in a certain case instead. Examiner notes that Examiner’s interpretation of the claim element for rejecting over prior art is further supported in [0013] of the instant specification which clearly describes that “exclusive allocation” may allow for a region of memory allocated for a low/medium priority request to be received by and allocated to a higher priority request.
3. Examiner further notes that even if Applicant were to amend the claim to positively recite that “the region is not allocable to another requester” means denying all requests to an allocated region, and Applicant were to cancel claim 19 to remove such a conflict, this would still not overcome the Herdrich reference. Herdrich only appears to only teach the priority-based override as one potential example embodiment, and that the cache locking on a purely first-come-first-served basis is also a valid potential example embodiment of Herdrich (see Herdrich [0056] and [0068]). Herdrich does not teach that the invention of Herdrich absolutely requires the priority-based override, and therefore reducing the teachings of Herdrich down to only using the priority-based override when alternatives without the priority-based override are taught would be an unreasonably narrow interpretation of Herdrich.
4. Regarding Applicant’s arguments that the amendments to claim 19 overcome the rejection, Examiner respectfully disagrees. The claim still contains several potential conflicting elements which render the relationship between “the region”, “the requester” and “the request” unclear. For example, Claim 14 recites “exclusively allocating a region of a near memory tier… to a requester”; Claim 15 recites “allocating the region (same region as in claim 14) of the near memory tier… based on receipt of a request”; Claim 19 recites “accepting the request based on the request (both requests being the same as in claim 15) being associated with a higher priority level than a priority level of the requester associated with the portion of the region (“the requester” meaning the same requester in claim 14 or a new requester lacking antecedent basis?). The claim limitations remain unclear regarding the exact relationship between “the region”, “the request”, and “the requester”, and regarding the existence of a new “requester” distinct from the requester from claim 14. Examiner notes that clarifying labels such as “first” and “second” could be used to better distinguish and distinctly claim any differing elements of the same type, and to clarify which of the elements are the same across all claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 19: in claim 14 lines 4-7 and in claim 15 lines 1-3 (which claim 19 depends on), the claims recite only one allocation region, which “the region” can refer back to. In claim 14 line 5 and claim 15 lines 2-3, there is also only one recited requester which the region is allocated to. In claim 15, there is also the recitation of “a request”, which is understood to be the request that caused the allocation of the region described in claim 14. However, claim 19 lines 3-5 recite “the request” and “the requester associated with the portion of the region”. It is unclear whether this newly recited “the requester associated with the portion of the region” is the same requester as the previously recited “requester” recited in claims 14-15, or if this is meant to refer to a different requester from the ones described in claims 14-15, such as a requester which the portion of the region is reserved for in claim 19 line 2. Further, it is unclear whether “the request” in claim 19 line 3 is meant to be the same request in claim 15 overriding the allocation of a different previous “a requester associated with the portion of the region”, or if “the request” of claim 19 is meant to be a new request for the same region to override the allocation of claims 14 and 15.
Examiner requests language to specifically clarify which requests, requesters, and region are referred to between claims 14, 15, and 19.
For the purposes of examining over prior art, claim 19 is interpreted to be referring to the same allocation corresponding to the same single requester making a single request, such that claims 19 and 15 are merely additional modifiers on how the one allocation in claim 14 is performed, and the “a requester associated with the portion of the region” is interpreted to be a requester which the portion of the region is already allocated/reserved for prior to this single allocation process of claims 14, 15, and 19, which corresponds to the portion of the region of the memory tier which is reserved in claim 19 line 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Erickson et al., U.S. Pub. No. 20220179799 (hereinafter “Erickson”) in view of
HERDRICH et al., U.S. Pub. No. 20190340123 (hereinafter “Herdrich”)
Regarding claim 1: Erickson teaches An apparatus comprising:
a memory controller, when connected to at least one memory device in a multi-tiered memory system comprising a near memory and far memory, is to allocate a region of the near memory to a requester based on receipt of a request, wherein ([0017-0018], Erickson teaches a set of memory control components that are connected to memory devices, and contains an access/allocation engine which coordinates memory pages allocated to processes, and receives memory allocation requests. The memory control components also teach a far memory, in the form of an auxiliary remote, MV-attached memory 116, that is separate to a local memory subsystem 115.).
circuitry to transmit at least one memory read command and address information associated with the at least one memory read command to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system, wherein ([0018], Erickson teaches that the access/allocation engine also responds to loads/stores directed to MV-attached memory by issuing corresponding signals to an auxiliary memory, including a fabric interface which transmits memory load/store instructions. Furthermore, in [0022], Erickson teaches that a process issues load/stores to a virtual address, which means that the address information is associated with the load request. Therefore, the circuitry to transmit at least one memory read (load) command and address information to read data from the system, and to transmit at least one memory write (store) command and address information to the memory system to write data is taught.)
the near memory comprises at least one memory connected to the memory controller via a memory interface and the far memory comprises at least one memory connected to the memory controller and accessible by an Ethernet packet via a network. ([0016], Erickson teaches that memory access requests are routed to local or remote memory, the remote memory including operating memory on servers other than the requesting server. Furthermore, [0017], Erickson teaches a memory subsystem coupled to a memory control unit via traces, within a server, which corresponds to the local memory and is interpreted to be the near memory comprising memory connected to the memory controller via a memory interface. While not explicit, in light of [0017], where Erickson teaches a network interface card that enables connection to a communication network, to enable data transport, the remote memory belonging on other servers and having a network of servers where access is allowed to be transmitted across teaches the far memory connected to the memory controller via a network, and that the physical interconnect and protocol suite used for that data transport may be Ethernet. With the protocol used for all data transports being Ethernet, all data transports via the network are interpreted to be by Ethernet packets.)
Erickson does not appear to explicitly disclose the region is allocated exclusively to a particular requester and not allocable to another requester to prevent eviction of data from the region by the another requester
However, Herdrich teaches the region is allocated exclusively to a particular requester and not allocable to another requester to prevent eviction of data from the region by the another requester ([0059-0060] and [0068], Herdrich teaches that the controller can grant or deny a request to lock a region, and describes priority considerations for whether it is granted when a region is already locked by an application. Since requests in an embodiment are only granted in certain conditions, and requests are either granted or denied, it is obvious that the request for the already-locked region may be denied when the conditions are not met, and therefore, target region of the request is not allocable to the particular requester that is different from the particular requester that already has a lock on the region.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of the system which allocates a region of near memory, to do so exclusively such that it is not allocable to another requester.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 2: The combination of Erickson and Herdrich teaches all limitations of claim 1, from which claim 2 depends.
Erickson/Herdrich further teaches the memory controller is to allocate the region of the near memory to the requester based on priority of the request. ([0065-0068], Herdrich teaches that an application can request locking (corresponding to allocating) of a cache region including a lowest level cache (corresponding to the near memory), and that the request can be granted or denied, with an embodiment being that the locking can be provided based on the priority of an application that requests cache locking.).
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 1.
Regarding claim 3: The combination of Erickson and Herdrich teaches all limitations of claim 1, from which claim 3 depends.
Erickson/Herdrich further teaches to allocate the region of the near memory to the requester, a processor-executed operating system (OS) is to configure the memory controller to provide access to the region of the near memory to the requester and no other requester ([0019], Erickson teaches that an allocation scheme invokes a local operating system’s page-fault handler to map addresses, and that the LPAs are issued by the CPU’s memory management unit and directed to a local memory controller, in which the LPA may decode to a page of local memory. The overall allocation scheme involving the execution of an operating system, to a local memory controller, which decodes to local memory, is interpreted to be the claimed processor-executed operating system configuring a memory controller to provide access to the region of the near memory to the requester. Furthermore, in [0042] and Table 2, Herdrich teaches that for a cache allocation, a set of fields in an input can be used. One of the fields includes an Access/Level field which sets an allocation to be private or public, wherein when it is private, there will be a protection fault upon illegal access by other threads in the group. The illegal access causing a protection fault from other threads is interpreted to be the providing access to no other service)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 1.
Regarding claim 4: The combination of Erickson and Herdrich teaches all limitations of claim 1, from which claim 4 depends.
Erickson/Herdrich teaches the memory controller is to selectively deny the request based on a portion of the region of the near memory being reserved for another requester ([0057], Herdrich teaches that, as part of a process to permit or deny cache locking (reserving), the controller declines a request from an application if part of the region is not available. Furthermore, in [0029], Herdrich teaches a table that tracks which portions of a cache system are occupied and what is available for locking or occupation. Since the occupied portions are described separately to the portions that are available, and the controller declines requests for a region that is not available, and that the portions that are occupied are obviously not available, Herdrich teaches the selectively denying the request based on the portion of the memory tier being reserved for another requester.).
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 1.
Regarding claim 5: The combination of Erickson and Herdrich teaches all limitations of claim 1, from which claim 5 depends.
Erickson/Herdrich further teaches the request comprises three or more of: requester identifier, amount of memory to reserve, tier of memory in which to reserve memory, level of priority of the requester, and/or latency sensitivity of the requester. ([0023], Erickson teaches that to fulfill memory allocation requests from local CPUs, a parametrized request specifying memory location (tier of memory in which to reserve) and average access latency characteristics desired by the requester (latency sensitivity), and that during fulfillment, the process identifier for the process that triggered the allocation is stored (requester identifier).)
Regarding claim 6: The combination of Erickson and Herdrich teaches all limitations of claim 1, from which claim 6 depends.
Erickson/Herdrich further teaches the multi-tiered memory system comprises one or more of: a volatile memory device and/or a non-volatile memory device. ([0017], Erickson teaches that the memory subsystem used in an example embodiment may be dynamic random access memory (DRAM), which is known in the art to be a type of volatile memory.)
Regarding claim 7: The combination of Erickson and Herdrich teaches all limitations of claim 1, from which claim 7 depends.
Erickson/Herdrich further teaches a server comprising at least one processor communicatively coupled to the memory controller, wherein the at least one processor is to execute an operating system (OS) to configure the memory controller to provide access to the region of the near memory to the requester. ([0017], Erickson teaches that each example server contains a CPU which performs the memory management. Further, in [0019], Erickson teaches that an allocation scheme invokes a local operating system’s page-fault handler to map addresses, and that the LPAs are issued by the CPU’s memory management unit and directed to a local memory controller, in which the LPA may decode to a page of local memory. The CPU directing LPAs, which are part of an overall allocation scheme involving the execution of an operating system, to a local memory controller, which decodes to local memory, is interpreted to be the claimed processor coupled to the memory controller, wherein an operating system configures a memory controller to provide access to the region of the near memory to the requester.
Regarding claim 8: Erickson teaches At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: ([0041-0042], Erickson teaches one or more computer readable media with instructions that can be processed by a processing entity to perform the invention.)
Erickson further teaches execute an operating system (OS) to configure a memory controller, when connected to at least one memory device in a multi-tiered memory system, to exclusively allocate a region of a near memory tier to a requester based on a request from the OS. ([0019], Erickson teaches that an allocation scheme invokes a local operating system’s page-fault handler to map addresses, and that the LPAs (which define a region) are issued by the CPU’s memory management unit and directed to a local memory controller, in which the LPA may decode to a page of local memory. Further, in [0017], Erickson teaches that the system includes a local operating memory and an auxiliary memory, interpreted to be the multi-tiered memory system. The CPU directing LPAs, which are part of an overall allocation scheme involving the execution of an operating system, to a local memory controller, which decodes to local memory, is interpreted to be the claimed execute an operating system (OS) to configure a memory controller, when connected to at least one memory device in a multi-tiered memory system, to allocate a region of a near memory tier to a requester based on a request from the OS. Furthermore, in [0021-0023], Erickson describes the process of allocating involves finding only memory that is free to be allocated to assign specifically to a process that triggers a fault, which is interpreted to mean that the allocated memory is exclusive to that process, as other processes would be given different free memory.)
Erickson does not appear to explicitly disclose the region is not allocable to another requester to prevent eviction of data from the region by the another requester
However, Herdrich teaches the region is not allocable to another requester to prevent eviction of data from the region by the another requester ([0059-0060] and [0068], Herdrich teaches that the controller can grant or deny a request to lock a region, and describes priority considerations for whether it is granted when a region is already locked by an application. Since requests in an embodiment are only granted in certain conditions, and requests are either granted or denied, it is obvious that the request for the already-locked region may be denied when the conditions are not met, and therefore, target region of the request is not allocable to the particular requester that is different from the particular requester that already has a lock on the region.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of the system which allocates a region of near memory, to do so exclusively such that it is not allocable to another requester.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 9: The combination of Erickson and Herdrich teaches all limitations of claim 8, from which claim 9 depends.
Erickson/Herdrich further teaches circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system. ([0018], Erickson teaches an access/allocation engine that responds to loads/stores directed to MV-attached memory by issuing corresponding signals to an auxiliary memory, including a fabric interface which transmits memory load/store instructions. Furthermore, in [0022], Erickson teaches that a process issues load/stores to a virtual address. Therefore, the circuitry to transmit at least one memory read (load) command and address information to read data from the system, and to transmit at least one memory write (store) command and address information to the memory system to write data is taught.)
Regarding claim 10: The combination of Erickson and Herdrich teaches all limitations of claim 8, from which claim 10 depends.
Erickson/Herdrich further teaches to allocate a region of a near memory tier to the requester based on a request from the OS, the OS is to configure the memory controller to provide access to the region of the memory tier to the requester and no other requester ([0019], Erickson teaches that an allocation scheme invokes a local operating system’s page-fault handler to map addresses, and that the LPAs are issued by the CPU’s memory management unit and directed to a local memory controller, in which the LPA may decode to a page of local memory. The overall allocation scheme involving the execution of an operating system, to a local memory controller, which decodes to local memory, is interpreted to be the claimed processor-executed operating system configuring a memory controller to provide access to the region of the near memory to the requester. Further, in [0042] and Table 2, Herdrich teaches that for a cache allocation, a set of fields in an input can be used. One of the fields includes an Access/Level field which sets an allocation to be private or public, wherein when it is private, there will be a protection fault upon illegal access by other threads in the group. The illegal access causing a protection fault from other threads is interpreted to be the providing access to no other service.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 8.
Regarding claim 11: The combination of Erickson and Herdrich teaches all limitations of claim 8, from which claim 11 depends.
Erickson/Herdrich further teaches the multi-tiered memory system comprises the near memory tier and a far memory tier and wherein the near memory tier is to provide a lower latency of data retrieval and/or higher bandwidth of data retrieval than that of the far memory tier. ([0019], Erickson teaches that memory-pooling servers can include hierarchically accessed storage devices, where the local (near memory tier) memory implements high bandwidth, low latency operating memory, and where the auxiliary (far memory tier) memory has a higher latency than the local memory.)
Regarding claim 12: The combination of Erickson and Herdrich teaches all limitations of claim 8, from which claim 12 depends.
Erickson/Herdrich further teaches the memory controller is to selectively deny the request based on a portion of the region of the memory tier being reserved ([0057], Herdrich teaches that, as part of a process to permit or deny cache locking (reserving), the controller declines a request from an application if part of the region is not available. Furthermore, in [0029], Herdrich teaches a table that tracks which portions of a cache system are occupied and what is available for locking or occupation. While not explicit, since the occupied portions are described separately to the portions that are available, and the controller declines requests for a region that is not available, and that the portions that are occupied are obviously not available, Herdrich teaches the selectively denying the request based on the portion of the memory tier being reserved for another requester.).
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 8.
Regarding claim 13: The combination of Erickson and Herdrich teaches all limitations of claim 8, from which claim 13 depends.
Erickson further teaches the request comprises one or more of: requester identifier, amount of memory to reserve, tier of memory in which to reserve memory, level of priority of the requester, and/or latency sensitivity of the requester. ([0023], Erickson teaches that to fulfill memory allocation requests from local CPUs, a parametrized request specifying memory location, and that during fulfillment, the process identifier for the process that triggered the allocation is stored.)
Regarding claim 14: Erickson teaches A method comprising:
in a data center comprising at least one processor, a memory controller, and a multi-tiered memory system: the memory controller exclusively allocating a region of a near memory tier of the multi-tiered memory system to a requester based on receipt of a request, ([0017-0018], Erickson teaches a data center with servers, which each contain a set of memory control components that are connected to memory devices, and contains an access/allocation engine which coordinates memory pages allocated to processes, and receives memory allocation requests. The memory control components also teach a far memory, in the form of an auxiliary remote, MV-attached memory 116, that is separate to a local memory subsystem 115. Furthermore, in [0021-0023], Erickson describes the process of allocating involves finding only memory that is free to be allocated to assign specifically to a process that triggers a fault, which is interpreted to mean that the allocated memory is exclusive to that process, as other processes would be given different free memory.).
circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system, wherein ([0018], Erickson teaches that the access/allocation engine also responds to loads/stores directed to MV-attached memory by issuing corresponding signals to an auxiliary memory, including a fabric interface which transmits memory load/store instructions. Furthermore, in [0022], Erickson teaches that a process issues load/stores to a virtual address. Therefore, the circuitry to transmit at least one memory read (load) command and address information to read data from the system, and to transmit at least one memory write (store) command and address information to the memory system to write data is taught.)
the near memory tier comprises at least one memory connected to the memory controller via a memory interface. (Furthermore, [0017], Erickson teaches a memory subsystem coupled to a memory control unit via traces, within a server, which corresponds to the local memory and is interpreted to be the near memory comprising memory connected to the memory controller via a memory interface.)
Erickson does not appear to explicitly disclose the region is not allocable to another requester to prevent eviction of data from the region by the another requester
However, Herdrich teaches the region is not allocable to another requester to prevent eviction of data from the region by the another requester ([0059-0060] and [0068], Herdrich teaches that the controller can grant or deny a request to lock a region, and describes priority considerations for whether it is granted when a region is already locked by an application. Since requests in an embodiment are only granted in certain conditions, and requests are either granted or denied, it is obvious that the request for the already-locked region may be denied when the conditions are not met, and therefore, target region of the request is not allocable to the particular requester that is different from the particular requester that already has a lock on the region.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of the system which allocates a region of near memory, to do so exclusively such that it is not allocable to another requester.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 15: The combination of Erickson and Herdrich teaches all limitations of claim 14, from which claim 15 depends.
Erickson/Herdrich further teaches the memory controller allocating the region of the near memory tier of the multi-tiered memory system to the requester based on receipt of a request is based on a priority level of the request. ([0065-0068], Herdrich teaches that an application can request locking (corresponding to allocating) of a cache region including a lowest level cache (corresponding to the near memory), and that the request can be granted or denied, with an embodiment being that the locking can be provided based on the priority of an application that requests cache locking.).
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 14.
Regarding claim 16: The combination of Erickson and Herdrich teaches all limitations of claim 14, from which claim 16 depends.
Erickson/Herdrich further teaches the multi-tiered memory system comprises the near memory tier and a far memory tier and wherein the near memory tier is to provide a lower latency of data retrieval and/or higher bandwidth of data retrieval than that of the far memory tier. ([0019], Erickson teaches that memory-pooling servers can include hierarchically accessed storage devices, where the local (near memory tier) memory implements high bandwidth, low latency operating memory, and where the auxiliary (far memory tier) memory has a higher latency than the local memory.)
Regarding claim 18: The combination of Erickson and Herdrich teaches all limitations of claim 15, from which claim 18 depends.
Erickson/Herdrich further teaches the memory controller selectively denying the request based on a portion of the region of the memory tier being reserved. ([0057], Herdrich teaches that, as part of a process to permit or deny cache locking (reserving), the controller declines a request from an application if part of the region is not available. Furthermore, in [0029], Herdrich teaches a table that tracks which portions of a cache system are occupied and what is available for locking or occupation. While not explicit, since the occupied portions are described separately to the portions that are available, and the controller declines requests for a region that is not available, and that the portions that are occupied are obviously not available, Herdrich teaches the selectively denying the request based on the portion of the memory tier being reserved for another requester.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 15.
Regarding claim 19: The combination of Erickson and Herdrich teaches all limitations of claim 15, from which claim 19 depends.
Erickson/Herdrich further teaches based on a portion of the region of the memory tier being reserved, the memory controller accepting the request based at least on the request being associated with a higher priority level than a priority level of a requester associated with the portion of the region. ([0067], Herdrich teaches an embodiment where the cache controller can provide cache locking based on the priority of an application that requests cache locking, which may cause the eviction of locked content of another application, with an example that a request from a higher priority application can cause the eviction of content from a lower priority application. The cache controller providing the cache locking in this scenario is interpreted to be the claimed memory controller accepting the request.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 15.
Regarding claim 20: The combination of Erickson and Herdrich teaches all limitations of claim 15, from which claim 20 depends.
Erickson/Herdrich further teaches the request comprises one or more of: requester identifier, amount of memory to reserve, tier of memory in which to reserve memory, level of priority of the requester, and/or latency sensitivity of the requester. ([0023], Erickson teaches that to fulfill memory allocation requests from local CPUs, a parametrized request specifying memory location, and that during fulfillment, the process identifier for the process that triggered the allocation is stored.)
Conclusion
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
